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ARM: meson: dts: add basic Meson/Meson6/Meson6-atv1200 DTSI/DTS
[deliverable/linux.git] / arch / arm / boot / dts / dra7.dtsi
1 /*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
9
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/dra.h>
12
13 #include "skeleton.dtsi"
14
15 #define MAX_SOURCES 400
16 #define DIRECT_IRQ(irq) (MAX_SOURCES + irq)
17
18 / {
19 #address-cells = <1>;
20 #size-cells = <1>;
21
22 compatible = "ti,dra7xx";
23 interrupt-parent = <&gic>;
24
25 aliases {
26 i2c0 = &i2c1;
27 i2c1 = &i2c2;
28 i2c2 = &i2c3;
29 i2c3 = &i2c4;
30 i2c4 = &i2c5;
31 serial0 = &uart1;
32 serial1 = &uart2;
33 serial2 = &uart3;
34 serial3 = &uart4;
35 serial4 = &uart5;
36 serial5 = &uart6;
37 };
38
39 timer {
40 compatible = "arm,armv7-timer";
41 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
42 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
43 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
44 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
45 };
46
47 gic: interrupt-controller@48211000 {
48 compatible = "arm,cortex-a15-gic";
49 interrupt-controller;
50 #interrupt-cells = <3>;
51 arm,routable-irqs = <192>;
52 reg = <0x48211000 0x1000>,
53 <0x48212000 0x1000>,
54 <0x48214000 0x2000>,
55 <0x48216000 0x2000>;
56 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
57 };
58
59 /*
60 * The soc node represents the soc top level view. It is used for IPs
61 * that are not memory mapped in the MPU view or for the MPU itself.
62 */
63 soc {
64 compatible = "ti,omap-infra";
65 mpu {
66 compatible = "ti,omap5-mpu";
67 ti,hwmods = "mpu";
68 };
69 };
70
71 /*
72 * XXX: Use a flat representation of the SOC interconnect.
73 * The real OMAP interconnect network is quite complex.
74 * Since it will not bring real advantage to represent that in DT for
75 * the moment, just use a fake OCP bus entry to represent the whole bus
76 * hierarchy.
77 */
78 ocp {
79 compatible = "ti,dra7-l3-noc", "simple-bus";
80 #address-cells = <1>;
81 #size-cells = <1>;
82 ranges;
83 ti,hwmods = "l3_main_1", "l3_main_2";
84 reg = <0x44000000 0x1000000>,
85 <0x45000000 0x1000>;
86 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
87 <GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH>;
88
89 prm: prm@4ae06000 {
90 compatible = "ti,dra7-prm";
91 reg = <0x4ae06000 0x3000>;
92
93 prm_clocks: clocks {
94 #address-cells = <1>;
95 #size-cells = <0>;
96 };
97
98 prm_clockdomains: clockdomains {
99 };
100 };
101
102 axi@0 {
103 compatible = "simple-bus";
104 #size-cells = <1>;
105 #address-cells = <1>;
106 ranges = <0x51000000 0x51000000 0x3000
107 0x0 0x20000000 0x10000000>;
108 pcie@51000000 {
109 compatible = "ti,dra7-pcie";
110 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
111 reg-names = "rc_dbics", "ti_conf", "config";
112 interrupts = <0 232 0x4>, <0 233 0x4>;
113 #address-cells = <3>;
114 #size-cells = <2>;
115 device_type = "pci";
116 ranges = <0x81000000 0 0 0x03000 0 0x00010000
117 0x82000000 0 0x20013000 0x13000 0 0xffed000>;
118 #interrupt-cells = <1>;
119 num-lanes = <1>;
120 ti,hwmods = "pcie1";
121 phys = <&pcie1_phy>;
122 phy-names = "pcie-phy0";
123 interrupt-map-mask = <0 0 0 7>;
124 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
125 <0 0 0 2 &pcie1_intc 2>,
126 <0 0 0 3 &pcie1_intc 3>,
127 <0 0 0 4 &pcie1_intc 4>;
128 pcie1_intc: interrupt-controller {
129 interrupt-controller;
130 #address-cells = <0>;
131 #interrupt-cells = <1>;
132 };
133 };
134 };
135
136 axi@1 {
137 compatible = "simple-bus";
138 #size-cells = <1>;
139 #address-cells = <1>;
140 ranges = <0x51800000 0x51800000 0x3000
141 0x0 0x30000000 0x10000000>;
142 status = "disabled";
143 pcie@51000000 {
144 compatible = "ti,dra7-pcie";
145 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
146 reg-names = "rc_dbics", "ti_conf", "config";
147 interrupts = <0 355 0x4>, <0 356 0x4>;
148 #address-cells = <3>;
149 #size-cells = <2>;
150 device_type = "pci";
151 ranges = <0x81000000 0 0 0x03000 0 0x00010000
152 0x82000000 0 0x30013000 0x13000 0 0xffed000>;
153 #interrupt-cells = <1>;
154 num-lanes = <1>;
155 ti,hwmods = "pcie2";
156 phys = <&pcie2_phy>;
157 phy-names = "pcie-phy0";
158 interrupt-map-mask = <0 0 0 7>;
159 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
160 <0 0 0 2 &pcie2_intc 2>,
161 <0 0 0 3 &pcie2_intc 3>,
162 <0 0 0 4 &pcie2_intc 4>;
163 pcie2_intc: interrupt-controller {
164 interrupt-controller;
165 #address-cells = <0>;
166 #interrupt-cells = <1>;
167 };
168 };
169 };
170
171 cm_core_aon: cm_core_aon@4a005000 {
172 compatible = "ti,dra7-cm-core-aon";
173 reg = <0x4a005000 0x2000>;
174
175 cm_core_aon_clocks: clocks {
176 #address-cells = <1>;
177 #size-cells = <0>;
178 };
179
180 cm_core_aon_clockdomains: clockdomains {
181 };
182 };
183
184 cm_core: cm_core@4a008000 {
185 compatible = "ti,dra7-cm-core";
186 reg = <0x4a008000 0x3000>;
187
188 cm_core_clocks: clocks {
189 #address-cells = <1>;
190 #size-cells = <0>;
191 };
192
193 cm_core_clockdomains: clockdomains {
194 };
195 };
196
197 counter32k: counter@4ae04000 {
198 compatible = "ti,omap-counter32k";
199 reg = <0x4ae04000 0x40>;
200 ti,hwmods = "counter_32k";
201 };
202
203 dra7_ctrl_general: tisyscon@4a002e00 {
204 compatible = "syscon";
205 reg = <0x4a002e00 0x7c>;
206 };
207
208 pbias_regulator: pbias_regulator {
209 compatible = "ti,pbias-omap";
210 reg = <0 0x4>;
211 syscon = <&dra7_ctrl_general>;
212 pbias_mmc_reg: pbias_mmc_omap5 {
213 regulator-name = "pbias_mmc_omap5";
214 regulator-min-microvolt = <1800000>;
215 regulator-max-microvolt = <3000000>;
216 };
217 };
218
219 dra7_pmx_core: pinmux@4a003400 {
220 compatible = "ti,dra7-padconf", "pinctrl-single";
221 reg = <0x4a003400 0x0464>;
222 #address-cells = <1>;
223 #size-cells = <0>;
224 #interrupt-cells = <1>;
225 interrupt-controller;
226 pinctrl-single,register-width = <32>;
227 pinctrl-single,function-mask = <0x3fffffff>;
228 };
229
230 sdma: dma-controller@4a056000 {
231 compatible = "ti,omap4430-sdma";
232 reg = <0x4a056000 0x1000>;
233 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
234 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
235 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
236 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
237 #dma-cells = <1>;
238 #dma-channels = <32>;
239 #dma-requests = <127>;
240 };
241
242 gpio1: gpio@4ae10000 {
243 compatible = "ti,omap4-gpio";
244 reg = <0x4ae10000 0x200>;
245 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
246 ti,hwmods = "gpio1";
247 gpio-controller;
248 #gpio-cells = <2>;
249 interrupt-controller;
250 #interrupt-cells = <2>;
251 };
252
253 gpio2: gpio@48055000 {
254 compatible = "ti,omap4-gpio";
255 reg = <0x48055000 0x200>;
256 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
257 ti,hwmods = "gpio2";
258 gpio-controller;
259 #gpio-cells = <2>;
260 interrupt-controller;
261 #interrupt-cells = <2>;
262 };
263
264 gpio3: gpio@48057000 {
265 compatible = "ti,omap4-gpio";
266 reg = <0x48057000 0x200>;
267 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
268 ti,hwmods = "gpio3";
269 gpio-controller;
270 #gpio-cells = <2>;
271 interrupt-controller;
272 #interrupt-cells = <2>;
273 };
274
275 gpio4: gpio@48059000 {
276 compatible = "ti,omap4-gpio";
277 reg = <0x48059000 0x200>;
278 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
279 ti,hwmods = "gpio4";
280 gpio-controller;
281 #gpio-cells = <2>;
282 interrupt-controller;
283 #interrupt-cells = <2>;
284 };
285
286 gpio5: gpio@4805b000 {
287 compatible = "ti,omap4-gpio";
288 reg = <0x4805b000 0x200>;
289 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
290 ti,hwmods = "gpio5";
291 gpio-controller;
292 #gpio-cells = <2>;
293 interrupt-controller;
294 #interrupt-cells = <2>;
295 };
296
297 gpio6: gpio@4805d000 {
298 compatible = "ti,omap4-gpio";
299 reg = <0x4805d000 0x200>;
300 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
301 ti,hwmods = "gpio6";
302 gpio-controller;
303 #gpio-cells = <2>;
304 interrupt-controller;
305 #interrupt-cells = <2>;
306 };
307
308 gpio7: gpio@48051000 {
309 compatible = "ti,omap4-gpio";
310 reg = <0x48051000 0x200>;
311 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
312 ti,hwmods = "gpio7";
313 gpio-controller;
314 #gpio-cells = <2>;
315 interrupt-controller;
316 #interrupt-cells = <2>;
317 };
318
319 gpio8: gpio@48053000 {
320 compatible = "ti,omap4-gpio";
321 reg = <0x48053000 0x200>;
322 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
323 ti,hwmods = "gpio8";
324 gpio-controller;
325 #gpio-cells = <2>;
326 interrupt-controller;
327 #interrupt-cells = <2>;
328 };
329
330 uart1: serial@4806a000 {
331 compatible = "ti,omap4-uart";
332 reg = <0x4806a000 0x100>;
333 interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
334 ti,hwmods = "uart1";
335 clock-frequency = <48000000>;
336 status = "disabled";
337 };
338
339 uart2: serial@4806c000 {
340 compatible = "ti,omap4-uart";
341 reg = <0x4806c000 0x100>;
342 interrupts-extended = <&gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
343 ti,hwmods = "uart2";
344 clock-frequency = <48000000>;
345 status = "disabled";
346 };
347
348 uart3: serial@48020000 {
349 compatible = "ti,omap4-uart";
350 reg = <0x48020000 0x100>;
351 interrupts-extended = <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
352 ti,hwmods = "uart3";
353 clock-frequency = <48000000>;
354 status = "disabled";
355 };
356
357 uart4: serial@4806e000 {
358 compatible = "ti,omap4-uart";
359 reg = <0x4806e000 0x100>;
360 interrupts-extended = <&gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
361 ti,hwmods = "uart4";
362 clock-frequency = <48000000>;
363 status = "disabled";
364 };
365
366 uart5: serial@48066000 {
367 compatible = "ti,omap4-uart";
368 reg = <0x48066000 0x100>;
369 interrupts-extended = <&gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
370 ti,hwmods = "uart5";
371 clock-frequency = <48000000>;
372 status = "disabled";
373 };
374
375 uart6: serial@48068000 {
376 compatible = "ti,omap4-uart";
377 reg = <0x48068000 0x100>;
378 interrupts-extended = <&gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
379 ti,hwmods = "uart6";
380 clock-frequency = <48000000>;
381 status = "disabled";
382 };
383
384 uart7: serial@48420000 {
385 compatible = "ti,omap4-uart";
386 reg = <0x48420000 0x100>;
387 interrupts-extended = <&gic GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
388 ti,hwmods = "uart7";
389 clock-frequency = <48000000>;
390 status = "disabled";
391 };
392
393 uart8: serial@48422000 {
394 compatible = "ti,omap4-uart";
395 reg = <0x48422000 0x100>;
396 interrupts-extended = <&gic GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
397 ti,hwmods = "uart8";
398 clock-frequency = <48000000>;
399 status = "disabled";
400 };
401
402 uart9: serial@48424000 {
403 compatible = "ti,omap4-uart";
404 reg = <0x48424000 0x100>;
405 interrupts-extended = <&gic GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
406 ti,hwmods = "uart9";
407 clock-frequency = <48000000>;
408 status = "disabled";
409 };
410
411 uart10: serial@4ae2b000 {
412 compatible = "ti,omap4-uart";
413 reg = <0x4ae2b000 0x100>;
414 interrupts-extended = <&gic GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
415 ti,hwmods = "uart10";
416 clock-frequency = <48000000>;
417 status = "disabled";
418 };
419
420 mailbox1: mailbox@4a0f4000 {
421 compatible = "ti,omap4-mailbox";
422 reg = <0x4a0f4000 0x200>;
423 ti,hwmods = "mailbox1";
424 ti,mbox-num-users = <3>;
425 ti,mbox-num-fifos = <8>;
426 status = "disabled";
427 };
428
429 mailbox2: mailbox@4883a000 {
430 compatible = "ti,omap4-mailbox";
431 reg = <0x4883a000 0x200>;
432 ti,hwmods = "mailbox2";
433 ti,mbox-num-users = <4>;
434 ti,mbox-num-fifos = <12>;
435 status = "disabled";
436 };
437
438 mailbox3: mailbox@4883c000 {
439 compatible = "ti,omap4-mailbox";
440 reg = <0x4883c000 0x200>;
441 ti,hwmods = "mailbox3";
442 ti,mbox-num-users = <4>;
443 ti,mbox-num-fifos = <12>;
444 status = "disabled";
445 };
446
447 mailbox4: mailbox@4883e000 {
448 compatible = "ti,omap4-mailbox";
449 reg = <0x4883e000 0x200>;
450 ti,hwmods = "mailbox4";
451 ti,mbox-num-users = <4>;
452 ti,mbox-num-fifos = <12>;
453 status = "disabled";
454 };
455
456 mailbox5: mailbox@48840000 {
457 compatible = "ti,omap4-mailbox";
458 reg = <0x48840000 0x200>;
459 ti,hwmods = "mailbox5";
460 ti,mbox-num-users = <4>;
461 ti,mbox-num-fifos = <12>;
462 status = "disabled";
463 };
464
465 mailbox6: mailbox@48842000 {
466 compatible = "ti,omap4-mailbox";
467 reg = <0x48842000 0x200>;
468 ti,hwmods = "mailbox6";
469 ti,mbox-num-users = <4>;
470 ti,mbox-num-fifos = <12>;
471 status = "disabled";
472 };
473
474 mailbox7: mailbox@48844000 {
475 compatible = "ti,omap4-mailbox";
476 reg = <0x48844000 0x200>;
477 ti,hwmods = "mailbox7";
478 ti,mbox-num-users = <4>;
479 ti,mbox-num-fifos = <12>;
480 status = "disabled";
481 };
482
483 mailbox8: mailbox@48846000 {
484 compatible = "ti,omap4-mailbox";
485 reg = <0x48846000 0x200>;
486 ti,hwmods = "mailbox8";
487 ti,mbox-num-users = <4>;
488 ti,mbox-num-fifos = <12>;
489 status = "disabled";
490 };
491
492 mailbox9: mailbox@4885e000 {
493 compatible = "ti,omap4-mailbox";
494 reg = <0x4885e000 0x200>;
495 ti,hwmods = "mailbox9";
496 ti,mbox-num-users = <4>;
497 ti,mbox-num-fifos = <12>;
498 status = "disabled";
499 };
500
501 mailbox10: mailbox@48860000 {
502 compatible = "ti,omap4-mailbox";
503 reg = <0x48860000 0x200>;
504 ti,hwmods = "mailbox10";
505 ti,mbox-num-users = <4>;
506 ti,mbox-num-fifos = <12>;
507 status = "disabled";
508 };
509
510 mailbox11: mailbox@48862000 {
511 compatible = "ti,omap4-mailbox";
512 reg = <0x48862000 0x200>;
513 ti,hwmods = "mailbox11";
514 ti,mbox-num-users = <4>;
515 ti,mbox-num-fifos = <12>;
516 status = "disabled";
517 };
518
519 mailbox12: mailbox@48864000 {
520 compatible = "ti,omap4-mailbox";
521 reg = <0x48864000 0x200>;
522 ti,hwmods = "mailbox12";
523 ti,mbox-num-users = <4>;
524 ti,mbox-num-fifos = <12>;
525 status = "disabled";
526 };
527
528 mailbox13: mailbox@48802000 {
529 compatible = "ti,omap4-mailbox";
530 reg = <0x48802000 0x200>;
531 ti,hwmods = "mailbox13";
532 ti,mbox-num-users = <4>;
533 ti,mbox-num-fifos = <12>;
534 status = "disabled";
535 };
536
537 timer1: timer@4ae18000 {
538 compatible = "ti,omap5430-timer";
539 reg = <0x4ae18000 0x80>;
540 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
541 ti,hwmods = "timer1";
542 ti,timer-alwon;
543 };
544
545 timer2: timer@48032000 {
546 compatible = "ti,omap5430-timer";
547 reg = <0x48032000 0x80>;
548 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
549 ti,hwmods = "timer2";
550 };
551
552 timer3: timer@48034000 {
553 compatible = "ti,omap5430-timer";
554 reg = <0x48034000 0x80>;
555 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
556 ti,hwmods = "timer3";
557 };
558
559 timer4: timer@48036000 {
560 compatible = "ti,omap5430-timer";
561 reg = <0x48036000 0x80>;
562 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
563 ti,hwmods = "timer4";
564 };
565
566 timer5: timer@48820000 {
567 compatible = "ti,omap5430-timer";
568 reg = <0x48820000 0x80>;
569 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
570 ti,hwmods = "timer5";
571 ti,timer-dsp;
572 };
573
574 timer6: timer@48822000 {
575 compatible = "ti,omap5430-timer";
576 reg = <0x48822000 0x80>;
577 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
578 ti,hwmods = "timer6";
579 ti,timer-dsp;
580 ti,timer-pwm;
581 };
582
583 timer7: timer@48824000 {
584 compatible = "ti,omap5430-timer";
585 reg = <0x48824000 0x80>;
586 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
587 ti,hwmods = "timer7";
588 ti,timer-dsp;
589 };
590
591 timer8: timer@48826000 {
592 compatible = "ti,omap5430-timer";
593 reg = <0x48826000 0x80>;
594 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
595 ti,hwmods = "timer8";
596 ti,timer-dsp;
597 ti,timer-pwm;
598 };
599
600 timer9: timer@4803e000 {
601 compatible = "ti,omap5430-timer";
602 reg = <0x4803e000 0x80>;
603 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
604 ti,hwmods = "timer9";
605 };
606
607 timer10: timer@48086000 {
608 compatible = "ti,omap5430-timer";
609 reg = <0x48086000 0x80>;
610 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
611 ti,hwmods = "timer10";
612 };
613
614 timer11: timer@48088000 {
615 compatible = "ti,omap5430-timer";
616 reg = <0x48088000 0x80>;
617 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
618 ti,hwmods = "timer11";
619 ti,timer-pwm;
620 };
621
622 timer13: timer@48828000 {
623 compatible = "ti,omap5430-timer";
624 reg = <0x48828000 0x80>;
625 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
626 ti,hwmods = "timer13";
627 status = "disabled";
628 };
629
630 timer14: timer@4882a000 {
631 compatible = "ti,omap5430-timer";
632 reg = <0x4882a000 0x80>;
633 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
634 ti,hwmods = "timer14";
635 status = "disabled";
636 };
637
638 timer15: timer@4882c000 {
639 compatible = "ti,omap5430-timer";
640 reg = <0x4882c000 0x80>;
641 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
642 ti,hwmods = "timer15";
643 status = "disabled";
644 };
645
646 timer16: timer@4882e000 {
647 compatible = "ti,omap5430-timer";
648 reg = <0x4882e000 0x80>;
649 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
650 ti,hwmods = "timer16";
651 status = "disabled";
652 };
653
654 wdt2: wdt@4ae14000 {
655 compatible = "ti,omap4-wdt";
656 reg = <0x4ae14000 0x80>;
657 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
658 ti,hwmods = "wd_timer2";
659 };
660
661 hwspinlock: spinlock@4a0f6000 {
662 compatible = "ti,omap4-hwspinlock";
663 reg = <0x4a0f6000 0x1000>;
664 ti,hwmods = "spinlock";
665 #hwlock-cells = <1>;
666 };
667
668 dmm@4e000000 {
669 compatible = "ti,omap5-dmm";
670 reg = <0x4e000000 0x800>;
671 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
672 ti,hwmods = "dmm";
673 };
674
675 i2c1: i2c@48070000 {
676 compatible = "ti,omap4-i2c";
677 reg = <0x48070000 0x100>;
678 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
679 #address-cells = <1>;
680 #size-cells = <0>;
681 ti,hwmods = "i2c1";
682 status = "disabled";
683 };
684
685 i2c2: i2c@48072000 {
686 compatible = "ti,omap4-i2c";
687 reg = <0x48072000 0x100>;
688 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
689 #address-cells = <1>;
690 #size-cells = <0>;
691 ti,hwmods = "i2c2";
692 status = "disabled";
693 };
694
695 i2c3: i2c@48060000 {
696 compatible = "ti,omap4-i2c";
697 reg = <0x48060000 0x100>;
698 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
699 #address-cells = <1>;
700 #size-cells = <0>;
701 ti,hwmods = "i2c3";
702 status = "disabled";
703 };
704
705 i2c4: i2c@4807a000 {
706 compatible = "ti,omap4-i2c";
707 reg = <0x4807a000 0x100>;
708 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
709 #address-cells = <1>;
710 #size-cells = <0>;
711 ti,hwmods = "i2c4";
712 status = "disabled";
713 };
714
715 i2c5: i2c@4807c000 {
716 compatible = "ti,omap4-i2c";
717 reg = <0x4807c000 0x100>;
718 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
719 #address-cells = <1>;
720 #size-cells = <0>;
721 ti,hwmods = "i2c5";
722 status = "disabled";
723 };
724
725 mmc1: mmc@4809c000 {
726 compatible = "ti,omap4-hsmmc";
727 reg = <0x4809c000 0x400>;
728 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
729 ti,hwmods = "mmc1";
730 ti,dual-volt;
731 ti,needs-special-reset;
732 dmas = <&sdma 61>, <&sdma 62>;
733 dma-names = "tx", "rx";
734 status = "disabled";
735 pbias-supply = <&pbias_mmc_reg>;
736 };
737
738 mmc2: mmc@480b4000 {
739 compatible = "ti,omap4-hsmmc";
740 reg = <0x480b4000 0x400>;
741 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
742 ti,hwmods = "mmc2";
743 ti,needs-special-reset;
744 dmas = <&sdma 47>, <&sdma 48>;
745 dma-names = "tx", "rx";
746 status = "disabled";
747 };
748
749 mmc3: mmc@480ad000 {
750 compatible = "ti,omap4-hsmmc";
751 reg = <0x480ad000 0x400>;
752 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
753 ti,hwmods = "mmc3";
754 ti,needs-special-reset;
755 dmas = <&sdma 77>, <&sdma 78>;
756 dma-names = "tx", "rx";
757 status = "disabled";
758 };
759
760 mmc4: mmc@480d1000 {
761 compatible = "ti,omap4-hsmmc";
762 reg = <0x480d1000 0x400>;
763 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
764 ti,hwmods = "mmc4";
765 ti,needs-special-reset;
766 dmas = <&sdma 57>, <&sdma 58>;
767 dma-names = "tx", "rx";
768 status = "disabled";
769 };
770
771 abb_mpu: regulator-abb-mpu {
772 compatible = "ti,abb-v3";
773 regulator-name = "abb_mpu";
774 #address-cells = <0>;
775 #size-cells = <0>;
776 clocks = <&sys_clkin1>;
777 ti,settling-time = <50>;
778 ti,clock-cycles = <16>;
779
780 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
781 <0x4ae06014 0x4>, <0x4a003b20 0x8>,
782 <0x4ae0c158 0x4>;
783 reg-names = "setup-address", "control-address",
784 "int-address", "efuse-address",
785 "ldo-address";
786 ti,tranxdone-status-mask = <0x80>;
787 /* LDOVBBMPU_FBB_MUX_CTRL */
788 ti,ldovbb-override-mask = <0x400>;
789 /* LDOVBBMPU_FBB_VSET_OUT */
790 ti,ldovbb-vset-mask = <0x1F>;
791
792 /*
793 * NOTE: only FBB mode used but actual vset will
794 * determine final biasing
795 */
796 ti,abb_info = <
797 /*uV ABB efuse rbb_m fbb_m vset_m*/
798 1060000 0 0x0 0 0x02000000 0x01F00000
799 1160000 0 0x4 0 0x02000000 0x01F00000
800 1210000 0 0x8 0 0x02000000 0x01F00000
801 >;
802 };
803
804 abb_ivahd: regulator-abb-ivahd {
805 compatible = "ti,abb-v3";
806 regulator-name = "abb_ivahd";
807 #address-cells = <0>;
808 #size-cells = <0>;
809 clocks = <&sys_clkin1>;
810 ti,settling-time = <50>;
811 ti,clock-cycles = <16>;
812
813 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
814 <0x4ae06010 0x4>, <0x4a0025cc 0x8>,
815 <0x4a002470 0x4>;
816 reg-names = "setup-address", "control-address",
817 "int-address", "efuse-address",
818 "ldo-address";
819 ti,tranxdone-status-mask = <0x40000000>;
820 /* LDOVBBIVA_FBB_MUX_CTRL */
821 ti,ldovbb-override-mask = <0x400>;
822 /* LDOVBBIVA_FBB_VSET_OUT */
823 ti,ldovbb-vset-mask = <0x1F>;
824
825 /*
826 * NOTE: only FBB mode used but actual vset will
827 * determine final biasing
828 */
829 ti,abb_info = <
830 /*uV ABB efuse rbb_m fbb_m vset_m*/
831 1055000 0 0x0 0 0x02000000 0x01F00000
832 1150000 0 0x4 0 0x02000000 0x01F00000
833 1250000 0 0x8 0 0x02000000 0x01F00000
834 >;
835 };
836
837 abb_dspeve: regulator-abb-dspeve {
838 compatible = "ti,abb-v3";
839 regulator-name = "abb_dspeve";
840 #address-cells = <0>;
841 #size-cells = <0>;
842 clocks = <&sys_clkin1>;
843 ti,settling-time = <50>;
844 ti,clock-cycles = <16>;
845
846 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
847 <0x4ae06010 0x4>, <0x4a0025e0 0x8>,
848 <0x4a00246c 0x4>;
849 reg-names = "setup-address", "control-address",
850 "int-address", "efuse-address",
851 "ldo-address";
852 ti,tranxdone-status-mask = <0x20000000>;
853 /* LDOVBBDSPEVE_FBB_MUX_CTRL */
854 ti,ldovbb-override-mask = <0x400>;
855 /* LDOVBBDSPEVE_FBB_VSET_OUT */
856 ti,ldovbb-vset-mask = <0x1F>;
857
858 /*
859 * NOTE: only FBB mode used but actual vset will
860 * determine final biasing
861 */
862 ti,abb_info = <
863 /*uV ABB efuse rbb_m fbb_m vset_m*/
864 1055000 0 0x0 0 0x02000000 0x01F00000
865 1150000 0 0x4 0 0x02000000 0x01F00000
866 1250000 0 0x8 0 0x02000000 0x01F00000
867 >;
868 };
869
870 abb_gpu: regulator-abb-gpu {
871 compatible = "ti,abb-v3";
872 regulator-name = "abb_gpu";
873 #address-cells = <0>;
874 #size-cells = <0>;
875 clocks = <&sys_clkin1>;
876 ti,settling-time = <50>;
877 ti,clock-cycles = <16>;
878
879 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
880 <0x4ae06010 0x4>, <0x4a003b08 0x8>,
881 <0x4ae0c154 0x4>;
882 reg-names = "setup-address", "control-address",
883 "int-address", "efuse-address",
884 "ldo-address";
885 ti,tranxdone-status-mask = <0x10000000>;
886 /* LDOVBBGPU_FBB_MUX_CTRL */
887 ti,ldovbb-override-mask = <0x400>;
888 /* LDOVBBGPU_FBB_VSET_OUT */
889 ti,ldovbb-vset-mask = <0x1F>;
890
891 /*
892 * NOTE: only FBB mode used but actual vset will
893 * determine final biasing
894 */
895 ti,abb_info = <
896 /*uV ABB efuse rbb_m fbb_m vset_m*/
897 1090000 0 0x0 0 0x02000000 0x01F00000
898 1210000 0 0x4 0 0x02000000 0x01F00000
899 1280000 0 0x8 0 0x02000000 0x01F00000
900 >;
901 };
902
903 mcspi1: spi@48098000 {
904 compatible = "ti,omap4-mcspi";
905 reg = <0x48098000 0x200>;
906 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
907 #address-cells = <1>;
908 #size-cells = <0>;
909 ti,hwmods = "mcspi1";
910 ti,spi-num-cs = <4>;
911 dmas = <&sdma 35>,
912 <&sdma 36>,
913 <&sdma 37>,
914 <&sdma 38>,
915 <&sdma 39>,
916 <&sdma 40>,
917 <&sdma 41>,
918 <&sdma 42>;
919 dma-names = "tx0", "rx0", "tx1", "rx1",
920 "tx2", "rx2", "tx3", "rx3";
921 status = "disabled";
922 };
923
924 mcspi2: spi@4809a000 {
925 compatible = "ti,omap4-mcspi";
926 reg = <0x4809a000 0x200>;
927 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
928 #address-cells = <1>;
929 #size-cells = <0>;
930 ti,hwmods = "mcspi2";
931 ti,spi-num-cs = <2>;
932 dmas = <&sdma 43>,
933 <&sdma 44>,
934 <&sdma 45>,
935 <&sdma 46>;
936 dma-names = "tx0", "rx0", "tx1", "rx1";
937 status = "disabled";
938 };
939
940 mcspi3: spi@480b8000 {
941 compatible = "ti,omap4-mcspi";
942 reg = <0x480b8000 0x200>;
943 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
944 #address-cells = <1>;
945 #size-cells = <0>;
946 ti,hwmods = "mcspi3";
947 ti,spi-num-cs = <2>;
948 dmas = <&sdma 15>, <&sdma 16>;
949 dma-names = "tx0", "rx0";
950 status = "disabled";
951 };
952
953 mcspi4: spi@480ba000 {
954 compatible = "ti,omap4-mcspi";
955 reg = <0x480ba000 0x200>;
956 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
957 #address-cells = <1>;
958 #size-cells = <0>;
959 ti,hwmods = "mcspi4";
960 ti,spi-num-cs = <1>;
961 dmas = <&sdma 70>, <&sdma 71>;
962 dma-names = "tx0", "rx0";
963 status = "disabled";
964 };
965
966 qspi: qspi@4b300000 {
967 compatible = "ti,dra7xxx-qspi";
968 reg = <0x4b300000 0x100>;
969 reg-names = "qspi_base";
970 #address-cells = <1>;
971 #size-cells = <0>;
972 ti,hwmods = "qspi";
973 clocks = <&qspi_gfclk_div>;
974 clock-names = "fck";
975 num-cs = <4>;
976 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
977 status = "disabled";
978 };
979
980 omap_control_sata: control-phy@4a002374 {
981 compatible = "ti,control-phy-pipe3";
982 reg = <0x4a002374 0x4>;
983 reg-names = "power";
984 clocks = <&sys_clkin1>;
985 clock-names = "sysclk";
986 };
987
988 /* OCP2SCP3 */
989 ocp2scp@4a090000 {
990 compatible = "ti,omap-ocp2scp";
991 #address-cells = <1>;
992 #size-cells = <1>;
993 ranges;
994 reg = <0x4a090000 0x20>;
995 ti,hwmods = "ocp2scp3";
996 sata_phy: phy@4A096000 {
997 compatible = "ti,phy-pipe3-sata";
998 reg = <0x4A096000 0x80>, /* phy_rx */
999 <0x4A096400 0x64>, /* phy_tx */
1000 <0x4A096800 0x40>; /* pll_ctrl */
1001 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1002 ctrl-module = <&omap_control_sata>;
1003 clocks = <&sys_clkin1>;
1004 clock-names = "sysclk";
1005 #phy-cells = <0>;
1006 };
1007
1008 pcie1_phy: pciephy@4a094000 {
1009 compatible = "ti,phy-pipe3-pcie";
1010 reg = <0x4a094000 0x80>, /* phy_rx */
1011 <0x4a094400 0x64>; /* phy_tx */
1012 reg-names = "phy_rx", "phy_tx";
1013 ctrl-module = <&omap_control_pcie1phy>;
1014 clocks = <&dpll_pcie_ref_ck>,
1015 <&dpll_pcie_ref_m2ldo_ck>,
1016 <&optfclk_pciephy1_32khz>,
1017 <&optfclk_pciephy1_clk>,
1018 <&optfclk_pciephy1_div_clk>,
1019 <&optfclk_pciephy_div>;
1020 clock-names = "dpll_ref", "dpll_ref_m2",
1021 "wkupclk", "refclk",
1022 "div-clk", "phy-div";
1023 #phy-cells = <0>;
1024 id = <1>;
1025 ti,hwmods = "pcie1-phy";
1026 };
1027
1028 pcie2_phy: pciephy@4a095000 {
1029 compatible = "ti,phy-pipe3-pcie";
1030 reg = <0x4a095000 0x80>, /* phy_rx */
1031 <0x4a095400 0x64>; /* phy_tx */
1032 reg-names = "phy_rx", "phy_tx";
1033 ctrl-module = <&omap_control_pcie2phy>;
1034 clocks = <&dpll_pcie_ref_ck>,
1035 <&dpll_pcie_ref_m2ldo_ck>,
1036 <&optfclk_pciephy2_32khz>,
1037 <&optfclk_pciephy2_clk>,
1038 <&optfclk_pciephy2_div_clk>,
1039 <&optfclk_pciephy_div>;
1040 clock-names = "dpll_ref", "dpll_ref_m2",
1041 "wkupclk", "refclk",
1042 "div-clk", "phy-div";
1043 #phy-cells = <0>;
1044 ti,hwmods = "pcie2-phy";
1045 id = <2>;
1046 status = "disabled";
1047 };
1048 };
1049
1050 sata: sata@4a141100 {
1051 compatible = "snps,dwc-ahci";
1052 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
1053 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1054 phys = <&sata_phy>;
1055 phy-names = "sata-phy";
1056 clocks = <&sata_ref_clk>;
1057 ti,hwmods = "sata";
1058 };
1059
1060 omap_control_pcie1phy: control-phy@0x4a003c40 {
1061 compatible = "ti,control-phy-pcie";
1062 reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
1063 reg-names = "power", "control_sma", "pcie_pcs";
1064 clocks = <&sys_clkin1>;
1065 clock-names = "sysclk";
1066 };
1067
1068 omap_control_pcie2phy: control-pcie@0x4a003c44 {
1069 compatible = "ti,control-phy-pcie";
1070 reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
1071 reg-names = "power", "control_sma", "pcie_pcs";
1072 clocks = <&sys_clkin1>;
1073 clock-names = "sysclk";
1074 status = "disabled";
1075 };
1076
1077 omap_control_usb2phy1: control-phy@4a002300 {
1078 compatible = "ti,control-phy-usb2";
1079 reg = <0x4a002300 0x4>;
1080 reg-names = "power";
1081 };
1082
1083 omap_control_usb3phy1: control-phy@4a002370 {
1084 compatible = "ti,control-phy-pipe3";
1085 reg = <0x4a002370 0x4>;
1086 reg-names = "power";
1087 };
1088
1089 omap_control_usb2phy2: control-phy@0x4a002e74 {
1090 compatible = "ti,control-phy-usb2-dra7";
1091 reg = <0x4a002e74 0x4>;
1092 reg-names = "power";
1093 };
1094
1095 /* OCP2SCP1 */
1096 ocp2scp@4a080000 {
1097 compatible = "ti,omap-ocp2scp";
1098 #address-cells = <1>;
1099 #size-cells = <1>;
1100 ranges;
1101 reg = <0x4a080000 0x20>;
1102 ti,hwmods = "ocp2scp1";
1103
1104 usb2_phy1: phy@4a084000 {
1105 compatible = "ti,omap-usb2";
1106 reg = <0x4a084000 0x400>;
1107 ctrl-module = <&omap_control_usb2phy1>;
1108 clocks = <&usb_phy1_always_on_clk32k>,
1109 <&usb_otg_ss1_refclk960m>;
1110 clock-names = "wkupclk",
1111 "refclk";
1112 #phy-cells = <0>;
1113 };
1114
1115 usb2_phy2: phy@4a085000 {
1116 compatible = "ti,omap-usb2";
1117 reg = <0x4a085000 0x400>;
1118 ctrl-module = <&omap_control_usb2phy2>;
1119 clocks = <&usb_phy2_always_on_clk32k>,
1120 <&usb_otg_ss2_refclk960m>;
1121 clock-names = "wkupclk",
1122 "refclk";
1123 #phy-cells = <0>;
1124 };
1125
1126 usb3_phy1: phy@4a084400 {
1127 compatible = "ti,omap-usb3";
1128 reg = <0x4a084400 0x80>,
1129 <0x4a084800 0x64>,
1130 <0x4a084c00 0x40>;
1131 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1132 ctrl-module = <&omap_control_usb3phy1>;
1133 clocks = <&usb_phy3_always_on_clk32k>,
1134 <&sys_clkin1>,
1135 <&usb_otg_ss1_refclk960m>;
1136 clock-names = "wkupclk",
1137 "sysclk",
1138 "refclk";
1139 #phy-cells = <0>;
1140 };
1141 };
1142
1143 omap_dwc3_1@48880000 {
1144 compatible = "ti,dwc3";
1145 ti,hwmods = "usb_otg_ss1";
1146 reg = <0x48880000 0x10000>;
1147 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1148 #address-cells = <1>;
1149 #size-cells = <1>;
1150 utmi-mode = <2>;
1151 ranges;
1152 usb1: usb@48890000 {
1153 compatible = "snps,dwc3";
1154 reg = <0x48890000 0x17000>;
1155 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1156 phys = <&usb2_phy1>, <&usb3_phy1>;
1157 phy-names = "usb2-phy", "usb3-phy";
1158 tx-fifo-resize;
1159 maximum-speed = "super-speed";
1160 dr_mode = "otg";
1161 };
1162 };
1163
1164 omap_dwc3_2@488c0000 {
1165 compatible = "ti,dwc3";
1166 ti,hwmods = "usb_otg_ss2";
1167 reg = <0x488c0000 0x10000>;
1168 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1169 #address-cells = <1>;
1170 #size-cells = <1>;
1171 utmi-mode = <2>;
1172 ranges;
1173 usb2: usb@488d0000 {
1174 compatible = "snps,dwc3";
1175 reg = <0x488d0000 0x17000>;
1176 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1177 phys = <&usb2_phy2>;
1178 phy-names = "usb2-phy";
1179 tx-fifo-resize;
1180 maximum-speed = "high-speed";
1181 dr_mode = "otg";
1182 };
1183 };
1184
1185 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
1186 omap_dwc3_3@48900000 {
1187 compatible = "ti,dwc3";
1188 ti,hwmods = "usb_otg_ss3";
1189 reg = <0x48900000 0x10000>;
1190 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1191 #address-cells = <1>;
1192 #size-cells = <1>;
1193 utmi-mode = <2>;
1194 ranges;
1195 status = "disabled";
1196 usb3: usb@48910000 {
1197 compatible = "snps,dwc3";
1198 reg = <0x48910000 0x17000>;
1199 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1200 tx-fifo-resize;
1201 maximum-speed = "high-speed";
1202 dr_mode = "otg";
1203 };
1204 };
1205
1206 omap_dwc3_4@48940000 {
1207 compatible = "ti,dwc3";
1208 ti,hwmods = "usb_otg_ss4";
1209 reg = <0x48940000 0x10000>;
1210 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
1211 #address-cells = <1>;
1212 #size-cells = <1>;
1213 utmi-mode = <2>;
1214 ranges;
1215 status = "disabled";
1216 usb4: usb@48950000 {
1217 compatible = "snps,dwc3";
1218 reg = <0x48950000 0x17000>;
1219 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
1220 tx-fifo-resize;
1221 maximum-speed = "high-speed";
1222 dr_mode = "otg";
1223 };
1224 };
1225
1226 elm: elm@48078000 {
1227 compatible = "ti,am3352-elm";
1228 reg = <0x48078000 0xfc0>; /* device IO registers */
1229 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1230 ti,hwmods = "elm";
1231 status = "disabled";
1232 };
1233
1234 gpmc: gpmc@50000000 {
1235 compatible = "ti,am3352-gpmc";
1236 ti,hwmods = "gpmc";
1237 reg = <0x50000000 0x37c>; /* device IO registers */
1238 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1239 gpmc,num-cs = <8>;
1240 gpmc,num-waitpins = <2>;
1241 #address-cells = <2>;
1242 #size-cells = <1>;
1243 status = "disabled";
1244 };
1245
1246 atl: atl@4843c000 {
1247 compatible = "ti,dra7-atl";
1248 reg = <0x4843c000 0x3ff>;
1249 ti,hwmods = "atl";
1250 ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
1251 <&atl_clkin2_ck>, <&atl_clkin3_ck>;
1252 clocks = <&atl_gfclk_mux>;
1253 clock-names = "fck";
1254 status = "disabled";
1255 };
1256
1257 crossbar_mpu: crossbar@4a020000 {
1258 compatible = "ti,irq-crossbar";
1259 reg = <0x4a002a48 0x130>;
1260 ti,max-irqs = <160>;
1261 ti,max-crossbar-sources = <MAX_SOURCES>;
1262 ti,reg-size = <2>;
1263 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
1264 ti,irqs-skip = <10 133 139 140>;
1265 ti,irqs-safe-map = <0>;
1266 };
1267 };
1268 };
1269
1270 /include/ "dra7xx-clocks.dtsi"
Linux kernel - Deliverables
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