2 * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include "dra72x.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/clk/ti-dra7-atl.h>
15 compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
21 evm_3v3: fixedregulator-evm_3v3 {
22 compatible = "regulator-fixed";
23 regulator-name = "evm_3v3";
24 regulator-min-microvolt = <3300000>;
25 regulator-max-microvolt = <3300000>;
28 aic_dvdd: fixedregulator-aic_dvdd {
30 compatible = "regulator-fixed";
31 regulator-name = "aic_dvdd";
32 vin-supply = <&evm_3v3>;
33 regulator-min-microvolt = <1800000>;
34 regulator-max-microvolt = <1800000>;
37 evm_3v3_sd: fixedregulator-sd {
38 compatible = "regulator-fixed";
39 regulator-name = "evm_3v3_sd";
40 regulator-min-microvolt = <3300000>;
41 regulator-max-microvolt = <3300000>;
43 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
46 extcon_usb1: extcon_usb1 {
47 compatible = "linux,extcon-usb-gpio";
48 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
51 extcon_usb2: extcon_usb2 {
52 compatible = "linux,extcon-usb-gpio";
53 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
57 compatible = "hdmi-connector";
63 hdmi_connector_in: endpoint {
64 remote-endpoint = <&tpd12s015_out>;
70 compatible = "ti,tpd12s015";
72 pinctrl-names = "default";
73 pinctrl-0 = <&tpd12s015_pins>;
75 gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
76 <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
77 <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
86 tpd12s015_in: endpoint {
87 remote-endpoint = <&hdmi_out>;
94 tpd12s015_out: endpoint {
95 remote-endpoint = <&hdmi_connector_in>;
102 compatible = "simple-audio-card";
103 simple-audio-card,name = "DRA7xx-EVM";
104 simple-audio-card,widgets =
105 "Headphone", "Headphone Jack",
107 "Microphone", "Mic Jack",
109 simple-audio-card,routing =
110 "Headphone Jack", "HPLOUT",
111 "Headphone Jack", "HPROUT",
116 "Mic Jack", "Mic Bias",
119 simple-audio-card,format = "dsp_b";
120 simple-audio-card,bitclock-master = <&sound0_master>;
121 simple-audio-card,frame-master = <&sound0_master>;
122 simple-audio-card,bitclock-inversion;
124 sound0_master: simple-audio-card,cpu {
125 sound-dai = <&mcasp3>;
126 system-clock-frequency = <5644800>;
129 simple-audio-card,codec {
130 sound-dai = <&tlv320aic3106>;
131 clocks = <&atl_clkin2_ck>;
137 i2c1_pins: pinmux_i2c1_pins {
138 pinctrl-single,pins = <
139 DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
140 DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
144 i2c5_pins: pinmux_i2c5_pins {
145 pinctrl-single,pins = <
146 DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
147 DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
151 i2c5_pins: pinmux_i2c5_pins {
152 pinctrl-single,pins = <
153 DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
154 DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
158 nand_default: nand_default {
159 pinctrl-single,pins = <
160 DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
161 DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
162 DRA7XX_CORE_IOPAD(0x3408, PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
163 DRA7XX_CORE_IOPAD(0x340c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
164 DRA7XX_CORE_IOPAD(0x3410, PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
165 DRA7XX_CORE_IOPAD(0x3414, PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
166 DRA7XX_CORE_IOPAD(0x3418, PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
167 DRA7XX_CORE_IOPAD(0x341c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
168 DRA7XX_CORE_IOPAD(0x3420, PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
169 DRA7XX_CORE_IOPAD(0x3424, PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
170 DRA7XX_CORE_IOPAD(0x3428, PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
171 DRA7XX_CORE_IOPAD(0x342c, PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
172 DRA7XX_CORE_IOPAD(0x3430, PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
173 DRA7XX_CORE_IOPAD(0x3434, PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
174 DRA7XX_CORE_IOPAD(0x3438, PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
175 DRA7XX_CORE_IOPAD(0x343c, PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
176 DRA7XX_CORE_IOPAD(0x34b4, PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */
177 DRA7XX_CORE_IOPAD(0x34c4, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
178 DRA7XX_CORE_IOPAD(0x34cc, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
179 DRA7XX_CORE_IOPAD(0x34c8, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
180 DRA7XX_CORE_IOPAD(0x34d0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */
181 DRA7XX_CORE_IOPAD(0x34d8, PIN_INPUT | MUX_MODE0) /* gpmc_wait0 */
185 usb1_pins: pinmux_usb1_pins {
186 pinctrl-single,pins = <
187 DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
191 usb2_pins: pinmux_usb2_pins {
192 pinctrl-single,pins = <
193 DRA7XX_CORE_IOPAD(0x3684, PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
197 tps65917_pins_default: tps65917_pins_default {
198 pinctrl-single,pins = <
199 DRA7XX_CORE_IOPAD(0x3824, PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
203 mmc1_pins_default: mmc1_pins_default {
204 pinctrl-single,pins = <
205 DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
206 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
207 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
208 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
209 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
210 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
211 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
215 mmc2_pins_default: mmc2_pins_default {
216 pinctrl-single,pins = <
217 DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
218 DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
219 DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
220 DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
221 DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
222 DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
223 DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
224 DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
225 DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
226 DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
230 dcan1_pins_default: dcan1_pins_default {
231 pinctrl-single,pins = <
232 DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
233 DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
237 dcan1_pins_sleep: dcan1_pins_sleep {
238 pinctrl-single,pins = <
239 DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
240 DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
244 qspi1_pins: pinmux_qspi1_pins {
245 pinctrl-single,pins = <
246 DRA7XX_CORE_IOPAD(0x3474, PIN_OUTPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
247 DRA7XX_CORE_IOPAD(0x3478, PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
248 DRA7XX_CORE_IOPAD(0x347c, PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
249 DRA7XX_CORE_IOPAD(0x3480, PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
250 DRA7XX_CORE_IOPAD(0x3484, PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
251 DRA7XX_CORE_IOPAD(0x3488, PIN_OUTPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
252 DRA7XX_CORE_IOPAD(0x34b8, PIN_OUTPUT | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
256 hdmi_pins: pinmux_hdmi_pins {
257 pinctrl-single,pins = <
258 DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
259 DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
263 tpd12s015_pins: pinmux_tpd12s015_pins {
264 pinctrl-single,pins = <
265 DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */
269 atl_pins: pinmux_atl_pins {
270 pinctrl-single,pins = <
271 DRA7XX_CORE_IOPAD(0x3698, PIN_OUTPUT | MUX_MODE5) /* xref_clk1.atl_clk1 */
272 DRA7XX_CORE_IOPAD(0x369c, PIN_OUTPUT | MUX_MODE5) /* xref_clk2.atl_clk2 */
276 mcasp3_pins: pinmux_mcasp3_pins {
277 pinctrl-single,pins = <
278 DRA7XX_CORE_IOPAD(0x3724, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */
279 DRA7XX_CORE_IOPAD(0x3728, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */
280 DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */
281 DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1 */
285 mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins {
286 pinctrl-single,pins = <
287 DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT_PULLDOWN | MUX_MODE15)
288 DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT_PULLDOWN | MUX_MODE15)
289 DRA7XX_CORE_IOPAD(0x372c, PIN_INPUT_PULLDOWN | MUX_MODE15)
290 DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE15)
297 pinctrl-names = "default";
298 pinctrl-0 = <&i2c1_pins>;
299 clock-frequency = <400000>;
301 tps65917: tps65917@58 {
302 compatible = "ti,tps65917";
305 pinctrl-names = "default";
306 pinctrl-0 = <&tps65917_pins_default>;
308 interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
309 interrupt-controller;
310 #interrupt-cells = <2>;
312 ti,system-power-controller;
315 compatible = "ti,tps65917-pmic";
317 tps65917_regulators: regulators {
320 regulator-name = "smps1";
321 regulator-min-microvolt = <850000>;
322 regulator-max-microvolt = <1250000>;
329 regulator-name = "smps2";
330 regulator-min-microvolt = <850000>;
331 regulator-max-microvolt = <1060000>;
337 /* VDD_GPU IVA DSPEVE */
338 regulator-name = "smps3";
339 regulator-min-microvolt = <850000>;
340 regulator-max-microvolt = <1250000>;
347 regulator-name = "smps4";
348 regulator-min-microvolt = <1800000>;
349 regulator-max-microvolt = <1800000>;
356 regulator-name = "smps5";
357 regulator-min-microvolt = <1350000>;
358 regulator-max-microvolt = <1350000>;
364 /* LDO1_OUT --> SDIO */
365 regulator-name = "ldo1";
366 regulator-min-microvolt = <1800000>;
367 regulator-max-microvolt = <3300000>;
370 regulator-allow-bypass;
375 regulator-name = "ldo3";
376 regulator-min-microvolt = <1800000>;
377 regulator-max-microvolt = <1800000>;
384 regulator-name = "ldo5";
385 regulator-min-microvolt = <1800000>;
386 regulator-max-microvolt = <1800000>;
392 /* VDDA_3V_USB: VDDA_USBHS33 */
393 regulator-name = "ldo4";
394 regulator-min-microvolt = <3300000>;
395 regulator-max-microvolt = <3300000>;
401 tps65917_power_button {
402 compatible = "ti,palmas-pwrbutton";
403 interrupt-parent = <&tps65917>;
404 interrupts = <1 IRQ_TYPE_NONE>;
406 ti,palmas-long-press-seconds = <6>;
410 pcf_gpio_21: gpio@21 {
411 compatible = "nxp,pcf8575";
413 lines-initial-states = <0x1408>;
416 interrupt-controller;
417 #interrupt-cells = <2>;
420 tlv320aic3106: tlv320aic3106@19 {
421 #sound-dai-cells = <0>;
422 compatible = "ti,tlv320aic3106";
424 adc-settle-ms = <40>;
425 ai3x-micbias-vg = <1>; /* 2.0V */
429 AVDD-supply = <&evm_3v3>;
430 IOVDD-supply = <&evm_3v3>;
431 DRVDD-supply = <&evm_3v3>;
432 DVDD-supply = <&aic_dvdd>;
438 pinctrl-names = "default";
439 pinctrl-0 = <&i2c5_pins>;
440 clock-frequency = <400000>;
442 pcf_hdmi: pcf8575@26 {
443 compatible = "nxp,pcf8575";
448 * initial state is used here to keep the mdio interface
449 * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
450 * VIN2_S0 driven high otherwise Ethernet stops working
451 * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
453 lines-initial-states = <0x0f2b>;
456 /* vin6_sel_s0: high: VIN6, low: audio */
458 gpios = <1 GPIO_ACTIVE_HIGH>;
460 line-name = "vin6_sel_s0";
467 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
468 <&dra7_pmx_core 0x3e0>;
477 pinctrl-names = "default";
478 pinctrl-0 = <&nand_default>;
479 ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
481 /* To use NAND, DIP switch SW5 must be set like so:
482 * SW5.1 (NAND_SELn) = ON (LOW)
483 * SW5.9 (GPMC_WPN) = OFF (HIGH)
485 compatible = "ti,omap2-nand";
486 reg = <0 0 4>; /* device IO registers */
487 interrupt-parent = <&gpmc>;
488 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
489 <1 IRQ_TYPE_NONE>; /* termcount */
490 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
491 ti,nand-ecc-opt = "bch8";
493 nand-bus-width = <16>;
494 gpmc,device-width = <2>;
495 gpmc,sync-clk-ps = <0>;
497 gpmc,cs-rd-off-ns = <80>;
498 gpmc,cs-wr-off-ns = <80>;
499 gpmc,adv-on-ns = <0>;
500 gpmc,adv-rd-off-ns = <60>;
501 gpmc,adv-wr-off-ns = <60>;
502 gpmc,we-on-ns = <10>;
503 gpmc,we-off-ns = <50>;
505 gpmc,oe-off-ns = <40>;
506 gpmc,access-ns = <40>;
507 gpmc,wr-access-ns = <80>;
508 gpmc,rd-cycle-ns = <80>;
509 gpmc,wr-cycle-ns = <80>;
510 gpmc,bus-turnaround-ns = <0>;
511 gpmc,cycle2cycle-delay-ns = <0>;
512 gpmc,clk-activation-ns = <0>;
513 gpmc,wr-data-mux-bus-ns = <0>;
514 /* MTD partition table */
515 /* All SPL-* partitions are sized to minimal length
516 * which can be independently programmable. For
517 * NAND flash this is equal to size of erase-block */
518 #address-cells = <1>;
522 reg = <0x00000000 0x000020000>;
525 label = "NAND.SPL.backup1";
526 reg = <0x00020000 0x00020000>;
529 label = "NAND.SPL.backup2";
530 reg = <0x00040000 0x00020000>;
533 label = "NAND.SPL.backup3";
534 reg = <0x00060000 0x00020000>;
537 label = "NAND.u-boot-spl-os";
538 reg = <0x00080000 0x00040000>;
541 label = "NAND.u-boot";
542 reg = <0x000c0000 0x00100000>;
545 label = "NAND.u-boot-env";
546 reg = <0x001c0000 0x00020000>;
549 label = "NAND.u-boot-env.backup1";
550 reg = <0x001e0000 0x00020000>;
553 label = "NAND.kernel";
554 reg = <0x00200000 0x00800000>;
557 label = "NAND.file-system";
558 reg = <0x00a00000 0x0f600000>;
564 phy-supply = <&ldo4_reg>;
568 phy-supply = <&ldo4_reg>;
572 extcon = <&extcon_usb1>;
576 extcon = <&extcon_usb2>;
580 dr_mode = "peripheral";
581 pinctrl-names = "default";
582 pinctrl-0 = <&usb1_pins>;
587 pinctrl-names = "default";
588 pinctrl-0 = <&usb2_pins>;
593 pinctrl-names = "default";
594 pinctrl-0 = <&mmc1_pins_default>;
595 vmmc-supply = <&evm_3v3_sd>;
596 vmmc_aux-supply = <&ldo1_reg>;
599 * SDCD signal is not being used here - using the fact that GPIO mode
600 * is a viable alternative
602 cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
603 max-frequency = <192000000>;
607 /* SW5-3 in ON position */
609 pinctrl-names = "default";
610 pinctrl-0 = <&mmc2_pins_default>;
612 vmmc-supply = <&evm_3v3>;
615 max-frequency = <192000000>;
619 cpsw_default: cpsw_default {
620 pinctrl-single,pins = <
622 DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
623 DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
624 DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
625 DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
626 DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
627 DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
628 DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
629 DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
630 DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
631 DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
632 DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
633 DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
638 cpsw_sleep: cpsw_sleep {
639 pinctrl-single,pins = <
641 DRA7XX_CORE_IOPAD(0x3598, MUX_MODE15)
642 DRA7XX_CORE_IOPAD(0x359c, MUX_MODE15)
643 DRA7XX_CORE_IOPAD(0x35a0, MUX_MODE15)
644 DRA7XX_CORE_IOPAD(0x35a4, MUX_MODE15)
645 DRA7XX_CORE_IOPAD(0x35a8, MUX_MODE15)
646 DRA7XX_CORE_IOPAD(0x35ac, MUX_MODE15)
647 DRA7XX_CORE_IOPAD(0x35b0, MUX_MODE15)
648 DRA7XX_CORE_IOPAD(0x35b4, MUX_MODE15)
649 DRA7XX_CORE_IOPAD(0x35b8, MUX_MODE15)
650 DRA7XX_CORE_IOPAD(0x35bc, MUX_MODE15)
651 DRA7XX_CORE_IOPAD(0x35c0, MUX_MODE15)
652 DRA7XX_CORE_IOPAD(0x35c4, MUX_MODE15)
656 davinci_mdio_default: davinci_mdio_default {
657 pinctrl-single,pins = <
659 DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
660 DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
664 davinci_mdio_sleep: davinci_mdio_sleep {
665 pinctrl-single,pins = <
666 DRA7XX_CORE_IOPAD(0x363c, MUX_MODE15)
667 DRA7XX_CORE_IOPAD(0x3640, MUX_MODE15)
674 pinctrl-names = "default", "sleep";
675 pinctrl-0 = <&cpsw_default>;
676 pinctrl-1 = <&cpsw_sleep>;
680 pinctrl-names = "default", "sleep";
681 pinctrl-0 = <&davinci_mdio_default>;
682 pinctrl-1 = <&davinci_mdio_sleep>;
687 pinctrl-names = "default", "sleep", "active";
688 pinctrl-0 = <&dcan1_pins_sleep>;
689 pinctrl-1 = <&dcan1_pins_sleep>;
690 pinctrl-2 = <&dcan1_pins_default>;
695 pinctrl-names = "default";
696 pinctrl-0 = <&qspi1_pins>;
698 spi-max-frequency = <48000000>;
700 compatible = "s25fl256s1";
701 spi-max-frequency = <48000000>;
703 spi-tx-bus-width = <1>;
704 spi-rx-bus-width = <4>;
707 #address-cells = <1>;
710 /* MTD partition table.
711 * The ROM checks the first four physical blocks
712 * for a valid file to boot and the flash here is
717 reg = <0x00000000 0x000010000>;
720 label = "QSPI.SPL.backup1";
721 reg = <0x00010000 0x00010000>;
724 label = "QSPI.SPL.backup2";
725 reg = <0x00020000 0x00010000>;
728 label = "QSPI.SPL.backup3";
729 reg = <0x00030000 0x00010000>;
732 label = "QSPI.u-boot";
733 reg = <0x00040000 0x00100000>;
736 label = "QSPI.u-boot-spl-os";
737 reg = <0x00140000 0x00080000>;
740 label = "QSPI.u-boot-env";
741 reg = <0x001c0000 0x00010000>;
744 label = "QSPI.u-boot-env.backup1";
745 reg = <0x001d0000 0x0010000>;
748 label = "QSPI.kernel";
749 reg = <0x001e0000 0x0800000>;
752 label = "QSPI.file-system";
753 reg = <0x009e0000 0x01620000>;
761 vdda_video-supply = <&ldo5_reg>;
767 pinctrl-names = "default";
768 pinctrl-0 = <&hdmi_pins>;
772 remote-endpoint = <&tpd12s015_in>;
778 pinctrl-names = "default";
779 pinctrl-0 = <&atl_pins>;
781 assigned-clocks = <&abe_dpll_sys_clk_mux>,
786 assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
787 assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
792 bws = <DRA7_ATL_WS_MCASP2_FSX>;
793 aws = <DRA7_ATL_WS_MCASP3_FSX>;
798 #sound-dai-cells = <0>;
799 pinctrl-names = "default", "sleep";
800 pinctrl-0 = <&mcasp3_pins>;
801 pinctrl-1 = <&mcasp3_sleep_pins>;
803 assigned-clocks = <&mcasp3_ahclkx_mux>;
804 assigned-clock-parents = <&atl_clkin2_ck>;
808 op-mode = <0>; /* MCASP_IIS_MODE */
811 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
820 mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
823 mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
830 mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {