arch/arm/boot/dts/dra72-evm.dts

   1 /*
   2  * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 /dts-v1/;
   9
  10 #include "dra72x.dtsi"
  11 #include <dt-bindings/gpio/gpio.h>
  12
  13 / {
  14         model = "TI DRA722";
  15         compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
  16
  17         memory {
  18                 device_type = "memory";
  19                 reg = <0x80000000 0x40000000>; /* 1024 MB */
  20         };
  21
  22         aliases {
  23                 display0 = &hdmi0;
  24         };
  25
  26         evm_3v3: fixedregulator-evm_3v3 {
  27                 compatible = "regulator-fixed";
  28                 regulator-name = "evm_3v3";
  29                 regulator-min-microvolt = <3300000>;
  30                 regulator-max-microvolt = <3300000>;
  31         };
  32
  33         evm_3v3_sd: fixedregulator-sd {
  34                 compatible = "regulator-fixed";
  35                 regulator-name = "evm_3v3_sd";
  36                 regulator-min-microvolt = <3300000>;
  37                 regulator-max-microvolt = <3300000>;
  38                 enable-active-high;
  39                 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
  40         };
  41
  42         extcon_usb1: extcon_usb1 {
  43                 compatible = "linux,extcon-usb-gpio";
  44                 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
  45         };
  46
  47         extcon_usb2: extcon_usb2 {
  48                 compatible = "linux,extcon-usb-gpio";
  49                 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
  50         };
  51
  52         hdmi0: connector {
  53                 compatible = "hdmi-connector";
  54                 label = "hdmi";
  55
  56                 type = "a";
  57
  58                 port {
  59                         hdmi_connector_in: endpoint {
  60                                 remote-endpoint = <&tpd12s015_out>;
  61                         };
  62                 };
  63         };
  64
  65         tpd12s015: encoder {
  66                 compatible = "ti,tpd12s015";
  67
  68                 pinctrl-names = "default";
  69                 pinctrl-0 = <&tpd12s015_pins>;
  70
  71                 gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
  72                         <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
  73                         <&gpio7 12 GPIO_ACTIVE_HIGH>;   /* gpio7_12/sp1_cs2, HPD */
  74
  75                 ports {
  76                         #address-cells = <1>;
  77                         #size-cells = <0>;
  78
  79                         port@0 {
  80                                 reg = <0>;
  81
  82                                 tpd12s015_in: endpoint {
  83                                         remote-endpoint = <&hdmi_out>;
  84                                 };
  85                         };
  86
  87                         port@1 {
  88                                 reg = <1>;
  89
  90                                 tpd12s015_out: endpoint {
  91                                         remote-endpoint = <&hdmi_connector_in>;
  92                                 };
  93                         };
  94                 };
  95         };
  96 };
  97
  98 &dra7_pmx_core {
  99         i2c1_pins: pinmux_i2c1_pins {
 100                 pinctrl-single,pins = <
 101                         0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
 102                         0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
 103                 >;
 104         };
 105
 106         i2c5_pins: pinmux_i2c5_pins {
 107                 pinctrl-single,pins = <
 108                         0x2b4 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
 109                         0x2b8 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
 110                 >;
 111         };
 112
 113         nand_default: nand_default {
 114                 pinctrl-single,pins = <
 115                         0x0     (PIN_INPUT  | MUX_MODE0) /* gpmc_ad0 */
 116                         0x4     (PIN_INPUT  | MUX_MODE0) /* gpmc_ad1 */
 117                         0x8     (PIN_INPUT  | MUX_MODE0) /* gpmc_ad2 */
 118                         0xc     (PIN_INPUT  | MUX_MODE0) /* gpmc_ad3 */
 119                         0x10    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad4 */
 120                         0x14    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad5 */
 121                         0x18    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad6 */
 122                         0x1c    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad7 */
 123                         0x20    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad8 */
 124                         0x24    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad9 */
 125                         0x28    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad10 */
 126                         0x2c    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad11 */
 127                         0x30    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad12 */
 128                         0x34    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad13 */
 129                         0x38    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad14 */
 130                         0x3c    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad15 */
 131                         0xb4    (PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */
 132                         0xc4    (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
 133                         0xcc    (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
 134                         0xc8    (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
 135                         0xd0    (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */
 136                         0xd8    (PIN_INPUT  | MUX_MODE0) /* gpmc_wait0 */
 137                 >;
 138         };
 139
 140         usb1_pins: pinmux_usb1_pins {
 141                 pinctrl-single,pins = <
 142                         0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
 143                 >;
 144         };
 145
 146         usb2_pins: pinmux_usb2_pins {
 147                 pinctrl-single,pins = <
 148                         0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
 149                 >;
 150         };
 151
 152         tps65917_pins_default: tps65917_pins_default {
 153                 pinctrl-single,pins = <
 154                         0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
 155                 >;
 156         };
 157
 158         mmc1_pins_default: mmc1_pins_default {
 159                 pinctrl-single,pins = <
 160                         0x36c (PIN_INPUT | MUX_MODE14)  /* mmc1sdcd.gpio219 */
 161                         0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
 162                         0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
 163                         0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
 164                         0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
 165                         0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
 166                         0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
 167                 >;
 168         };
 169
 170         mmc2_pins_default: mmc2_pins_default {
 171                 pinctrl-single,pins = <
 172                         0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
 173                         0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
 174                         0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
 175                         0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
 176                         0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
 177                         0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
 178                         0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
 179                         0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
 180                         0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
 181                         0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
 182                 >;
 183         };
 184
 185         dcan1_pins_default: dcan1_pins_default {
 186                 pinctrl-single,pins = <
 187                         0x3d0   (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
 188                         0x418   (PULL_UP | MUX_MODE1)   /* wakeup0.dcan1_rx */
 189                 >;
 190         };
 191
 192         dcan1_pins_sleep: dcan1_pins_sleep {
 193                 pinctrl-single,pins = <
 194                         0x3d0   (MUX_MODE15 | PULL_UP)  /* dcan1_tx.off */
 195                         0x418   (MUX_MODE15 | PULL_UP)  /* wakeup0.off */
 196                 >;
 197         };
 198
 199         qspi1_pins: pinmux_qspi1_pins {
 200                 pinctrl-single,pins = <
 201                         0x74 (PIN_OUTPUT | MUX_MODE1)   /* gpmc_a13.qspi1_rtclk */
 202                         0x78 (PIN_INPUT | MUX_MODE1)    /* gpmc_a14.qspi1_d3 */
 203                         0x7c (PIN_INPUT | MUX_MODE1)    /* gpmc_a15.qspi1_d2 */
 204                         0x80 (PIN_INPUT | MUX_MODE1)    /* gpmc_a16.qspi1_d1 */
 205                         0x84 (PIN_INPUT | MUX_MODE1)    /* gpmc_a17.qspi1_d0 */
 206                         0x88 (PIN_OUTPUT | MUX_MODE1)   /* qpmc_a18.qspi1_sclk */
 207                         0xb8 (PIN_OUTPUT | MUX_MODE1)   /* gpmc_cs2.qspi1_cs0 */
 208                 >;
 209         };
 210
 211         hdmi_pins: pinmux_hdmi_pins {
 212                 pinctrl-single,pins = <
 213                         0x408 (PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
 214                         0x40c (PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
 215                 >;
 216         };
 217
 218         tpd12s015_pins: pinmux_tpd12s015_pins {
 219                 pinctrl-single,pins = <
 220                         0x3b8 (PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */
 221                 >;
 222         };
 223 };
 224
 225 &i2c1 {
 226         status = "okay";
 227         pinctrl-names = "default";
 228         pinctrl-0 = <&i2c1_pins>;
 229         clock-frequency = <400000>;
 230
 231         tps65917: tps65917@58 {
 232                 compatible = "ti,tps65917";
 233                 reg = <0x58>;
 234
 235                 pinctrl-names = "default";
 236                 pinctrl-0 = <&tps65917_pins_default>;
 237
 238                 interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>;  /* IRQ_SYS_1N */
 239                 interrupt-controller;
 240                 #interrupt-cells = <2>;
 241
 242                 ti,system-power-controller;
 243
 244                 tps65917_pmic {
 245                         compatible = "ti,tps65917-pmic";
 246
 247                         regulators {
 248                                 smps1_reg: smps1 {
 249                                         /* VDD_MPU */
 250                                         regulator-name = "smps1";
 251                                         regulator-min-microvolt = <850000>;
 252                                         regulator-max-microvolt = <1250000>;
 253                                         regulator-always-on;
 254                                         regulator-boot-on;
 255                                 };
 256
 257                                 smps2_reg: smps2 {
 258                                         /* VDD_CORE */
 259                                         regulator-name = "smps2";
 260                                         regulator-min-microvolt = <850000>;
 261                                         regulator-max-microvolt = <1060000>;
 262                                         regulator-boot-on;
 263                                         regulator-always-on;
 264                                 };
 265
 266                                 smps3_reg: smps3 {
 267                                         /* VDD_GPU IVA DSPEVE */
 268                                         regulator-name = "smps3";
 269                                         regulator-min-microvolt = <850000>;
 270                                         regulator-max-microvolt = <1250000>;
 271                                         regulator-boot-on;
 272                                         regulator-always-on;
 273                                 };
 274
 275                                 smps4_reg: smps4 {
 276                                         /* VDDS1V8 */
 277                                         regulator-name = "smps4";
 278                                         regulator-min-microvolt = <1800000>;
 279                                         regulator-max-microvolt = <1800000>;
 280                                         regulator-always-on;
 281                                         regulator-boot-on;
 282                                 };
 283
 284                                 smps5_reg: smps5 {
 285                                         /* VDD_DDR */
 286                                         regulator-name = "smps5";
 287                                         regulator-min-microvolt = <1350000>;
 288                                         regulator-max-microvolt = <1350000>;
 289                                         regulator-boot-on;
 290                                         regulator-always-on;
 291                                 };
 292
 293                                 ldo1_reg: ldo1 {
 294                                         /* LDO1_OUT --> SDIO  */
 295                                         regulator-name = "ldo1";
 296                                         regulator-min-microvolt = <1800000>;
 297                                         regulator-max-microvolt = <3300000>;
 298                                         regulator-boot-on;
 299                                 };
 300
 301                                 ldo2_reg: ldo2 {
 302                                         /* LDO2_OUT --> TP1017 (UNUSED)  */
 303                                         regulator-name = "ldo2";
 304                                         regulator-min-microvolt = <1800000>;
 305                                         regulator-max-microvolt = <3300000>;
 306                                 };
 307
 308                                 ldo3_reg: ldo3 {
 309                                         /* VDDA_1V8_PHY */
 310                                         regulator-name = "ldo3";
 311                                         regulator-min-microvolt = <1800000>;
 312                                         regulator-max-microvolt = <1800000>;
 313                                         regulator-boot-on;
 314                                         regulator-always-on;
 315                                 };
 316
 317                                 ldo5_reg: ldo5 {
 318                                         /* VDDA_1V8_PLL */
 319                                         regulator-name = "ldo5";
 320                                         regulator-min-microvolt = <1800000>;
 321                                         regulator-max-microvolt = <1800000>;
 322                                         regulator-always-on;
 323                                         regulator-boot-on;
 324                                 };
 325
 326                                 ldo4_reg: ldo4 {
 327                                         /* VDDA_3V_USB: VDDA_USBHS33 */
 328                                         regulator-name = "ldo4";
 329                                         regulator-min-microvolt = <3300000>;
 330                                         regulator-max-microvolt = <3300000>;
 331                                         regulator-boot-on;
 332                                 };
 333                         };
 334                 };
 335
 336                 tps65917_power_button {
 337                         compatible = "ti,palmas-pwrbutton";
 338                         interrupt-parent = <&tps65917>;
 339                         interrupts = <1 IRQ_TYPE_NONE>;
 340                         wakeup-source;
 341                         ti,palmas-long-press-seconds = <6>;
 342                 };
 343         };
 344
 345         pcf_gpio_21: gpio@21 {
 346                 compatible = "ti,pcf8575";
 347                 reg = <0x21>;
 348                 lines-initial-states = <0x1408>;
 349                 gpio-controller;
 350                 #gpio-cells = <2>;
 351                 interrupt-parent = <&gpio6>;
 352                 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
 353                 interrupt-controller;
 354                 #interrupt-cells = <2>;
 355
 356                 cpsw_sel_s0 {
 357                         gpio-hog;
 358                         gpios = <4 GPIO_ACTIVE_HIGH>;
 359                         output-low;
 360                 };
 361         };
 362 };
 363
 364 &i2c5 {
 365         status = "okay";
 366         pinctrl-names = "default";
 367         pinctrl-0 = <&i2c5_pins>;
 368         clock-frequency = <400000>;
 369
 370         pcf_hdmi: pcf8575@26 {
 371                 compatible = "nxp,pcf8575";
 372                 reg = <0x26>;
 373                 gpio-controller;
 374                 #gpio-cells = <2>;
 375                 /*
 376                  * initial state is used here to keep the mdio interface
 377                  * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
 378                  * VIN2_S0 driven high otherwise Ethernet stops working
 379                  * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
 380                  */
 381                 lines-initial-states = <0x0f2b>;
 382         };
 383 };
 384
 385 &uart1 {
 386         status = "okay";
 387 };
 388
 389 &elm {
 390         status = "okay";
 391 };
 392
 393 &gpmc {
 394         status = "okay";
 395         pinctrl-names = "default";
 396         pinctrl-0 = <&nand_default>;
 397         ranges = <0 0 0 0x01000000>;    /* minimum GPMC partition = 16MB */
 398         nand@0,0 {
 399                 /* To use NAND, DIP switch SW5 must be set like so:
 400                  * SW5.1 (NAND_SELn) = ON (LOW)
 401                  * SW5.9 (GPMC_WPN) = OFF (HIGH)
 402                  */
 403                 reg = <0 0 4>;          /* device IO registers */
 404                 ti,nand-ecc-opt = "bch8";
 405                 ti,elm-id = <&elm>;
 406                 nand-bus-width = <16>;
 407                 gpmc,device-width = <2>;
 408                 gpmc,sync-clk-ps = <0>;
 409                 gpmc,cs-on-ns = <0>;
 410                 gpmc,cs-rd-off-ns = <80>;
 411                 gpmc,cs-wr-off-ns = <80>;
 412                 gpmc,adv-on-ns = <0>;
 413                 gpmc,adv-rd-off-ns = <60>;
 414                 gpmc,adv-wr-off-ns = <60>;
 415                 gpmc,we-on-ns = <10>;
 416                 gpmc,we-off-ns = <50>;
 417                 gpmc,oe-on-ns = <4>;
 418                 gpmc,oe-off-ns = <40>;
 419                 gpmc,access-ns = <40>;
 420                 gpmc,wr-access-ns = <80>;
 421                 gpmc,rd-cycle-ns = <80>;
 422                 gpmc,wr-cycle-ns = <80>;
 423                 gpmc,bus-turnaround-ns = <0>;
 424                 gpmc,cycle2cycle-delay-ns = <0>;
 425                 gpmc,clk-activation-ns = <0>;
 426                 gpmc,wait-monitoring-ns = <0>;
 427                 gpmc,wr-data-mux-bus-ns = <0>;
 428                 /* MTD partition table */
 429                 /* All SPL-* partitions are sized to minimal length
 430                  * which can be independently programmable. For
 431                  * NAND flash this is equal to size of erase-block */
 432                 #address-cells = <1>;
 433                 #size-cells = <1>;
 434                 partition@0 {
 435                         label = "NAND.SPL";
 436                         reg = <0x00000000 0x000020000>;
 437                 };
 438                 partition@1 {
 439                         label = "NAND.SPL.backup1";
 440                         reg = <0x00020000 0x00020000>;
 441                 };
 442                 partition@2 {
 443                         label = "NAND.SPL.backup2";
 444                         reg = <0x00040000 0x00020000>;
 445                 };
 446                 partition@3 {
 447                         label = "NAND.SPL.backup3";
 448                         reg = <0x00060000 0x00020000>;
 449                 };
 450                 partition@4 {
 451                         label = "NAND.u-boot-spl-os";
 452                         reg = <0x00080000 0x00040000>;
 453                 };
 454                 partition@5 {
 455                         label = "NAND.u-boot";
 456                         reg = <0x000c0000 0x00100000>;
 457                 };
 458                 partition@6 {
 459                         label = "NAND.u-boot-env";
 460                         reg = <0x001c0000 0x00020000>;
 461                 };
 462                 partition@7 {
 463                         label = "NAND.u-boot-env.backup1";
 464                         reg = <0x001e0000 0x00020000>;
 465                 };
 466                 partition@8 {
 467                         label = "NAND.kernel";
 468                         reg = <0x00200000 0x00800000>;
 469                 };
 470                 partition@9 {
 471                         label = "NAND.file-system";
 472                         reg = <0x00a00000 0x0f600000>;
 473                 };
 474         };
 475 };
 476
 477 &usb2_phy1 {
 478         phy-supply = <&ldo4_reg>;
 479 };
 480
 481 &usb2_phy2 {
 482         phy-supply = <&ldo4_reg>;
 483 };
 484
 485 &omap_dwc3_1 {
 486         extcon = <&extcon_usb1>;
 487 };
 488
 489 &omap_dwc3_2 {
 490         extcon = <&extcon_usb2>;
 491 };
 492
 493 &usb1 {
 494         dr_mode = "peripheral";
 495         pinctrl-names = "default";
 496         pinctrl-0 = <&usb1_pins>;
 497 };
 498
 499 &usb2 {
 500         dr_mode = "host";
 501         pinctrl-names = "default";
 502         pinctrl-0 = <&usb2_pins>;
 503 };
 504
 505 &mmc1 {
 506         status = "okay";
 507         pinctrl-names = "default";
 508         pinctrl-0 = <&mmc1_pins_default>;
 509         vmmc-supply = <&evm_3v3_sd>;
 510         vmmc_aux-supply = <&ldo1_reg>;
 511         bus-width = <4>;
 512         /*
 513          * SDCD signal is not being used here - using the fact that GPIO mode
 514          * is a viable alternative
 515          */
 516         cd-gpios = <&gpio6 27 0>;
 517 };
 518
 519 &mmc2 {
 520         /* SW5-3 in ON position */
 521         status = "okay";
 522         pinctrl-names = "default";
 523         pinctrl-0 = <&mmc2_pins_default>;
 524
 525         vmmc-supply = <&evm_3v3>;
 526         bus-width = <8>;
 527         ti,non-removable;
 528 };
 529
 530 &dra7_pmx_core {
 531         cpsw_default: cpsw_default {
 532                 pinctrl-single,pins = <
 533                         /* Slave 2 */
 534                         0x198 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d12.rgmii1_txc */
 535                         0x19c (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d13.rgmii1_tctl */
 536                         0x1a0 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d14.rgmii1_td3 */
 537                         0x1a4 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d15.rgmii1_td2 */
 538                         0x1a8 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d16.rgmii1_td1 */
 539                         0x1ac (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d17.rgmii1_td0 */
 540                         0x1b0 (PIN_INPUT | MUX_MODE3)   /* vin2a_d18.rgmii1_rclk */
 541                         0x1b4 (PIN_INPUT | MUX_MODE3)   /* vin2a_d19.rgmii1_rctl */
 542                         0x1b8 (PIN_INPUT | MUX_MODE3)   /* vin2a_d20.rgmii1_rd3 */
 543                         0x1bc (PIN_INPUT | MUX_MODE3)   /* vin2a_d21.rgmii1_rd2 */
 544                         0x1c0 (PIN_INPUT | MUX_MODE3)   /* vin2a_d22.rgmii1_rd1 */
 545                         0x1c4 (PIN_INPUT | MUX_MODE3)   /* vin2a_d23.rgmii1_rd0 */
 546                 >;
 547
 548         };
 549
 550         cpsw_sleep: cpsw_sleep {
 551                 pinctrl-single,pins = <
 552                         /* Slave 2 */
 553                         0x198 (MUX_MODE15)
 554                         0x19c (MUX_MODE15)
 555                         0x1a0 (MUX_MODE15)
 556                         0x1a4 (MUX_MODE15)
 557                         0x1a8 (MUX_MODE15)
 558                         0x1ac (MUX_MODE15)
 559                         0x1b0 (MUX_MODE15)
 560                         0x1b4 (MUX_MODE15)
 561                         0x1b8 (MUX_MODE15)
 562                         0x1bc (MUX_MODE15)
 563                         0x1c0 (MUX_MODE15)
 564                         0x1c4 (MUX_MODE15)
 565                 >;
 566         };
 567
 568         davinci_mdio_default: davinci_mdio_default {
 569                 pinctrl-single,pins = <
 570                         /* MDIO */
 571                         0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0)   /* mdio_d.mdio_d */
 572                         0x240 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mdio_clk.mdio_clk */
 573                 >;
 574         };
 575
 576         davinci_mdio_sleep: davinci_mdio_sleep {
 577                 pinctrl-single,pins = <
 578                         0x23c (MUX_MODE15)
 579                         0x240 (MUX_MODE15)
 580                 >;
 581         };
 582 };
 583
 584 &mac {
 585         status = "okay";
 586         pinctrl-names = "default", "sleep";
 587         pinctrl-0 = <&cpsw_default>;
 588         pinctrl-1 = <&cpsw_sleep>;
 589         slaves = <1>;
 590 };
 591
 592 &cpsw_emac0 {
 593         phy_id = <&davinci_mdio>, <3>;
 594         phy-mode = "rgmii";
 595 };
 596
 597 &davinci_mdio {
 598         pinctrl-names = "default", "sleep";
 599         pinctrl-0 = <&davinci_mdio_default>;
 600         pinctrl-1 = <&davinci_mdio_sleep>;
 601 };
 602
 603 &dcan1 {
 604         status = "ok";
 605         pinctrl-names = "default", "sleep";
 606         pinctrl-0 = <&dcan1_pins_default>;
 607         pinctrl-1 = <&dcan1_pins_sleep>;
 608 };
 609
 610 &qspi {
 611         status = "okay";
 612         pinctrl-names = "default";
 613         pinctrl-0 = <&qspi1_pins>;
 614
 615         spi-max-frequency = <48000000>;
 616         m25p80@0 {
 617                 compatible = "s25fl256s1";
 618                 spi-max-frequency = <48000000>;
 619                 reg = <0>;
 620                 spi-tx-bus-width = <1>;
 621                 spi-rx-bus-width = <4>;
 622                 spi-cpol;
 623                 spi-cpha;
 624                 #address-cells = <1>;
 625                 #size-cells = <1>;
 626
 627                 /* MTD partition table.
 628                  * The ROM checks the first four physical blocks
 629                  * for a valid file to boot and the flash here is
 630                  * 64KiB block size.
 631                  */
 632                 partition@0 {
 633                         label = "QSPI.SPL";
 634                         reg = <0x00000000 0x000010000>;
 635                 };
 636                 partition@1 {
 637                         label = "QSPI.SPL.backup1";
 638                         reg = <0x00010000 0x00010000>;
 639                 };
 640                 partition@2 {
 641                         label = "QSPI.SPL.backup2";
 642                         reg = <0x00020000 0x00010000>;
 643                 };
 644                 partition@3 {
 645                         label = "QSPI.SPL.backup3";
 646                         reg = <0x00030000 0x00010000>;
 647                 };
 648                 partition@4 {
 649                         label = "QSPI.u-boot";
 650                         reg = <0x00040000 0x00100000>;
 651                 };
 652                 partition@5 {
 653                         label = "QSPI.u-boot-spl-os";
 654                         reg = <0x00140000 0x00080000>;
 655                 };
 656                 partition@6 {
 657                         label = "QSPI.u-boot-env";
 658                         reg = <0x001c0000 0x00010000>;
 659                 };
 660                 partition@7 {
 661                         label = "QSPI.u-boot-env.backup1";
 662                         reg = <0x001d0000 0x0010000>;
 663                 };
 664                 partition@8 {
 665                         label = "QSPI.kernel";
 666                         reg = <0x001e0000 0x0800000>;
 667                 };
 668                 partition@9 {
 669                         label = "QSPI.file-system";
 670                         reg = <0x009e0000 0x01620000>;
 671                 };
 672         };
 673 };
 674
 675 &dss {
 676         status = "ok";
 677
 678         vdda_video-supply = <&ldo5_reg>;
 679 };
 680
 681 &hdmi {
 682         status = "ok";
 683         vdda-supply = <&ldo3_reg>;
 684
 685         pinctrl-names = "default";
 686         pinctrl-0 = <&hdmi_pins>;
 687
 688         port {
 689                 hdmi_out: endpoint {
 690                         remote-endpoint = <&tpd12s015_in>;
 691                 };
 692         };
 693 };