2 * Device Tree Source for DRA7xx clock data
4 * Copyright (C) 2013 Texas Instruments, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 atl_clkin0_ck: atl_clkin0_ck {
13 compatible = "ti,dra7-atl-clock";
14 clocks = <&atl_gfclk_mux>;
17 atl_clkin1_ck: atl_clkin1_ck {
19 compatible = "ti,dra7-atl-clock";
20 clocks = <&atl_gfclk_mux>;
23 atl_clkin2_ck: atl_clkin2_ck {
25 compatible = "ti,dra7-atl-clock";
26 clocks = <&atl_gfclk_mux>;
29 atl_clkin3_ck: atl_clkin3_ck {
31 compatible = "ti,dra7-atl-clock";
32 clocks = <&atl_gfclk_mux>;
35 hdmi_clkin_ck: hdmi_clkin_ck {
37 compatible = "fixed-clock";
38 clock-frequency = <0>;
41 mlb_clkin_ck: mlb_clkin_ck {
43 compatible = "fixed-clock";
44 clock-frequency = <0>;
47 mlbp_clkin_ck: mlbp_clkin_ck {
49 compatible = "fixed-clock";
50 clock-frequency = <0>;
53 pciesref_acs_clk_ck: pciesref_acs_clk_ck {
55 compatible = "fixed-clock";
56 clock-frequency = <100000000>;
59 ref_clkin0_ck: ref_clkin0_ck {
61 compatible = "fixed-clock";
62 clock-frequency = <0>;
65 ref_clkin1_ck: ref_clkin1_ck {
67 compatible = "fixed-clock";
68 clock-frequency = <0>;
71 ref_clkin2_ck: ref_clkin2_ck {
73 compatible = "fixed-clock";
74 clock-frequency = <0>;
77 ref_clkin3_ck: ref_clkin3_ck {
79 compatible = "fixed-clock";
80 clock-frequency = <0>;
83 rmii_clk_ck: rmii_clk_ck {
85 compatible = "fixed-clock";
86 clock-frequency = <0>;
89 sdvenc_clkin_ck: sdvenc_clkin_ck {
91 compatible = "fixed-clock";
92 clock-frequency = <0>;
95 secure_32k_clk_src_ck: secure_32k_clk_src_ck {
97 compatible = "fixed-clock";
98 clock-frequency = <32768>;
101 sys_clk32_crystal_ck: sys_clk32_crystal_ck {
103 compatible = "fixed-clock";
104 clock-frequency = <32768>;
107 sys_clk32_pseudo_ck: sys_clk32_pseudo_ck {
109 compatible = "fixed-factor-clock";
110 clocks = <&sys_clkin1>;
115 virt_12000000_ck: virt_12000000_ck {
117 compatible = "fixed-clock";
118 clock-frequency = <12000000>;
121 virt_13000000_ck: virt_13000000_ck {
123 compatible = "fixed-clock";
124 clock-frequency = <13000000>;
127 virt_16800000_ck: virt_16800000_ck {
129 compatible = "fixed-clock";
130 clock-frequency = <16800000>;
133 virt_19200000_ck: virt_19200000_ck {
135 compatible = "fixed-clock";
136 clock-frequency = <19200000>;
139 virt_20000000_ck: virt_20000000_ck {
141 compatible = "fixed-clock";
142 clock-frequency = <20000000>;
145 virt_26000000_ck: virt_26000000_ck {
147 compatible = "fixed-clock";
148 clock-frequency = <26000000>;
151 virt_27000000_ck: virt_27000000_ck {
153 compatible = "fixed-clock";
154 clock-frequency = <27000000>;
157 virt_38400000_ck: virt_38400000_ck {
159 compatible = "fixed-clock";
160 clock-frequency = <38400000>;
163 sys_clkin2: sys_clkin2 {
165 compatible = "fixed-clock";
166 clock-frequency = <22579200>;
169 usb_otg_clkin_ck: usb_otg_clkin_ck {
171 compatible = "fixed-clock";
172 clock-frequency = <0>;
175 video1_clkin_ck: video1_clkin_ck {
177 compatible = "fixed-clock";
178 clock-frequency = <0>;
181 video1_m2_clkin_ck: video1_m2_clkin_ck {
183 compatible = "fixed-clock";
184 clock-frequency = <0>;
187 video2_clkin_ck: video2_clkin_ck {
189 compatible = "fixed-clock";
190 clock-frequency = <0>;
193 video2_m2_clkin_ck: video2_m2_clkin_ck {
195 compatible = "fixed-clock";
196 clock-frequency = <0>;
199 dpll_abe_ck: dpll_abe_ck@1e0 {
201 compatible = "ti,omap4-dpll-m4xen-clock";
202 clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
203 reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
206 dpll_abe_x2_ck: dpll_abe_x2_ck {
208 compatible = "ti,omap4-dpll-x2-clock";
209 clocks = <&dpll_abe_ck>;
212 dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
214 compatible = "ti,divider-clock";
215 clocks = <&dpll_abe_x2_ck>;
217 ti,autoidle-shift = <8>;
219 ti,index-starts-at-one;
220 ti,invert-autoidle-bit;
223 abe_clk: abe_clk@108 {
225 compatible = "ti,divider-clock";
226 clocks = <&dpll_abe_m2x2_ck>;
229 ti,index-power-of-two;
232 dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 {
234 compatible = "ti,divider-clock";
235 clocks = <&dpll_abe_ck>;
237 ti,autoidle-shift = <8>;
239 ti,index-starts-at-one;
240 ti,invert-autoidle-bit;
243 dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
245 compatible = "ti,divider-clock";
246 clocks = <&dpll_abe_x2_ck>;
248 ti,autoidle-shift = <8>;
250 ti,index-starts-at-one;
251 ti,invert-autoidle-bit;
254 dpll_core_byp_mux: dpll_core_byp_mux@12c {
256 compatible = "ti,mux-clock";
257 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
262 dpll_core_ck: dpll_core_ck@120 {
264 compatible = "ti,omap4-dpll-core-clock";
265 clocks = <&sys_clkin1>, <&dpll_core_byp_mux>;
266 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
269 dpll_core_x2_ck: dpll_core_x2_ck {
271 compatible = "ti,omap4-dpll-x2-clock";
272 clocks = <&dpll_core_ck>;
275 dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c {
277 compatible = "ti,divider-clock";
278 clocks = <&dpll_core_x2_ck>;
280 ti,autoidle-shift = <8>;
282 ti,index-starts-at-one;
283 ti,invert-autoidle-bit;
286 mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
288 compatible = "fixed-factor-clock";
289 clocks = <&dpll_core_h12x2_ck>;
294 dpll_mpu_ck: dpll_mpu_ck@160 {
296 compatible = "ti,omap5-mpu-dpll-clock";
297 clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
298 reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
301 dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
303 compatible = "ti,divider-clock";
304 clocks = <&dpll_mpu_ck>;
306 ti,autoidle-shift = <8>;
308 ti,index-starts-at-one;
309 ti,invert-autoidle-bit;
312 mpu_dclk_div: mpu_dclk_div {
314 compatible = "fixed-factor-clock";
315 clocks = <&dpll_mpu_m2_ck>;
320 dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div {
322 compatible = "fixed-factor-clock";
323 clocks = <&dpll_core_h12x2_ck>;
328 dpll_dsp_byp_mux: dpll_dsp_byp_mux@240 {
330 compatible = "ti,mux-clock";
331 clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
336 dpll_dsp_ck: dpll_dsp_ck@234 {
338 compatible = "ti,omap4-dpll-clock";
339 clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
340 reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
343 dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 {
345 compatible = "ti,divider-clock";
346 clocks = <&dpll_dsp_ck>;
348 ti,autoidle-shift = <8>;
350 ti,index-starts-at-one;
351 ti,invert-autoidle-bit;
354 iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
356 compatible = "fixed-factor-clock";
357 clocks = <&dpll_core_h12x2_ck>;
362 dpll_iva_byp_mux: dpll_iva_byp_mux@1ac {
364 compatible = "ti,mux-clock";
365 clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
370 dpll_iva_ck: dpll_iva_ck@1a0 {
372 compatible = "ti,omap4-dpll-clock";
373 clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
374 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
377 dpll_iva_m2_ck: dpll_iva_m2_ck@1b0 {
379 compatible = "ti,divider-clock";
380 clocks = <&dpll_iva_ck>;
382 ti,autoidle-shift = <8>;
384 ti,index-starts-at-one;
385 ti,invert-autoidle-bit;
390 compatible = "fixed-factor-clock";
391 clocks = <&dpll_iva_m2_ck>;
396 dpll_gpu_byp_mux: dpll_gpu_byp_mux@2e4 {
398 compatible = "ti,mux-clock";
399 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
404 dpll_gpu_ck: dpll_gpu_ck@2d8 {
406 compatible = "ti,omap4-dpll-clock";
407 clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
408 reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
411 dpll_gpu_m2_ck: dpll_gpu_m2_ck@2e8 {
413 compatible = "ti,divider-clock";
414 clocks = <&dpll_gpu_ck>;
416 ti,autoidle-shift = <8>;
418 ti,index-starts-at-one;
419 ti,invert-autoidle-bit;
422 dpll_core_m2_ck: dpll_core_m2_ck@130 {
424 compatible = "ti,divider-clock";
425 clocks = <&dpll_core_ck>;
427 ti,autoidle-shift = <8>;
429 ti,index-starts-at-one;
430 ti,invert-autoidle-bit;
433 core_dpll_out_dclk_div: core_dpll_out_dclk_div {
435 compatible = "fixed-factor-clock";
436 clocks = <&dpll_core_m2_ck>;
441 dpll_ddr_byp_mux: dpll_ddr_byp_mux@21c {
443 compatible = "ti,mux-clock";
444 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
449 dpll_ddr_ck: dpll_ddr_ck@210 {
451 compatible = "ti,omap4-dpll-clock";
452 clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>;
453 reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
456 dpll_ddr_m2_ck: dpll_ddr_m2_ck@220 {
458 compatible = "ti,divider-clock";
459 clocks = <&dpll_ddr_ck>;
461 ti,autoidle-shift = <8>;
463 ti,index-starts-at-one;
464 ti,invert-autoidle-bit;
467 dpll_gmac_byp_mux: dpll_gmac_byp_mux@2b4 {
469 compatible = "ti,mux-clock";
470 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
475 dpll_gmac_ck: dpll_gmac_ck@2a8 {
477 compatible = "ti,omap4-dpll-clock";
478 clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;
479 reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
482 dpll_gmac_m2_ck: dpll_gmac_m2_ck@2b8 {
484 compatible = "ti,divider-clock";
485 clocks = <&dpll_gmac_ck>;
487 ti,autoidle-shift = <8>;
489 ti,index-starts-at-one;
490 ti,invert-autoidle-bit;
493 video2_dclk_div: video2_dclk_div {
495 compatible = "fixed-factor-clock";
496 clocks = <&video2_m2_clkin_ck>;
501 video1_dclk_div: video1_dclk_div {
503 compatible = "fixed-factor-clock";
504 clocks = <&video1_m2_clkin_ck>;
509 hdmi_dclk_div: hdmi_dclk_div {
511 compatible = "fixed-factor-clock";
512 clocks = <&hdmi_clkin_ck>;
517 per_dpll_hs_clk_div: per_dpll_hs_clk_div {
519 compatible = "fixed-factor-clock";
520 clocks = <&dpll_abe_m3x2_ck>;
525 usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
527 compatible = "fixed-factor-clock";
528 clocks = <&dpll_abe_m3x2_ck>;
533 eve_dpll_hs_clk_div: eve_dpll_hs_clk_div {
535 compatible = "fixed-factor-clock";
536 clocks = <&dpll_core_h12x2_ck>;
541 dpll_eve_byp_mux: dpll_eve_byp_mux@290 {
543 compatible = "ti,mux-clock";
544 clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
549 dpll_eve_ck: dpll_eve_ck@284 {
551 compatible = "ti,omap4-dpll-clock";
552 clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>;
553 reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
556 dpll_eve_m2_ck: dpll_eve_m2_ck@294 {
558 compatible = "ti,divider-clock";
559 clocks = <&dpll_eve_ck>;
561 ti,autoidle-shift = <8>;
563 ti,index-starts-at-one;
564 ti,invert-autoidle-bit;
567 eve_dclk_div: eve_dclk_div {
569 compatible = "fixed-factor-clock";
570 clocks = <&dpll_eve_m2_ck>;
575 dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 {
577 compatible = "ti,divider-clock";
578 clocks = <&dpll_core_x2_ck>;
580 ti,autoidle-shift = <8>;
582 ti,index-starts-at-one;
583 ti,invert-autoidle-bit;
586 dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 {
588 compatible = "ti,divider-clock";
589 clocks = <&dpll_core_x2_ck>;
591 ti,autoidle-shift = <8>;
593 ti,index-starts-at-one;
594 ti,invert-autoidle-bit;
597 dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 {
599 compatible = "ti,divider-clock";
600 clocks = <&dpll_core_x2_ck>;
602 ti,autoidle-shift = <8>;
604 ti,index-starts-at-one;
605 ti,invert-autoidle-bit;
608 dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 {
610 compatible = "ti,divider-clock";
611 clocks = <&dpll_core_x2_ck>;
613 ti,autoidle-shift = <8>;
615 ti,index-starts-at-one;
616 ti,invert-autoidle-bit;
619 dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c {
621 compatible = "ti,divider-clock";
622 clocks = <&dpll_core_x2_ck>;
624 ti,autoidle-shift = <8>;
626 ti,index-starts-at-one;
627 ti,invert-autoidle-bit;
630 dpll_ddr_x2_ck: dpll_ddr_x2_ck {
632 compatible = "ti,omap4-dpll-x2-clock";
633 clocks = <&dpll_ddr_ck>;
636 dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck@228 {
638 compatible = "ti,divider-clock";
639 clocks = <&dpll_ddr_x2_ck>;
641 ti,autoidle-shift = <8>;
643 ti,index-starts-at-one;
644 ti,invert-autoidle-bit;
647 dpll_dsp_x2_ck: dpll_dsp_x2_ck {
649 compatible = "ti,omap4-dpll-x2-clock";
650 clocks = <&dpll_dsp_ck>;
653 dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck@248 {
655 compatible = "ti,divider-clock";
656 clocks = <&dpll_dsp_x2_ck>;
658 ti,autoidle-shift = <8>;
660 ti,index-starts-at-one;
661 ti,invert-autoidle-bit;
664 dpll_gmac_x2_ck: dpll_gmac_x2_ck {
666 compatible = "ti,omap4-dpll-x2-clock";
667 clocks = <&dpll_gmac_ck>;
670 dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck@2c0 {
672 compatible = "ti,divider-clock";
673 clocks = <&dpll_gmac_x2_ck>;
675 ti,autoidle-shift = <8>;
677 ti,index-starts-at-one;
678 ti,invert-autoidle-bit;
681 dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck@2c4 {
683 compatible = "ti,divider-clock";
684 clocks = <&dpll_gmac_x2_ck>;
686 ti,autoidle-shift = <8>;
688 ti,index-starts-at-one;
689 ti,invert-autoidle-bit;
692 dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck@2c8 {
694 compatible = "ti,divider-clock";
695 clocks = <&dpll_gmac_x2_ck>;
697 ti,autoidle-shift = <8>;
699 ti,index-starts-at-one;
700 ti,invert-autoidle-bit;
703 dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck@2bc {
705 compatible = "ti,divider-clock";
706 clocks = <&dpll_gmac_x2_ck>;
708 ti,autoidle-shift = <8>;
710 ti,index-starts-at-one;
711 ti,invert-autoidle-bit;
714 gmii_m_clk_div: gmii_m_clk_div {
716 compatible = "fixed-factor-clock";
717 clocks = <&dpll_gmac_h11x2_ck>;
722 hdmi_clk2_div: hdmi_clk2_div {
724 compatible = "fixed-factor-clock";
725 clocks = <&hdmi_clkin_ck>;
730 hdmi_div_clk: hdmi_div_clk {
732 compatible = "fixed-factor-clock";
733 clocks = <&hdmi_clkin_ck>;
738 l3_iclk_div: l3_iclk_div@100 {
740 compatible = "ti,divider-clock";
744 clocks = <&dpll_core_h12x2_ck>;
745 ti,index-power-of-two;
748 l4_root_clk_div: l4_root_clk_div {
750 compatible = "fixed-factor-clock";
751 clocks = <&l3_iclk_div>;
756 video1_clk2_div: video1_clk2_div {
758 compatible = "fixed-factor-clock";
759 clocks = <&video1_clkin_ck>;
764 video1_div_clk: video1_div_clk {
766 compatible = "fixed-factor-clock";
767 clocks = <&video1_clkin_ck>;
772 video2_clk2_div: video2_clk2_div {
774 compatible = "fixed-factor-clock";
775 clocks = <&video2_clkin_ck>;
780 video2_div_clk: video2_div_clk {
782 compatible = "fixed-factor-clock";
783 clocks = <&video2_clkin_ck>;
788 ipu1_gfclk_mux: ipu1_gfclk_mux@520 {
790 compatible = "ti,mux-clock";
791 clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
796 mcasp1_ahclkr_mux: mcasp1_ahclkr_mux@550 {
798 compatible = "ti,mux-clock";
799 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
804 mcasp1_ahclkx_mux: mcasp1_ahclkx_mux@550 {
806 compatible = "ti,mux-clock";
807 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
812 mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux@550 {
814 compatible = "ti,mux-clock";
815 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
820 timer5_gfclk_mux: timer5_gfclk_mux@558 {
822 compatible = "ti,mux-clock";
823 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
828 timer6_gfclk_mux: timer6_gfclk_mux@560 {
830 compatible = "ti,mux-clock";
831 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
836 timer7_gfclk_mux: timer7_gfclk_mux@568 {
838 compatible = "ti,mux-clock";
839 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
844 timer8_gfclk_mux: timer8_gfclk_mux@570 {
846 compatible = "ti,mux-clock";
847 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
852 uart6_gfclk_mux: uart6_gfclk_mux@580 {
854 compatible = "ti,mux-clock";
855 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
862 compatible = "fixed-clock";
863 clock-frequency = <0>;
867 sys_clkin1: sys_clkin1@110 {
869 compatible = "ti,mux-clock";
870 clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
872 ti,index-starts-at-one;
875 abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux@118 {
877 compatible = "ti,mux-clock";
878 clocks = <&sys_clkin1>, <&sys_clkin2>;
882 abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@114 {
884 compatible = "ti,mux-clock";
885 clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
889 abe_dpll_clk_mux: abe_dpll_clk_mux@10c {
891 compatible = "ti,mux-clock";
892 clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
896 abe_24m_fclk: abe_24m_fclk@11c {
898 compatible = "ti,divider-clock";
899 clocks = <&dpll_abe_m2x2_ck>;
901 ti,dividers = <8>, <16>;
904 aess_fclk: aess_fclk@178 {
906 compatible = "ti,divider-clock";
912 abe_giclk_div: abe_giclk_div@174 {
914 compatible = "ti,divider-clock";
915 clocks = <&aess_fclk>;
920 abe_lp_clk_div: abe_lp_clk_div@1d8 {
922 compatible = "ti,divider-clock";
923 clocks = <&dpll_abe_m2x2_ck>;
925 ti,dividers = <16>, <32>;
928 abe_sys_clk_div: abe_sys_clk_div@120 {
930 compatible = "ti,divider-clock";
931 clocks = <&sys_clkin1>;
936 adc_gfclk_mux: adc_gfclk_mux@1dc {
938 compatible = "ti,mux-clock";
939 clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
943 sys_clk1_dclk_div: sys_clk1_dclk_div@1c8 {
945 compatible = "ti,divider-clock";
946 clocks = <&sys_clkin1>;
949 ti,index-power-of-two;
952 sys_clk2_dclk_div: sys_clk2_dclk_div@1cc {
954 compatible = "ti,divider-clock";
955 clocks = <&sys_clkin2>;
958 ti,index-power-of-two;
961 per_abe_x1_dclk_div: per_abe_x1_dclk_div@1bc {
963 compatible = "ti,divider-clock";
964 clocks = <&dpll_abe_m2_ck>;
967 ti,index-power-of-two;
970 dsp_gclk_div: dsp_gclk_div@18c {
972 compatible = "ti,divider-clock";
973 clocks = <&dpll_dsp_m2_ck>;
976 ti,index-power-of-two;
979 gpu_dclk: gpu_dclk@1a0 {
981 compatible = "ti,divider-clock";
982 clocks = <&dpll_gpu_m2_ck>;
985 ti,index-power-of-two;
988 emif_phy_dclk_div: emif_phy_dclk_div@190 {
990 compatible = "ti,divider-clock";
991 clocks = <&dpll_ddr_m2_ck>;
994 ti,index-power-of-two;
997 gmac_250m_dclk_div: gmac_250m_dclk_div@19c {
999 compatible = "ti,divider-clock";
1000 clocks = <&dpll_gmac_m2_ck>;
1003 ti,index-power-of-two;
1006 l3init_480m_dclk_div: l3init_480m_dclk_div@1ac {
1008 compatible = "ti,divider-clock";
1009 clocks = <&dpll_usb_m2_ck>;
1012 ti,index-power-of-two;
1015 usb_otg_dclk_div: usb_otg_dclk_div@184 {
1017 compatible = "ti,divider-clock";
1018 clocks = <&usb_otg_clkin_ck>;
1021 ti,index-power-of-two;
1024 sata_dclk_div: sata_dclk_div@1c0 {
1026 compatible = "ti,divider-clock";
1027 clocks = <&sys_clkin1>;
1030 ti,index-power-of-two;
1033 pcie2_dclk_div: pcie2_dclk_div@1b8 {
1035 compatible = "ti,divider-clock";
1036 clocks = <&dpll_pcie_ref_m2_ck>;
1039 ti,index-power-of-two;
1042 pcie_dclk_div: pcie_dclk_div@1b4 {
1044 compatible = "ti,divider-clock";
1045 clocks = <&apll_pcie_m2_ck>;
1048 ti,index-power-of-two;
1051 emu_dclk_div: emu_dclk_div@194 {
1053 compatible = "ti,divider-clock";
1054 clocks = <&sys_clkin1>;
1057 ti,index-power-of-two;
1060 secure_32k_dclk_div: secure_32k_dclk_div@1c4 {
1062 compatible = "ti,divider-clock";
1063 clocks = <&secure_32k_clk_src_ck>;
1066 ti,index-power-of-two;
1069 clkoutmux0_clk_mux: clkoutmux0_clk_mux@158 {
1071 compatible = "ti,mux-clock";
1072 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1076 clkoutmux1_clk_mux: clkoutmux1_clk_mux@15c {
1078 compatible = "ti,mux-clock";
1079 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1083 clkoutmux2_clk_mux: clkoutmux2_clk_mux@160 {
1085 compatible = "ti,mux-clock";
1086 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1090 custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
1092 compatible = "fixed-factor-clock";
1093 clocks = <&sys_clkin1>;
1098 eve_clk: eve_clk@180 {
1100 compatible = "ti,mux-clock";
1101 clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
1105 hdmi_dpll_clk_mux: hdmi_dpll_clk_mux@164 {
1107 compatible = "ti,mux-clock";
1108 clocks = <&sys_clkin1>, <&sys_clkin2>;
1112 mlb_clk: mlb_clk@134 {
1114 compatible = "ti,divider-clock";
1115 clocks = <&mlb_clkin_ck>;
1118 ti,index-power-of-two;
1121 mlbp_clk: mlbp_clk@130 {
1123 compatible = "ti,divider-clock";
1124 clocks = <&mlbp_clkin_ck>;
1127 ti,index-power-of-two;
1130 per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div@138 {
1132 compatible = "ti,divider-clock";
1133 clocks = <&dpll_abe_m2_ck>;
1136 ti,index-power-of-two;
1139 timer_sys_clk_div: timer_sys_clk_div@144 {
1141 compatible = "ti,divider-clock";
1142 clocks = <&sys_clkin1>;
1147 video1_dpll_clk_mux: video1_dpll_clk_mux@168 {
1149 compatible = "ti,mux-clock";
1150 clocks = <&sys_clkin1>, <&sys_clkin2>;
1154 video2_dpll_clk_mux: video2_dpll_clk_mux@16c {
1156 compatible = "ti,mux-clock";
1157 clocks = <&sys_clkin1>, <&sys_clkin2>;
1161 wkupaon_iclk_mux: wkupaon_iclk_mux@108 {
1163 compatible = "ti,mux-clock";
1164 clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
1168 gpio1_dbclk: gpio1_dbclk@1838 {
1170 compatible = "ti,gate-clock";
1171 clocks = <&sys_32k_ck>;
1176 dcan1_sys_clk_mux: dcan1_sys_clk_mux@1888 {
1178 compatible = "ti,mux-clock";
1179 clocks = <&sys_clkin1>, <&sys_clkin2>;
1180 ti,bit-shift = <24>;
1184 timer1_gfclk_mux: timer1_gfclk_mux@1840 {
1186 compatible = "ti,mux-clock";
1187 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1188 ti,bit-shift = <24>;
1192 uart10_gfclk_mux: uart10_gfclk_mux@1880 {
1194 compatible = "ti,mux-clock";
1195 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1196 ti,bit-shift = <24>;
1201 dpll_pcie_ref_ck: dpll_pcie_ref_ck@200 {
1203 compatible = "ti,omap4-dpll-clock";
1204 clocks = <&sys_clkin1>, <&sys_clkin1>;
1205 reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
1208 dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck@210 {
1210 compatible = "ti,divider-clock";
1211 clocks = <&dpll_pcie_ref_ck>;
1213 ti,autoidle-shift = <8>;
1215 ti,index-starts-at-one;
1216 ti,invert-autoidle-bit;
1219 apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
1220 compatible = "ti,mux-clock";
1221 clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;
1227 apll_pcie_ck: apll_pcie_ck@21c {
1229 compatible = "ti,dra7-apll-clock";
1230 clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
1231 reg = <0x021c>, <0x0220>;
1234 optfclk_pciephy1_32khz: optfclk_pciephy1_32khz@4a0093b0 {
1235 compatible = "ti,gate-clock";
1236 clocks = <&sys_32k_ck>;
1242 optfclk_pciephy2_32khz: optfclk_pciephy2_32khz@4a0093b8 {
1243 compatible = "ti,gate-clock";
1244 clocks = <&sys_32k_ck>;
1250 optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
1251 compatible = "ti,divider-clock";
1252 clocks = <&apll_pcie_ck>;
1255 ti,dividers = <2>, <1>;
1260 optfclk_pciephy1_clk: optfclk_pciephy1_clk@4a0093b0 {
1261 compatible = "ti,gate-clock";
1262 clocks = <&apll_pcie_ck>;
1268 optfclk_pciephy2_clk: optfclk_pciephy2_clk@4a0093b8 {
1269 compatible = "ti,gate-clock";
1270 clocks = <&apll_pcie_ck>;
1276 optfclk_pciephy1_div_clk: optfclk_pciephy1_div_clk@4a0093b0 {
1277 compatible = "ti,gate-clock";
1278 clocks = <&optfclk_pciephy_div>;
1281 ti,bit-shift = <10>;
1284 optfclk_pciephy2_div_clk: optfclk_pciephy2_div_clk@4a0093b8 {
1285 compatible = "ti,gate-clock";
1286 clocks = <&optfclk_pciephy_div>;
1289 ti,bit-shift = <10>;
1292 apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
1294 compatible = "fixed-factor-clock";
1295 clocks = <&apll_pcie_ck>;
1300 apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {
1302 compatible = "fixed-factor-clock";
1303 clocks = <&apll_pcie_ck>;
1308 apll_pcie_m2_ck: apll_pcie_m2_ck {
1310 compatible = "fixed-factor-clock";
1311 clocks = <&apll_pcie_ck>;
1316 dpll_per_byp_mux: dpll_per_byp_mux@14c {
1318 compatible = "ti,mux-clock";
1319 clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
1320 ti,bit-shift = <23>;
1324 dpll_per_ck: dpll_per_ck@140 {
1326 compatible = "ti,omap4-dpll-clock";
1327 clocks = <&sys_clkin1>, <&dpll_per_byp_mux>;
1328 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
1331 dpll_per_m2_ck: dpll_per_m2_ck@150 {
1333 compatible = "ti,divider-clock";
1334 clocks = <&dpll_per_ck>;
1336 ti,autoidle-shift = <8>;
1338 ti,index-starts-at-one;
1339 ti,invert-autoidle-bit;
1342 func_96m_aon_dclk_div: func_96m_aon_dclk_div {
1344 compatible = "fixed-factor-clock";
1345 clocks = <&dpll_per_m2_ck>;
1350 dpll_usb_byp_mux: dpll_usb_byp_mux@18c {
1352 compatible = "ti,mux-clock";
1353 clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
1354 ti,bit-shift = <23>;
1358 dpll_usb_ck: dpll_usb_ck@180 {
1360 compatible = "ti,omap4-dpll-j-type-clock";
1361 clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>;
1362 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
1365 dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
1367 compatible = "ti,divider-clock";
1368 clocks = <&dpll_usb_ck>;
1370 ti,autoidle-shift = <8>;
1372 ti,index-starts-at-one;
1373 ti,invert-autoidle-bit;
1376 dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck@210 {
1378 compatible = "ti,divider-clock";
1379 clocks = <&dpll_pcie_ref_ck>;
1381 ti,autoidle-shift = <8>;
1383 ti,index-starts-at-one;
1384 ti,invert-autoidle-bit;
1387 dpll_per_x2_ck: dpll_per_x2_ck {
1389 compatible = "ti,omap4-dpll-x2-clock";
1390 clocks = <&dpll_per_ck>;
1393 dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 {
1395 compatible = "ti,divider-clock";
1396 clocks = <&dpll_per_x2_ck>;
1398 ti,autoidle-shift = <8>;
1400 ti,index-starts-at-one;
1401 ti,invert-autoidle-bit;
1404 dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c {
1406 compatible = "ti,divider-clock";
1407 clocks = <&dpll_per_x2_ck>;
1409 ti,autoidle-shift = <8>;
1411 ti,index-starts-at-one;
1412 ti,invert-autoidle-bit;
1415 dpll_per_h13x2_ck: dpll_per_h13x2_ck@160 {
1417 compatible = "ti,divider-clock";
1418 clocks = <&dpll_per_x2_ck>;
1420 ti,autoidle-shift = <8>;
1422 ti,index-starts-at-one;
1423 ti,invert-autoidle-bit;
1426 dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 {
1428 compatible = "ti,divider-clock";
1429 clocks = <&dpll_per_x2_ck>;
1431 ti,autoidle-shift = <8>;
1433 ti,index-starts-at-one;
1434 ti,invert-autoidle-bit;
1437 dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
1439 compatible = "ti,divider-clock";
1440 clocks = <&dpll_per_x2_ck>;
1442 ti,autoidle-shift = <8>;
1444 ti,index-starts-at-one;
1445 ti,invert-autoidle-bit;
1448 dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
1450 compatible = "fixed-factor-clock";
1451 clocks = <&dpll_usb_ck>;
1456 func_128m_clk: func_128m_clk {
1458 compatible = "fixed-factor-clock";
1459 clocks = <&dpll_per_h11x2_ck>;
1464 func_12m_fclk: func_12m_fclk {
1466 compatible = "fixed-factor-clock";
1467 clocks = <&dpll_per_m2x2_ck>;
1472 func_24m_clk: func_24m_clk {
1474 compatible = "fixed-factor-clock";
1475 clocks = <&dpll_per_m2_ck>;
1480 func_48m_fclk: func_48m_fclk {
1482 compatible = "fixed-factor-clock";
1483 clocks = <&dpll_per_m2x2_ck>;
1488 func_96m_fclk: func_96m_fclk {
1490 compatible = "fixed-factor-clock";
1491 clocks = <&dpll_per_m2x2_ck>;
1496 l3init_60m_fclk: l3init_60m_fclk@104 {
1498 compatible = "ti,divider-clock";
1499 clocks = <&dpll_usb_m2_ck>;
1501 ti,dividers = <1>, <8>;
1504 clkout2_clk: clkout2_clk@6b0 {
1506 compatible = "ti,gate-clock";
1507 clocks = <&clkoutmux2_clk_mux>;
1512 l3init_960m_gfclk: l3init_960m_gfclk@6c0 {
1514 compatible = "ti,gate-clock";
1515 clocks = <&dpll_usb_clkdcoldo>;
1520 dss_32khz_clk: dss_32khz_clk@1120 {
1522 compatible = "ti,gate-clock";
1523 clocks = <&sys_32k_ck>;
1524 ti,bit-shift = <11>;
1528 dss_48mhz_clk: dss_48mhz_clk@1120 {
1530 compatible = "ti,gate-clock";
1531 clocks = <&func_48m_fclk>;
1536 dss_dss_clk: dss_dss_clk@1120 {
1538 compatible = "ti,gate-clock";
1539 clocks = <&dpll_per_h12x2_ck>;
1545 dss_hdmi_clk: dss_hdmi_clk@1120 {
1547 compatible = "ti,gate-clock";
1548 clocks = <&hdmi_dpll_clk_mux>;
1549 ti,bit-shift = <10>;
1553 dss_video1_clk: dss_video1_clk@1120 {
1555 compatible = "ti,gate-clock";
1556 clocks = <&video1_dpll_clk_mux>;
1557 ti,bit-shift = <12>;
1561 dss_video2_clk: dss_video2_clk@1120 {
1563 compatible = "ti,gate-clock";
1564 clocks = <&video2_dpll_clk_mux>;
1565 ti,bit-shift = <13>;
1569 gpio2_dbclk: gpio2_dbclk@1760 {
1571 compatible = "ti,gate-clock";
1572 clocks = <&sys_32k_ck>;
1577 gpio3_dbclk: gpio3_dbclk@1768 {
1579 compatible = "ti,gate-clock";
1580 clocks = <&sys_32k_ck>;
1585 gpio4_dbclk: gpio4_dbclk@1770 {
1587 compatible = "ti,gate-clock";
1588 clocks = <&sys_32k_ck>;
1593 gpio5_dbclk: gpio5_dbclk@1778 {
1595 compatible = "ti,gate-clock";
1596 clocks = <&sys_32k_ck>;
1601 gpio6_dbclk: gpio6_dbclk@1780 {
1603 compatible = "ti,gate-clock";
1604 clocks = <&sys_32k_ck>;
1609 gpio7_dbclk: gpio7_dbclk@1810 {
1611 compatible = "ti,gate-clock";
1612 clocks = <&sys_32k_ck>;
1617 gpio8_dbclk: gpio8_dbclk@1818 {
1619 compatible = "ti,gate-clock";
1620 clocks = <&sys_32k_ck>;
1625 mmc1_clk32k: mmc1_clk32k@1328 {
1627 compatible = "ti,gate-clock";
1628 clocks = <&sys_32k_ck>;
1633 mmc2_clk32k: mmc2_clk32k@1330 {
1635 compatible = "ti,gate-clock";
1636 clocks = <&sys_32k_ck>;
1641 mmc3_clk32k: mmc3_clk32k@1820 {
1643 compatible = "ti,gate-clock";
1644 clocks = <&sys_32k_ck>;
1649 mmc4_clk32k: mmc4_clk32k@1828 {
1651 compatible = "ti,gate-clock";
1652 clocks = <&sys_32k_ck>;
1657 sata_ref_clk: sata_ref_clk@1388 {
1659 compatible = "ti,gate-clock";
1660 clocks = <&sys_clkin1>;
1665 usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m@13f0 {
1667 compatible = "ti,gate-clock";
1668 clocks = <&l3init_960m_gfclk>;
1673 usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m@1340 {
1675 compatible = "ti,gate-clock";
1676 clocks = <&l3init_960m_gfclk>;
1681 usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@640 {
1683 compatible = "ti,gate-clock";
1684 clocks = <&sys_32k_ck>;
1689 usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k@688 {
1691 compatible = "ti,gate-clock";
1692 clocks = <&sys_32k_ck>;
1697 usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k@698 {
1699 compatible = "ti,gate-clock";
1700 clocks = <&sys_32k_ck>;
1705 atl_dpll_clk_mux: atl_dpll_clk_mux@c00 {
1707 compatible = "ti,mux-clock";
1708 clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>;
1709 ti,bit-shift = <24>;
1713 atl_gfclk_mux: atl_gfclk_mux@c00 {
1715 compatible = "ti,mux-clock";
1716 clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>;
1717 ti,bit-shift = <26>;
1721 gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div@13d0 {
1723 compatible = "ti,divider-clock";
1724 clocks = <&dpll_gmac_m2_ck>;
1725 ti,bit-shift = <24>;
1730 gmac_rft_clk_mux: gmac_rft_clk_mux@13d0 {
1732 compatible = "ti,mux-clock";
1733 clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>;
1734 ti,bit-shift = <25>;
1738 gpu_core_gclk_mux: gpu_core_gclk_mux@1220 {
1740 compatible = "ti,mux-clock";
1741 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
1742 ti,bit-shift = <24>;
1746 gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1220 {
1748 compatible = "ti,mux-clock";
1749 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
1750 ti,bit-shift = <26>;
1754 l3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 {
1756 compatible = "ti,divider-clock";
1757 clocks = <&wkupaon_iclk_mux>;
1758 ti,bit-shift = <24>;
1760 ti,dividers = <8>, <16>, <32>;
1763 mcasp2_ahclkr_mux: mcasp2_ahclkr_mux@1860 {
1765 compatible = "ti,mux-clock";
1766 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1767 ti,bit-shift = <28>;
1771 mcasp2_ahclkx_mux: mcasp2_ahclkx_mux@1860 {
1773 compatible = "ti,mux-clock";
1774 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1775 ti,bit-shift = <24>;
1779 mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux@1860 {
1781 compatible = "ti,mux-clock";
1782 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1783 ti,bit-shift = <22>;
1787 mcasp3_ahclkx_mux: mcasp3_ahclkx_mux@1868 {
1789 compatible = "ti,mux-clock";
1790 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1791 ti,bit-shift = <24>;
1795 mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux@1868 {
1797 compatible = "ti,mux-clock";
1798 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1799 ti,bit-shift = <22>;
1803 mcasp4_ahclkx_mux: mcasp4_ahclkx_mux@1898 {
1805 compatible = "ti,mux-clock";
1806 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1807 ti,bit-shift = <24>;
1811 mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux@1898 {
1813 compatible = "ti,mux-clock";
1814 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1815 ti,bit-shift = <22>;
1819 mcasp5_ahclkx_mux: mcasp5_ahclkx_mux@1878 {
1821 compatible = "ti,mux-clock";
1822 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1823 ti,bit-shift = <24>;
1827 mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux@1878 {
1829 compatible = "ti,mux-clock";
1830 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1831 ti,bit-shift = <22>;
1835 mcasp6_ahclkx_mux: mcasp6_ahclkx_mux@1904 {
1837 compatible = "ti,mux-clock";
1838 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1839 ti,bit-shift = <24>;
1843 mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux@1904 {
1845 compatible = "ti,mux-clock";
1846 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1847 ti,bit-shift = <22>;
1851 mcasp7_ahclkx_mux: mcasp7_ahclkx_mux@1908 {
1853 compatible = "ti,mux-clock";
1854 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1855 ti,bit-shift = <24>;
1859 mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux@1908 {
1861 compatible = "ti,mux-clock";
1862 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1863 ti,bit-shift = <22>;
1867 mcasp8_ahclkx_mux: mcasp8_ahclkx_mux@1890 {
1869 compatible = "ti,mux-clock";
1870 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1871 ti,bit-shift = <22>;
1875 mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux@1890 {
1877 compatible = "ti,mux-clock";
1878 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1879 ti,bit-shift = <24>;
1883 mmc1_fclk_mux: mmc1_fclk_mux@1328 {
1885 compatible = "ti,mux-clock";
1886 clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
1887 ti,bit-shift = <24>;
1891 mmc1_fclk_div: mmc1_fclk_div@1328 {
1893 compatible = "ti,divider-clock";
1894 clocks = <&mmc1_fclk_mux>;
1895 ti,bit-shift = <25>;
1898 ti,index-power-of-two;
1901 mmc2_fclk_mux: mmc2_fclk_mux@1330 {
1903 compatible = "ti,mux-clock";
1904 clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
1905 ti,bit-shift = <24>;
1909 mmc2_fclk_div: mmc2_fclk_div@1330 {
1911 compatible = "ti,divider-clock";
1912 clocks = <&mmc2_fclk_mux>;
1913 ti,bit-shift = <25>;
1916 ti,index-power-of-two;
1919 mmc3_gfclk_mux: mmc3_gfclk_mux@1820 {
1921 compatible = "ti,mux-clock";
1922 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1923 ti,bit-shift = <24>;
1927 mmc3_gfclk_div: mmc3_gfclk_div@1820 {
1929 compatible = "ti,divider-clock";
1930 clocks = <&mmc3_gfclk_mux>;
1931 ti,bit-shift = <25>;
1934 ti,index-power-of-two;
1937 mmc4_gfclk_mux: mmc4_gfclk_mux@1828 {
1939 compatible = "ti,mux-clock";
1940 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1941 ti,bit-shift = <24>;
1945 mmc4_gfclk_div: mmc4_gfclk_div@1828 {
1947 compatible = "ti,divider-clock";
1948 clocks = <&mmc4_gfclk_mux>;
1949 ti,bit-shift = <25>;
1952 ti,index-power-of-two;
1955 qspi_gfclk_mux: qspi_gfclk_mux@1838 {
1957 compatible = "ti,mux-clock";
1958 clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>;
1959 ti,bit-shift = <24>;
1963 qspi_gfclk_div: qspi_gfclk_div@1838 {
1965 compatible = "ti,divider-clock";
1966 clocks = <&qspi_gfclk_mux>;
1967 ti,bit-shift = <25>;
1970 ti,index-power-of-two;
1973 timer10_gfclk_mux: timer10_gfclk_mux@1728 {
1975 compatible = "ti,mux-clock";
1976 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1977 ti,bit-shift = <24>;
1981 timer11_gfclk_mux: timer11_gfclk_mux@1730 {
1983 compatible = "ti,mux-clock";
1984 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1985 ti,bit-shift = <24>;
1989 timer13_gfclk_mux: timer13_gfclk_mux@17c8 {
1991 compatible = "ti,mux-clock";
1992 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1993 ti,bit-shift = <24>;
1997 timer14_gfclk_mux: timer14_gfclk_mux@17d0 {
1999 compatible = "ti,mux-clock";
2000 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2001 ti,bit-shift = <24>;
2005 timer15_gfclk_mux: timer15_gfclk_mux@17d8 {
2007 compatible = "ti,mux-clock";
2008 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2009 ti,bit-shift = <24>;
2013 timer16_gfclk_mux: timer16_gfclk_mux@1830 {
2015 compatible = "ti,mux-clock";
2016 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2017 ti,bit-shift = <24>;
2021 timer2_gfclk_mux: timer2_gfclk_mux@1738 {
2023 compatible = "ti,mux-clock";
2024 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2025 ti,bit-shift = <24>;
2029 timer3_gfclk_mux: timer3_gfclk_mux@1740 {
2031 compatible = "ti,mux-clock";
2032 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2033 ti,bit-shift = <24>;
2037 timer4_gfclk_mux: timer4_gfclk_mux@1748 {
2039 compatible = "ti,mux-clock";
2040 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2041 ti,bit-shift = <24>;
2045 timer9_gfclk_mux: timer9_gfclk_mux@1750 {
2047 compatible = "ti,mux-clock";
2048 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2049 ti,bit-shift = <24>;
2053 uart1_gfclk_mux: uart1_gfclk_mux@1840 {
2055 compatible = "ti,mux-clock";
2056 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2057 ti,bit-shift = <24>;
2061 uart2_gfclk_mux: uart2_gfclk_mux@1848 {
2063 compatible = "ti,mux-clock";
2064 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2065 ti,bit-shift = <24>;
2069 uart3_gfclk_mux: uart3_gfclk_mux@1850 {
2071 compatible = "ti,mux-clock";
2072 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2073 ti,bit-shift = <24>;
2077 uart4_gfclk_mux: uart4_gfclk_mux@1858 {
2079 compatible = "ti,mux-clock";
2080 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2081 ti,bit-shift = <24>;
2085 uart5_gfclk_mux: uart5_gfclk_mux@1870 {
2087 compatible = "ti,mux-clock";
2088 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2089 ti,bit-shift = <24>;
2093 uart7_gfclk_mux: uart7_gfclk_mux@18d0 {
2095 compatible = "ti,mux-clock";
2096 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2097 ti,bit-shift = <24>;
2101 uart8_gfclk_mux: uart8_gfclk_mux@18e0 {
2103 compatible = "ti,mux-clock";
2104 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2105 ti,bit-shift = <24>;
2109 uart9_gfclk_mux: uart9_gfclk_mux@18e8 {
2111 compatible = "ti,mux-clock";
2112 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2113 ti,bit-shift = <24>;
2117 vip1_gclk_mux: vip1_gclk_mux@1020 {
2119 compatible = "ti,mux-clock";
2120 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
2121 ti,bit-shift = <24>;
2125 vip2_gclk_mux: vip2_gclk_mux@1028 {
2127 compatible = "ti,mux-clock";
2128 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
2129 ti,bit-shift = <24>;
2133 vip3_gclk_mux: vip3_gclk_mux@1030 {
2135 compatible = "ti,mux-clock";
2136 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
2137 ti,bit-shift = <24>;
2142 &cm_core_clockdomains {
2143 coreaon_clkdm: coreaon_clkdm {
2144 compatible = "ti,clockdomain";
2145 clocks = <&dpll_usb_ck>;
2150 dss_deshdcp_clk: dss_deshdcp_clk@558 {
2152 compatible = "ti,gate-clock";
2153 clocks = <&l3_iclk_div>;
2158 ehrpwm0_tbclk: ehrpwm0_tbclk@558 {
2160 compatible = "ti,gate-clock";
2161 clocks = <&l4_root_clk_div>;
2162 ti,bit-shift = <20>;
2166 ehrpwm1_tbclk: ehrpwm1_tbclk@558 {
2168 compatible = "ti,gate-clock";
2169 clocks = <&l4_root_clk_div>;
2170 ti,bit-shift = <21>;
2174 ehrpwm2_tbclk: ehrpwm2_tbclk@558 {
2176 compatible = "ti,gate-clock";
2177 clocks = <&l4_root_clk_div>;
2178 ti,bit-shift = <22>;
2182 sys_32k_ck: sys_32k_ck {
2184 compatible = "ti,mux-clock";
2185 clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>;