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ARM: dts: Update video-phy node with syscon phandle for exynos3250
[deliverable/linux.git] / arch / arm / boot / dts / exynos3250.dtsi
1 /*
2 * Samsung's Exynos3250 SoC device tree source
3 *
4 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
8 * based board files can include this file and provide values for board specfic
9 * bindings.
10 *
11 * Note: This file does not include device nodes for all the controllers in
12 * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
13 * nodes can be added to this file.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20 #include "skeleton.dtsi"
21 #include "exynos4-cpu-thermal.dtsi"
22 #include <dt-bindings/clock/exynos3250.h>
23
24 / {
25 compatible = "samsung,exynos3250";
26 interrupt-parent = <&gic>;
27
28 aliases {
29 pinctrl0 = &pinctrl_0;
30 pinctrl1 = &pinctrl_1;
31 mshc0 = &mshc_0;
32 mshc1 = &mshc_1;
33 spi0 = &spi_0;
34 spi1 = &spi_1;
35 i2c0 = &i2c_0;
36 i2c1 = &i2c_1;
37 i2c2 = &i2c_2;
38 i2c3 = &i2c_3;
39 i2c4 = &i2c_4;
40 i2c5 = &i2c_5;
41 i2c6 = &i2c_6;
42 i2c7 = &i2c_7;
43 serial0 = &serial_0;
44 serial1 = &serial_1;
45 };
46
47 cpus {
48 #address-cells = <1>;
49 #size-cells = <0>;
50
51 cpu0: cpu@0 {
52 device_type = "cpu";
53 compatible = "arm,cortex-a7";
54 reg = <0>;
55 clock-frequency = <1000000000>;
56 };
57
58 cpu1: cpu@1 {
59 device_type = "cpu";
60 compatible = "arm,cortex-a7";
61 reg = <1>;
62 clock-frequency = <1000000000>;
63 };
64 };
65
66 soc: soc {
67 compatible = "simple-bus";
68 #address-cells = <1>;
69 #size-cells = <1>;
70 ranges;
71
72 fixed-rate-clocks {
73 #address-cells = <1>;
74 #size-cells = <0>;
75
76 xusbxti: clock@0 {
77 compatible = "fixed-clock";
78 #address-cells = <1>;
79 #size-cells = <0>;
80 reg = <0>;
81 clock-frequency = <0>;
82 #clock-cells = <0>;
83 clock-output-names = "xusbxti";
84 };
85
86 xxti: clock@1 {
87 compatible = "fixed-clock";
88 reg = <1>;
89 clock-frequency = <0>;
90 #clock-cells = <0>;
91 clock-output-names = "xxti";
92 };
93
94 xtcxo: clock@2 {
95 compatible = "fixed-clock";
96 reg = <2>;
97 clock-frequency = <0>;
98 #clock-cells = <0>;
99 clock-output-names = "xtcxo";
100 };
101 };
102
103 sysram@02020000 {
104 compatible = "mmio-sram";
105 reg = <0x02020000 0x40000>;
106 #address-cells = <1>;
107 #size-cells = <1>;
108 ranges = <0 0x02020000 0x40000>;
109
110 smp-sysram@0 {
111 compatible = "samsung,exynos4210-sysram";
112 reg = <0x0 0x1000>;
113 };
114
115 smp-sysram@3f000 {
116 compatible = "samsung,exynos4210-sysram-ns";
117 reg = <0x3f000 0x1000>;
118 };
119 };
120
121 chipid@10000000 {
122 compatible = "samsung,exynos4210-chipid";
123 reg = <0x10000000 0x100>;
124 };
125
126 sys_reg: syscon@10010000 {
127 compatible = "samsung,exynos3-sysreg", "syscon";
128 reg = <0x10010000 0x400>;
129 };
130
131 pmu_system_controller: system-controller@10020000 {
132 compatible = "samsung,exynos3250-pmu", "syscon";
133 reg = <0x10020000 0x4000>;
134 interrupt-controller;
135 #interrupt-cells = <3>;
136 interrupt-parent = <&gic>;
137 };
138
139 mipi_phy: video-phy@10020710 {
140 compatible = "samsung,s5pv210-mipi-video-phy";
141 #phy-cells = <1>;
142 syscon = <&pmu_system_controller>;
143 };
144
145 pd_cam: cam-power-domain@10023C00 {
146 compatible = "samsung,exynos4210-pd";
147 reg = <0x10023C00 0x20>;
148 #power-domain-cells = <0>;
149 };
150
151 pd_mfc: mfc-power-domain@10023C40 {
152 compatible = "samsung,exynos4210-pd";
153 reg = <0x10023C40 0x20>;
154 #power-domain-cells = <0>;
155 };
156
157 pd_g3d: g3d-power-domain@10023C60 {
158 compatible = "samsung,exynos4210-pd";
159 reg = <0x10023C60 0x20>;
160 #power-domain-cells = <0>;
161 };
162
163 pd_lcd0: lcd0-power-domain@10023C80 {
164 compatible = "samsung,exynos4210-pd";
165 reg = <0x10023C80 0x20>;
166 #power-domain-cells = <0>;
167 };
168
169 pd_isp: isp-power-domain@10023CA0 {
170 compatible = "samsung,exynos4210-pd";
171 reg = <0x10023CA0 0x20>;
172 #power-domain-cells = <0>;
173 };
174
175 cmu: clock-controller@10030000 {
176 compatible = "samsung,exynos3250-cmu";
177 reg = <0x10030000 0x20000>;
178 #clock-cells = <1>;
179 assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
180 <&cmu CLK_MOUT_ACLK_266_SUB>;
181 assigned-clock-parents = <&cmu CLK_FIN_PLL>,
182 <&cmu CLK_FIN_PLL>;
183 };
184
185 cmu_dmc: clock-controller@105C0000 {
186 compatible = "samsung,exynos3250-cmu-dmc";
187 reg = <0x105C0000 0x2000>;
188 #clock-cells = <1>;
189 };
190
191 rtc: rtc@10070000 {
192 compatible = "samsung,s3c6410-rtc";
193 reg = <0x10070000 0x100>;
194 interrupts = <0 73 0>, <0 74 0>;
195 interrupt-parent = <&pmu_system_controller>;
196 status = "disabled";
197 };
198
199 tmu: tmu@100C0000 {
200 compatible = "samsung,exynos3250-tmu";
201 reg = <0x100C0000 0x100>;
202 interrupts = <0 216 0>;
203 clocks = <&cmu CLK_TMU_APBIF>;
204 clock-names = "tmu_apbif";
205 #include "exynos4412-tmu-sensor-conf.dtsi"
206 status = "disabled";
207 };
208
209 gic: interrupt-controller@10481000 {
210 compatible = "arm,cortex-a15-gic";
211 #interrupt-cells = <3>;
212 interrupt-controller;
213 reg = <0x10481000 0x1000>,
214 <0x10482000 0x1000>,
215 <0x10484000 0x2000>,
216 <0x10486000 0x2000>;
217 interrupts = <1 9 0xf04>;
218 };
219
220 mct@10050000 {
221 compatible = "samsung,exynos4210-mct";
222 reg = <0x10050000 0x800>;
223 interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
224 <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
225 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
226 clock-names = "fin_pll", "mct";
227 };
228
229 pinctrl_1: pinctrl@11000000 {
230 compatible = "samsung,exynos3250-pinctrl";
231 reg = <0x11000000 0x1000>;
232 interrupts = <0 225 0>;
233
234 wakeup-interrupt-controller {
235 compatible = "samsung,exynos4210-wakeup-eint";
236 interrupts = <0 48 0>;
237 };
238 };
239
240 pinctrl_0: pinctrl@11400000 {
241 compatible = "samsung,exynos3250-pinctrl";
242 reg = <0x11400000 0x1000>;
243 interrupts = <0 240 0>;
244 };
245
246 jpeg: codec@11830000 {
247 compatible = "samsung,exynos3250-jpeg";
248 reg = <0x11830000 0x1000>;
249 interrupts = <0 171 0>;
250 clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>;
251 clock-names = "jpeg", "sclk";
252 power-domains = <&pd_cam>;
253 assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>;
254 assigned-clock-rates = <0>, <150000000>;
255 assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>;
256 iommus = <&sysmmu_jpeg>;
257 status = "disabled";
258 };
259
260 sysmmu_jpeg: sysmmu@11A60000 {
261 compatible = "samsung,exynos-sysmmu";
262 reg = <0x11a60000 0x1000>;
263 interrupts = <0 156 0>, <0 161 0>;
264 clock-names = "sysmmu", "master";
265 clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
266 power-domains = <&pd_cam>;
267 #iommu-cells = <0>;
268 };
269
270 fimd: fimd@11c00000 {
271 compatible = "samsung,exynos3250-fimd";
272 reg = <0x11c00000 0x30000>;
273 interrupt-names = "fifo", "vsync", "lcd_sys";
274 interrupts = <0 84 0>, <0 85 0>, <0 86 0>;
275 clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
276 clock-names = "sclk_fimd", "fimd";
277 power-domains = <&pd_lcd0>;
278 iommus = <&sysmmu_fimd0>;
279 samsung,sysreg = <&sys_reg>;
280 status = "disabled";
281 };
282
283 dsi_0: dsi@11C80000 {
284 compatible = "samsung,exynos3250-mipi-dsi";
285 reg = <0x11C80000 0x10000>;
286 interrupts = <0 83 0>;
287 samsung,phy-type = <0>;
288 power-domains = <&pd_lcd0>;
289 phys = <&mipi_phy 1>;
290 phy-names = "dsim";
291 clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
292 clock-names = "bus_clk", "pll_clk";
293 #address-cells = <1>;
294 #size-cells = <0>;
295 status = "disabled";
296 };
297
298 sysmmu_fimd0: sysmmu@11E20000 {
299 compatible = "samsung,exynos-sysmmu";
300 reg = <0x11e20000 0x1000>;
301 interrupts = <0 80 0>, <0 81 0>;
302 clock-names = "sysmmu", "master";
303 clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
304 power-domains = <&pd_lcd0>;
305 #iommu-cells = <0>;
306 };
307
308 hsotg: hsotg@12480000 {
309 compatible = "snps,dwc2";
310 reg = <0x12480000 0x20000>;
311 interrupts = <0 141 0>;
312 clocks = <&cmu CLK_USBOTG>;
313 clock-names = "otg";
314 phys = <&exynos_usbphy 0>;
315 phy-names = "usb2-phy";
316 status = "disabled";
317 };
318
319 mshc_0: mshc@12510000 {
320 compatible = "samsung,exynos5250-dw-mshc";
321 reg = <0x12510000 0x1000>;
322 interrupts = <0 142 0>;
323 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
324 clock-names = "biu", "ciu";
325 fifo-depth = <0x80>;
326 #address-cells = <1>;
327 #size-cells = <0>;
328 status = "disabled";
329 };
330
331 mshc_1: mshc@12520000 {
332 compatible = "samsung,exynos5250-dw-mshc";
333 reg = <0x12520000 0x1000>;
334 interrupts = <0 143 0>;
335 clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
336 clock-names = "biu", "ciu";
337 fifo-depth = <0x80>;
338 #address-cells = <1>;
339 #size-cells = <0>;
340 status = "disabled";
341 };
342
343 exynos_usbphy: exynos-usbphy@125B0000 {
344 compatible = "samsung,exynos3250-usb2-phy";
345 reg = <0x125B0000 0x100>;
346 samsung,pmureg-phandle = <&pmu_system_controller>;
347 clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>;
348 clock-names = "phy", "ref";
349 #phy-cells = <1>;
350 status = "disabled";
351 };
352
353 amba {
354 compatible = "arm,amba-bus";
355 #address-cells = <1>;
356 #size-cells = <1>;
357 ranges;
358
359 pdma0: pdma@12680000 {
360 compatible = "arm,pl330", "arm,primecell";
361 reg = <0x12680000 0x1000>;
362 interrupts = <0 138 0>;
363 clocks = <&cmu CLK_PDMA0>;
364 clock-names = "apb_pclk";
365 #dma-cells = <1>;
366 #dma-channels = <8>;
367 #dma-requests = <32>;
368 };
369
370 pdma1: pdma@12690000 {
371 compatible = "arm,pl330", "arm,primecell";
372 reg = <0x12690000 0x1000>;
373 interrupts = <0 139 0>;
374 clocks = <&cmu CLK_PDMA1>;
375 clock-names = "apb_pclk";
376 #dma-cells = <1>;
377 #dma-channels = <8>;
378 #dma-requests = <32>;
379 };
380 };
381
382 adc: adc@126C0000 {
383 compatible = "samsung,exynos3250-adc",
384 "samsung,exynos-adc-v2";
385 reg = <0x126C0000 0x100>;
386 interrupts = <0 137 0>;
387 clock-names = "adc", "sclk";
388 clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
389 #io-channel-cells = <1>;
390 io-channel-ranges;
391 samsung,syscon-phandle = <&pmu_system_controller>;
392 status = "disabled";
393 };
394
395 mfc: codec@13400000 {
396 compatible = "samsung,mfc-v7";
397 reg = <0x13400000 0x10000>;
398 interrupts = <0 102 0>;
399 clock-names = "mfc", "sclk_mfc";
400 clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
401 power-domains = <&pd_mfc>;
402 iommus = <&sysmmu_mfc>;
403 status = "disabled";
404 };
405
406 sysmmu_mfc: sysmmu@13620000 {
407 compatible = "samsung,exynos-sysmmu";
408 reg = <0x13620000 0x1000>;
409 interrupts = <0 96 0>, <0 98 0>;
410 clock-names = "sysmmu", "master";
411 clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;
412 power-domains = <&pd_mfc>;
413 #iommu-cells = <0>;
414 };
415
416 serial_0: serial@13800000 {
417 compatible = "samsung,exynos4210-uart";
418 reg = <0x13800000 0x100>;
419 interrupts = <0 109 0>;
420 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
421 clock-names = "uart", "clk_uart_baud0";
422 pinctrl-names = "default";
423 pinctrl-0 = <&uart0_data &uart0_fctl>;
424 status = "disabled";
425 };
426
427 serial_1: serial@13810000 {
428 compatible = "samsung,exynos4210-uart";
429 reg = <0x13810000 0x100>;
430 interrupts = <0 110 0>;
431 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
432 clock-names = "uart", "clk_uart_baud0";
433 pinctrl-names = "default";
434 pinctrl-0 = <&uart1_data>;
435 status = "disabled";
436 };
437
438 i2c_0: i2c@13860000 {
439 #address-cells = <1>;
440 #size-cells = <0>;
441 compatible = "samsung,s3c2440-i2c";
442 reg = <0x13860000 0x100>;
443 interrupts = <0 113 0>;
444 clocks = <&cmu CLK_I2C0>;
445 clock-names = "i2c";
446 pinctrl-names = "default";
447 pinctrl-0 = <&i2c0_bus>;
448 status = "disabled";
449 };
450
451 i2c_1: i2c@13870000 {
452 #address-cells = <1>;
453 #size-cells = <0>;
454 compatible = "samsung,s3c2440-i2c";
455 reg = <0x13870000 0x100>;
456 interrupts = <0 114 0>;
457 clocks = <&cmu CLK_I2C1>;
458 clock-names = "i2c";
459 pinctrl-names = "default";
460 pinctrl-0 = <&i2c1_bus>;
461 status = "disabled";
462 };
463
464 i2c_2: i2c@13880000 {
465 #address-cells = <1>;
466 #size-cells = <0>;
467 compatible = "samsung,s3c2440-i2c";
468 reg = <0x13880000 0x100>;
469 interrupts = <0 115 0>;
470 clocks = <&cmu CLK_I2C2>;
471 clock-names = "i2c";
472 pinctrl-names = "default";
473 pinctrl-0 = <&i2c2_bus>;
474 status = "disabled";
475 };
476
477 i2c_3: i2c@13890000 {
478 #address-cells = <1>;
479 #size-cells = <0>;
480 compatible = "samsung,s3c2440-i2c";
481 reg = <0x13890000 0x100>;
482 interrupts = <0 116 0>;
483 clocks = <&cmu CLK_I2C3>;
484 clock-names = "i2c";
485 pinctrl-names = "default";
486 pinctrl-0 = <&i2c3_bus>;
487 status = "disabled";
488 };
489
490 i2c_4: i2c@138A0000 {
491 #address-cells = <1>;
492 #size-cells = <0>;
493 compatible = "samsung,s3c2440-i2c";
494 reg = <0x138A0000 0x100>;
495 interrupts = <0 117 0>;
496 clocks = <&cmu CLK_I2C4>;
497 clock-names = "i2c";
498 pinctrl-names = "default";
499 pinctrl-0 = <&i2c4_bus>;
500 status = "disabled";
501 };
502
503 i2c_5: i2c@138B0000 {
504 #address-cells = <1>;
505 #size-cells = <0>;
506 compatible = "samsung,s3c2440-i2c";
507 reg = <0x138B0000 0x100>;
508 interrupts = <0 118 0>;
509 clocks = <&cmu CLK_I2C5>;
510 clock-names = "i2c";
511 pinctrl-names = "default";
512 pinctrl-0 = <&i2c5_bus>;
513 status = "disabled";
514 };
515
516 i2c_6: i2c@138C0000 {
517 #address-cells = <1>;
518 #size-cells = <0>;
519 compatible = "samsung,s3c2440-i2c";
520 reg = <0x138C0000 0x100>;
521 interrupts = <0 119 0>;
522 clocks = <&cmu CLK_I2C6>;
523 clock-names = "i2c";
524 pinctrl-names = "default";
525 pinctrl-0 = <&i2c6_bus>;
526 status = "disabled";
527 };
528
529 i2c_7: i2c@138D0000 {
530 #address-cells = <1>;
531 #size-cells = <0>;
532 compatible = "samsung,s3c2440-i2c";
533 reg = <0x138D0000 0x100>;
534 interrupts = <0 120 0>;
535 clocks = <&cmu CLK_I2C7>;
536 clock-names = "i2c";
537 pinctrl-names = "default";
538 pinctrl-0 = <&i2c7_bus>;
539 status = "disabled";
540 };
541
542 spi_0: spi@13920000 {
543 compatible = "samsung,exynos4210-spi";
544 reg = <0x13920000 0x100>;
545 interrupts = <0 121 0>;
546 dmas = <&pdma0 7>, <&pdma0 6>;
547 dma-names = "tx", "rx";
548 #address-cells = <1>;
549 #size-cells = <0>;
550 clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
551 clock-names = "spi", "spi_busclk0";
552 samsung,spi-src-clk = <0>;
553 pinctrl-names = "default";
554 pinctrl-0 = <&spi0_bus>;
555 status = "disabled";
556 };
557
558 spi_1: spi@13930000 {
559 compatible = "samsung,exynos4210-spi";
560 reg = <0x13930000 0x100>;
561 interrupts = <0 122 0>;
562 dmas = <&pdma1 7>, <&pdma1 6>;
563 dma-names = "tx", "rx";
564 #address-cells = <1>;
565 #size-cells = <0>;
566 clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
567 clock-names = "spi", "spi_busclk0";
568 samsung,spi-src-clk = <0>;
569 pinctrl-names = "default";
570 pinctrl-0 = <&spi1_bus>;
571 status = "disabled";
572 };
573
574 i2s2: i2s@13970000 {
575 compatible = "samsung,s3c6410-i2s";
576 reg = <0x13970000 0x100>;
577 interrupts = <0 126 0>;
578 clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
579 clock-names = "iis", "i2s_opclk0";
580 dmas = <&pdma0 14>, <&pdma0 13>;
581 dma-names = "tx", "rx";
582 pinctrl-0 = <&i2s2_bus>;
583 pinctrl-names = "default";
584 status = "disabled";
585 };
586
587 pwm: pwm@139D0000 {
588 compatible = "samsung,exynos4210-pwm";
589 reg = <0x139D0000 0x1000>;
590 interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
591 <0 107 0>, <0 108 0>;
592 #pwm-cells = <3>;
593 status = "disabled";
594 };
595
596 pmu {
597 compatible = "arm,cortex-a7-pmu";
598 interrupts = <0 18 0>, <0 19 0>;
599 };
600
601 ppmu_dmc0: ppmu_dmc0@106a0000 {
602 compatible = "samsung,exynos-ppmu";
603 reg = <0x106a0000 0x2000>;
604 status = "disabled";
605 };
606
607 ppmu_dmc1: ppmu_dmc1@106b0000 {
608 compatible = "samsung,exynos-ppmu";
609 reg = <0x106b0000 0x2000>;
610 status = "disabled";
611 };
612
613 ppmu_cpu: ppmu_cpu@106c0000 {
614 compatible = "samsung,exynos-ppmu";
615 reg = <0x106c0000 0x2000>;
616 status = "disabled";
617 };
618
619 ppmu_rightbus: ppmu_rightbus@112a0000 {
620 compatible = "samsung,exynos-ppmu";
621 reg = <0x112a0000 0x2000>;
622 clocks = <&cmu CLK_PPMURIGHT>;
623 clock-names = "ppmu";
624 status = "disabled";
625 };
626
627 ppmu_leftbus: ppmu_leftbus0@116a0000 {
628 compatible = "samsung,exynos-ppmu";
629 reg = <0x116a0000 0x2000>;
630 clocks = <&cmu CLK_PPMULEFT>;
631 clock-names = "ppmu";
632 status = "disabled";
633 };
634
635 ppmu_camif: ppmu_camif@11ac0000 {
636 compatible = "samsung,exynos-ppmu";
637 reg = <0x11ac0000 0x2000>;
638 clocks = <&cmu CLK_PPMUCAMIF>;
639 clock-names = "ppmu";
640 status = "disabled";
641 };
642
643 ppmu_lcd0: ppmu_lcd0@11e40000 {
644 compatible = "samsung,exynos-ppmu";
645 reg = <0x11e40000 0x2000>;
646 clocks = <&cmu CLK_PPMULCD0>;
647 clock-names = "ppmu";
648 status = "disabled";
649 };
650
651 ppmu_fsys: ppmu_fsys@12630000 {
652 compatible = "samsung,exynos-ppmu";
653 reg = <0x12630000 0x2000>;
654 clocks = <&cmu CLK_PPMUFILE>;
655 clock-names = "ppmu";
656 status = "disabled";
657 };
658
659 ppmu_g3d: ppmu_g3d@13220000 {
660 compatible = "samsung,exynos-ppmu";
661 reg = <0x13220000 0x2000>;
662 clocks = <&cmu CLK_PPMUG3D>;
663 clock-names = "ppmu";
664 status = "disabled";
665 };
666
667 ppmu_mfc: ppmu_mfc@13660000 {
668 compatible = "samsung,exynos-ppmu";
669 reg = <0x13660000 0x2000>;
670 clocks = <&cmu CLK_PPMUMFC_L>;
671 clock-names = "ppmu";
672 status = "disabled";
673 };
674 };
675 };
676
677 #include "exynos3250-pinctrl.dtsi"
Linux kernel - Deliverables
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