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ARM: dts: Add TMU dt node to monitor the temperature for exynos3250
[deliverable/linux.git] / arch / arm / boot / dts / exynos3250.dtsi
1 /*
2 * Samsung's Exynos3250 SoC device tree source
3 *
4 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
8 * based board files can include this file and provide values for board specfic
9 * bindings.
10 *
11 * Note: This file does not include device nodes for all the controllers in
12 * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
13 * nodes can be added to this file.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20 #include "skeleton.dtsi"
21 #include <dt-bindings/clock/exynos3250.h>
22
23 / {
24 compatible = "samsung,exynos3250";
25 interrupt-parent = <&gic>;
26
27 aliases {
28 pinctrl0 = &pinctrl_0;
29 pinctrl1 = &pinctrl_1;
30 mshc0 = &mshc_0;
31 mshc1 = &mshc_1;
32 spi0 = &spi_0;
33 spi1 = &spi_1;
34 i2c0 = &i2c_0;
35 i2c1 = &i2c_1;
36 i2c2 = &i2c_2;
37 i2c3 = &i2c_3;
38 i2c4 = &i2c_4;
39 i2c5 = &i2c_5;
40 i2c6 = &i2c_6;
41 i2c7 = &i2c_7;
42 };
43
44 cpus {
45 #address-cells = <1>;
46 #size-cells = <0>;
47
48 cpu0: cpu@0 {
49 device_type = "cpu";
50 compatible = "arm,cortex-a7";
51 reg = <0>;
52 clock-frequency = <1000000000>;
53 };
54
55 cpu1: cpu@1 {
56 device_type = "cpu";
57 compatible = "arm,cortex-a7";
58 reg = <1>;
59 clock-frequency = <1000000000>;
60 };
61 };
62
63 soc: soc {
64 compatible = "simple-bus";
65 #address-cells = <1>;
66 #size-cells = <1>;
67 ranges;
68
69 fixed-rate-clocks {
70 #address-cells = <1>;
71 #size-cells = <0>;
72
73 xusbxti: clock@0 {
74 compatible = "fixed-clock";
75 #address-cells = <1>;
76 #size-cells = <0>;
77 reg = <0>;
78 clock-frequency = <0>;
79 #clock-cells = <0>;
80 clock-output-names = "xusbxti";
81 };
82
83 xxti: clock@1 {
84 compatible = "fixed-clock";
85 reg = <1>;
86 clock-frequency = <0>;
87 #clock-cells = <0>;
88 clock-output-names = "xxti";
89 };
90
91 xtcxo: clock@2 {
92 compatible = "fixed-clock";
93 reg = <2>;
94 clock-frequency = <0>;
95 #clock-cells = <0>;
96 clock-output-names = "xtcxo";
97 };
98 };
99
100 sysram@02020000 {
101 compatible = "mmio-sram";
102 reg = <0x02020000 0x40000>;
103 #address-cells = <1>;
104 #size-cells = <1>;
105 ranges = <0 0x02020000 0x40000>;
106
107 smp-sysram@0 {
108 compatible = "samsung,exynos4210-sysram";
109 reg = <0x0 0x1000>;
110 };
111
112 smp-sysram@3f000 {
113 compatible = "samsung,exynos4210-sysram-ns";
114 reg = <0x3f000 0x1000>;
115 };
116 };
117
118 chipid@10000000 {
119 compatible = "samsung,exynos4210-chipid";
120 reg = <0x10000000 0x100>;
121 };
122
123 sys_reg: syscon@10010000 {
124 compatible = "samsung,exynos3-sysreg", "syscon";
125 reg = <0x10010000 0x400>;
126 };
127
128 pmu_system_controller: system-controller@10020000 {
129 compatible = "samsung,exynos3250-pmu", "syscon";
130 reg = <0x10020000 0x4000>;
131 };
132
133 pd_cam: cam-power-domain@10023C00 {
134 compatible = "samsung,exynos4210-pd";
135 reg = <0x10023C00 0x20>;
136 };
137
138 pd_mfc: mfc-power-domain@10023C40 {
139 compatible = "samsung,exynos4210-pd";
140 reg = <0x10023C40 0x20>;
141 };
142
143 pd_g3d: g3d-power-domain@10023C60 {
144 compatible = "samsung,exynos4210-pd";
145 reg = <0x10023C60 0x20>;
146 };
147
148 pd_lcd0: lcd0-power-domain@10023C80 {
149 compatible = "samsung,exynos4210-pd";
150 reg = <0x10023C80 0x20>;
151 };
152
153 pd_isp: isp-power-domain@10023CA0 {
154 compatible = "samsung,exynos4210-pd";
155 reg = <0x10023CA0 0x20>;
156 };
157
158 cmu: clock-controller@10030000 {
159 compatible = "samsung,exynos3250-cmu";
160 reg = <0x10030000 0x20000>;
161 #clock-cells = <1>;
162 };
163
164 rtc: rtc@10070000 {
165 compatible = "samsung,s3c6410-rtc";
166 reg = <0x10070000 0x100>;
167 interrupts = <0 73 0>, <0 74 0>;
168 status = "disabled";
169 };
170
171 tmu: tmu@100C0000 {
172 compatible = "samsung,exynos3250-tmu";
173 reg = <0x100C0000 0x100>;
174 interrupts = <0 216 0>;
175 clocks = <&cmu CLK_TMU_APBIF>;
176 clock-names = "tmu_apbif";
177 status = "disabled";
178 };
179
180 gic: interrupt-controller@10481000 {
181 compatible = "arm,cortex-a15-gic";
182 #interrupt-cells = <3>;
183 interrupt-controller;
184 reg = <0x10481000 0x1000>,
185 <0x10482000 0x1000>,
186 <0x10484000 0x2000>,
187 <0x10486000 0x2000>;
188 interrupts = <1 9 0xf04>;
189 };
190
191 mct@10050000 {
192 compatible = "samsung,exynos4210-mct";
193 reg = <0x10050000 0x800>;
194 interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
195 <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
196 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
197 clock-names = "fin_pll", "mct";
198 };
199
200 pinctrl_1: pinctrl@11000000 {
201 compatible = "samsung,exynos3250-pinctrl";
202 reg = <0x11000000 0x1000>;
203 interrupts = <0 225 0>;
204
205 wakeup-interrupt-controller {
206 compatible = "samsung,exynos4210-wakeup-eint";
207 interrupt-parent = <&gic>;
208 interrupts = <0 48 0>;
209 };
210 };
211
212 pinctrl_0: pinctrl@11400000 {
213 compatible = "samsung,exynos3250-pinctrl";
214 reg = <0x11400000 0x1000>;
215 interrupts = <0 240 0>;
216 };
217
218 mshc_0: mshc@12510000 {
219 compatible = "samsung,exynos5250-dw-mshc";
220 reg = <0x12510000 0x1000>;
221 interrupts = <0 142 0>;
222 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
223 clock-names = "biu", "ciu";
224 fifo-depth = <0x80>;
225 #address-cells = <1>;
226 #size-cells = <0>;
227 status = "disabled";
228 };
229
230 mshc_1: mshc@12520000 {
231 compatible = "samsung,exynos5250-dw-mshc";
232 reg = <0x12520000 0x1000>;
233 interrupts = <0 143 0>;
234 clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
235 clock-names = "biu", "ciu";
236 fifo-depth = <0x80>;
237 #address-cells = <1>;
238 #size-cells = <0>;
239 status = "disabled";
240 };
241
242 amba {
243 compatible = "arm,amba-bus";
244 #address-cells = <1>;
245 #size-cells = <1>;
246 interrupt-parent = <&gic>;
247 ranges;
248
249 pdma0: pdma@12680000 {
250 compatible = "arm,pl330", "arm,primecell";
251 reg = <0x12680000 0x1000>;
252 interrupts = <0 138 0>;
253 clocks = <&cmu CLK_PDMA0>;
254 clock-names = "apb_pclk";
255 #dma-cells = <1>;
256 #dma-channels = <8>;
257 #dma-requests = <32>;
258 };
259
260 pdma1: pdma@12690000 {
261 compatible = "arm,pl330", "arm,primecell";
262 reg = <0x12690000 0x1000>;
263 interrupts = <0 139 0>;
264 clocks = <&cmu CLK_PDMA1>;
265 clock-names = "apb_pclk";
266 #dma-cells = <1>;
267 #dma-channels = <8>;
268 #dma-requests = <32>;
269 };
270 };
271
272 adc: adc@126C0000 {
273 compatible = "samsung,exynos-adc-v3";
274 reg = <0x126C0000 0x100>, <0x10020718 0x4>;
275 interrupts = <0 137 0>;
276 clock-names = "adc", "sclk_tsadc";
277 clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
278 #io-channel-cells = <1>;
279 io-channel-ranges;
280 status = "disabled";
281 };
282
283 serial_0: serial@13800000 {
284 compatible = "samsung,exynos4210-uart";
285 reg = <0x13800000 0x100>;
286 interrupts = <0 109 0>;
287 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
288 clock-names = "uart", "clk_uart_baud0";
289 status = "disabled";
290 };
291
292 serial_1: serial@13810000 {
293 compatible = "samsung,exynos4210-uart";
294 reg = <0x13810000 0x100>;
295 interrupts = <0 110 0>;
296 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
297 clock-names = "uart", "clk_uart_baud0";
298 status = "disabled";
299 };
300
301 i2c_0: i2c@13860000 {
302 #address-cells = <1>;
303 #size-cells = <0>;
304 compatible = "samsung,s3c2440-i2c";
305 reg = <0x13860000 0x100>;
306 interrupts = <0 113 0>;
307 clocks = <&cmu CLK_I2C0>;
308 clock-names = "i2c";
309 pinctrl-names = "default";
310 pinctrl-0 = <&i2c0_bus>;
311 status = "disabled";
312 };
313
314 i2c_1: i2c@13870000 {
315 #address-cells = <1>;
316 #size-cells = <0>;
317 compatible = "samsung,s3c2440-i2c";
318 reg = <0x13870000 0x100>;
319 interrupts = <0 114 0>;
320 clocks = <&cmu CLK_I2C1>;
321 clock-names = "i2c";
322 pinctrl-names = "default";
323 pinctrl-0 = <&i2c1_bus>;
324 status = "disabled";
325 };
326
327 i2c_2: i2c@13880000 {
328 #address-cells = <1>;
329 #size-cells = <0>;
330 compatible = "samsung,s3c2440-i2c";
331 reg = <0x13880000 0x100>;
332 interrupts = <0 115 0>;
333 clocks = <&cmu CLK_I2C2>;
334 clock-names = "i2c";
335 pinctrl-names = "default";
336 pinctrl-0 = <&i2c2_bus>;
337 status = "disabled";
338 };
339
340 i2c_3: i2c@13890000 {
341 #address-cells = <1>;
342 #size-cells = <0>;
343 compatible = "samsung,s3c2440-i2c";
344 reg = <0x13890000 0x100>;
345 interrupts = <0 116 0>;
346 clocks = <&cmu CLK_I2C3>;
347 clock-names = "i2c";
348 pinctrl-names = "default";
349 pinctrl-0 = <&i2c3_bus>;
350 status = "disabled";
351 };
352
353 i2c_4: i2c@138A0000 {
354 #address-cells = <1>;
355 #size-cells = <0>;
356 compatible = "samsung,s3c2440-i2c";
357 reg = <0x138A0000 0x100>;
358 interrupts = <0 117 0>;
359 clocks = <&cmu CLK_I2C4>;
360 clock-names = "i2c";
361 pinctrl-names = "default";
362 pinctrl-0 = <&i2c4_bus>;
363 status = "disabled";
364 };
365
366 i2c_5: i2c@138B0000 {
367 #address-cells = <1>;
368 #size-cells = <0>;
369 compatible = "samsung,s3c2440-i2c";
370 reg = <0x138B0000 0x100>;
371 interrupts = <0 118 0>;
372 clocks = <&cmu CLK_I2C5>;
373 clock-names = "i2c";
374 pinctrl-names = "default";
375 pinctrl-0 = <&i2c5_bus>;
376 status = "disabled";
377 };
378
379 i2c_6: i2c@138C0000 {
380 #address-cells = <1>;
381 #size-cells = <0>;
382 compatible = "samsung,s3c2440-i2c";
383 reg = <0x138C0000 0x100>;
384 interrupts = <0 119 0>;
385 clocks = <&cmu CLK_I2C6>;
386 clock-names = "i2c";
387 pinctrl-names = "default";
388 pinctrl-0 = <&i2c6_bus>;
389 status = "disabled";
390 };
391
392 i2c_7: i2c@138D0000 {
393 #address-cells = <1>;
394 #size-cells = <0>;
395 compatible = "samsung,s3c2440-i2c";
396 reg = <0x138D0000 0x100>;
397 interrupts = <0 120 0>;
398 clocks = <&cmu CLK_I2C7>;
399 clock-names = "i2c";
400 pinctrl-names = "default";
401 pinctrl-0 = <&i2c7_bus>;
402 status = "disabled";
403 };
404
405 spi_0: spi@13920000 {
406 compatible = "samsung,exynos4210-spi";
407 reg = <0x13920000 0x100>;
408 interrupts = <0 121 0>;
409 dmas = <&pdma0 7>, <&pdma0 6>;
410 dma-names = "tx", "rx";
411 #address-cells = <1>;
412 #size-cells = <0>;
413 clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
414 clock-names = "spi", "spi_busclk0";
415 samsung,spi-src-clk = <0>;
416 pinctrl-names = "default";
417 pinctrl-0 = <&spi0_bus>;
418 status = "disabled";
419 };
420
421 spi_1: spi@13930000 {
422 compatible = "samsung,exynos4210-spi";
423 reg = <0x13930000 0x100>;
424 interrupts = <0 122 0>;
425 dmas = <&pdma1 7>, <&pdma1 6>;
426 dma-names = "tx", "rx";
427 #address-cells = <1>;
428 #size-cells = <0>;
429 clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
430 clock-names = "spi", "spi_busclk0";
431 samsung,spi-src-clk = <0>;
432 pinctrl-names = "default";
433 pinctrl-0 = <&spi1_bus>;
434 status = "disabled";
435 };
436
437 i2s2: i2s@13970000 {
438 compatible = "samsung,s3c6410-i2s";
439 reg = <0x13970000 0x100>;
440 interrupts = <0 126 0>;
441 clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
442 clock-names = "iis", "i2s_opclk0";
443 dmas = <&pdma0 14>, <&pdma0 13>;
444 dma-names = "tx", "rx";
445 pinctrl-0 = <&i2s2_bus>;
446 pinctrl-names = "default";
447 status = "disabled";
448 };
449
450 pwm: pwm@139D0000 {
451 compatible = "samsung,exynos4210-pwm";
452 reg = <0x139D0000 0x1000>;
453 interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
454 <0 107 0>, <0 108 0>;
455 #pwm-cells = <3>;
456 status = "disabled";
457 };
458
459 pmu {
460 compatible = "arm,cortex-a7-pmu";
461 interrupts = <0 18 0>, <0 19 0>;
462 };
463 };
464 };
465
466 #include "exynos3250-pinctrl.dtsi"
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