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ARM: dts: Remove duplicate 'interrput-parent' property for exynos3250
[deliverable/linux.git] / arch / arm / boot / dts / exynos3250.dtsi
1 /*
2 * Samsung's Exynos3250 SoC device tree source
3 *
4 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
8 * based board files can include this file and provide values for board specfic
9 * bindings.
10 *
11 * Note: This file does not include device nodes for all the controllers in
12 * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
13 * nodes can be added to this file.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20 #include "skeleton.dtsi"
21 #include <dt-bindings/clock/exynos3250.h>
22
23 / {
24 compatible = "samsung,exynos3250";
25 interrupt-parent = <&gic>;
26
27 aliases {
28 pinctrl0 = &pinctrl_0;
29 pinctrl1 = &pinctrl_1;
30 mshc0 = &mshc_0;
31 mshc1 = &mshc_1;
32 spi0 = &spi_0;
33 spi1 = &spi_1;
34 i2c0 = &i2c_0;
35 i2c1 = &i2c_1;
36 i2c2 = &i2c_2;
37 i2c3 = &i2c_3;
38 i2c4 = &i2c_4;
39 i2c5 = &i2c_5;
40 i2c6 = &i2c_6;
41 i2c7 = &i2c_7;
42 };
43
44 cpus {
45 #address-cells = <1>;
46 #size-cells = <0>;
47
48 cpu0: cpu@0 {
49 device_type = "cpu";
50 compatible = "arm,cortex-a7";
51 reg = <0>;
52 clock-frequency = <1000000000>;
53 };
54
55 cpu1: cpu@1 {
56 device_type = "cpu";
57 compatible = "arm,cortex-a7";
58 reg = <1>;
59 clock-frequency = <1000000000>;
60 };
61 };
62
63 soc: soc {
64 compatible = "simple-bus";
65 #address-cells = <1>;
66 #size-cells = <1>;
67 ranges;
68
69 fixed-rate-clocks {
70 #address-cells = <1>;
71 #size-cells = <0>;
72
73 xusbxti: clock@0 {
74 compatible = "fixed-clock";
75 #address-cells = <1>;
76 #size-cells = <0>;
77 reg = <0>;
78 clock-frequency = <0>;
79 #clock-cells = <0>;
80 clock-output-names = "xusbxti";
81 };
82
83 xxti: clock@1 {
84 compatible = "fixed-clock";
85 reg = <1>;
86 clock-frequency = <0>;
87 #clock-cells = <0>;
88 clock-output-names = "xxti";
89 };
90
91 xtcxo: clock@2 {
92 compatible = "fixed-clock";
93 reg = <2>;
94 clock-frequency = <0>;
95 #clock-cells = <0>;
96 clock-output-names = "xtcxo";
97 };
98 };
99
100 sysram@02020000 {
101 compatible = "mmio-sram";
102 reg = <0x02020000 0x40000>;
103 #address-cells = <1>;
104 #size-cells = <1>;
105 ranges = <0 0x02020000 0x40000>;
106
107 smp-sysram@0 {
108 compatible = "samsung,exynos4210-sysram";
109 reg = <0x0 0x1000>;
110 };
111
112 smp-sysram@3f000 {
113 compatible = "samsung,exynos4210-sysram-ns";
114 reg = <0x3f000 0x1000>;
115 };
116 };
117
118 chipid@10000000 {
119 compatible = "samsung,exynos4210-chipid";
120 reg = <0x10000000 0x100>;
121 };
122
123 sys_reg: syscon@10010000 {
124 compatible = "samsung,exynos3-sysreg", "syscon";
125 reg = <0x10010000 0x400>;
126 };
127
128 pmu_system_controller: system-controller@10020000 {
129 compatible = "samsung,exynos3250-pmu", "syscon";
130 reg = <0x10020000 0x4000>;
131 };
132
133 pd_cam: cam-power-domain@10023C00 {
134 compatible = "samsung,exynos4210-pd";
135 reg = <0x10023C00 0x20>;
136 };
137
138 pd_mfc: mfc-power-domain@10023C40 {
139 compatible = "samsung,exynos4210-pd";
140 reg = <0x10023C40 0x20>;
141 };
142
143 pd_g3d: g3d-power-domain@10023C60 {
144 compatible = "samsung,exynos4210-pd";
145 reg = <0x10023C60 0x20>;
146 };
147
148 pd_lcd0: lcd0-power-domain@10023C80 {
149 compatible = "samsung,exynos4210-pd";
150 reg = <0x10023C80 0x20>;
151 };
152
153 pd_isp: isp-power-domain@10023CA0 {
154 compatible = "samsung,exynos4210-pd";
155 reg = <0x10023CA0 0x20>;
156 };
157
158 cmu: clock-controller@10030000 {
159 compatible = "samsung,exynos3250-cmu";
160 reg = <0x10030000 0x20000>;
161 #clock-cells = <1>;
162 };
163
164 rtc: rtc@10070000 {
165 compatible = "samsung,s3c6410-rtc";
166 reg = <0x10070000 0x100>;
167 interrupts = <0 73 0>, <0 74 0>;
168 status = "disabled";
169 };
170
171 tmu: tmu@100C0000 {
172 compatible = "samsung,exynos3250-tmu";
173 reg = <0x100C0000 0x100>;
174 interrupts = <0 216 0>;
175 clocks = <&cmu CLK_TMU_APBIF>;
176 clock-names = "tmu_apbif";
177 status = "disabled";
178 };
179
180 gic: interrupt-controller@10481000 {
181 compatible = "arm,cortex-a15-gic";
182 #interrupt-cells = <3>;
183 interrupt-controller;
184 reg = <0x10481000 0x1000>,
185 <0x10482000 0x1000>,
186 <0x10484000 0x2000>,
187 <0x10486000 0x2000>;
188 interrupts = <1 9 0xf04>;
189 };
190
191 mct@10050000 {
192 compatible = "samsung,exynos4210-mct";
193 reg = <0x10050000 0x800>;
194 interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
195 <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
196 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
197 clock-names = "fin_pll", "mct";
198 };
199
200 pinctrl_1: pinctrl@11000000 {
201 compatible = "samsung,exynos3250-pinctrl";
202 reg = <0x11000000 0x1000>;
203 interrupts = <0 225 0>;
204
205 wakeup-interrupt-controller {
206 compatible = "samsung,exynos4210-wakeup-eint";
207 interrupts = <0 48 0>;
208 };
209 };
210
211 pinctrl_0: pinctrl@11400000 {
212 compatible = "samsung,exynos3250-pinctrl";
213 reg = <0x11400000 0x1000>;
214 interrupts = <0 240 0>;
215 };
216
217 mshc_0: mshc@12510000 {
218 compatible = "samsung,exynos5250-dw-mshc";
219 reg = <0x12510000 0x1000>;
220 interrupts = <0 142 0>;
221 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
222 clock-names = "biu", "ciu";
223 fifo-depth = <0x80>;
224 #address-cells = <1>;
225 #size-cells = <0>;
226 status = "disabled";
227 };
228
229 mshc_1: mshc@12520000 {
230 compatible = "samsung,exynos5250-dw-mshc";
231 reg = <0x12520000 0x1000>;
232 interrupts = <0 143 0>;
233 clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
234 clock-names = "biu", "ciu";
235 fifo-depth = <0x80>;
236 #address-cells = <1>;
237 #size-cells = <0>;
238 status = "disabled";
239 };
240
241 amba {
242 compatible = "arm,amba-bus";
243 #address-cells = <1>;
244 #size-cells = <1>;
245 ranges;
246
247 pdma0: pdma@12680000 {
248 compatible = "arm,pl330", "arm,primecell";
249 reg = <0x12680000 0x1000>;
250 interrupts = <0 138 0>;
251 clocks = <&cmu CLK_PDMA0>;
252 clock-names = "apb_pclk";
253 #dma-cells = <1>;
254 #dma-channels = <8>;
255 #dma-requests = <32>;
256 };
257
258 pdma1: pdma@12690000 {
259 compatible = "arm,pl330", "arm,primecell";
260 reg = <0x12690000 0x1000>;
261 interrupts = <0 139 0>;
262 clocks = <&cmu CLK_PDMA1>;
263 clock-names = "apb_pclk";
264 #dma-cells = <1>;
265 #dma-channels = <8>;
266 #dma-requests = <32>;
267 };
268 };
269
270 adc: adc@126C0000 {
271 compatible = "samsung,exynos-adc-v3";
272 reg = <0x126C0000 0x100>, <0x10020718 0x4>;
273 interrupts = <0 137 0>;
274 clock-names = "adc", "sclk_tsadc";
275 clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
276 #io-channel-cells = <1>;
277 io-channel-ranges;
278 status = "disabled";
279 };
280
281 serial_0: serial@13800000 {
282 compatible = "samsung,exynos4210-uart";
283 reg = <0x13800000 0x100>;
284 interrupts = <0 109 0>;
285 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
286 clock-names = "uart", "clk_uart_baud0";
287 status = "disabled";
288 };
289
290 serial_1: serial@13810000 {
291 compatible = "samsung,exynos4210-uart";
292 reg = <0x13810000 0x100>;
293 interrupts = <0 110 0>;
294 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
295 clock-names = "uart", "clk_uart_baud0";
296 status = "disabled";
297 };
298
299 i2c_0: i2c@13860000 {
300 #address-cells = <1>;
301 #size-cells = <0>;
302 compatible = "samsung,s3c2440-i2c";
303 reg = <0x13860000 0x100>;
304 interrupts = <0 113 0>;
305 clocks = <&cmu CLK_I2C0>;
306 clock-names = "i2c";
307 pinctrl-names = "default";
308 pinctrl-0 = <&i2c0_bus>;
309 status = "disabled";
310 };
311
312 i2c_1: i2c@13870000 {
313 #address-cells = <1>;
314 #size-cells = <0>;
315 compatible = "samsung,s3c2440-i2c";
316 reg = <0x13870000 0x100>;
317 interrupts = <0 114 0>;
318 clocks = <&cmu CLK_I2C1>;
319 clock-names = "i2c";
320 pinctrl-names = "default";
321 pinctrl-0 = <&i2c1_bus>;
322 status = "disabled";
323 };
324
325 i2c_2: i2c@13880000 {
326 #address-cells = <1>;
327 #size-cells = <0>;
328 compatible = "samsung,s3c2440-i2c";
329 reg = <0x13880000 0x100>;
330 interrupts = <0 115 0>;
331 clocks = <&cmu CLK_I2C2>;
332 clock-names = "i2c";
333 pinctrl-names = "default";
334 pinctrl-0 = <&i2c2_bus>;
335 status = "disabled";
336 };
337
338 i2c_3: i2c@13890000 {
339 #address-cells = <1>;
340 #size-cells = <0>;
341 compatible = "samsung,s3c2440-i2c";
342 reg = <0x13890000 0x100>;
343 interrupts = <0 116 0>;
344 clocks = <&cmu CLK_I2C3>;
345 clock-names = "i2c";
346 pinctrl-names = "default";
347 pinctrl-0 = <&i2c3_bus>;
348 status = "disabled";
349 };
350
351 i2c_4: i2c@138A0000 {
352 #address-cells = <1>;
353 #size-cells = <0>;
354 compatible = "samsung,s3c2440-i2c";
355 reg = <0x138A0000 0x100>;
356 interrupts = <0 117 0>;
357 clocks = <&cmu CLK_I2C4>;
358 clock-names = "i2c";
359 pinctrl-names = "default";
360 pinctrl-0 = <&i2c4_bus>;
361 status = "disabled";
362 };
363
364 i2c_5: i2c@138B0000 {
365 #address-cells = <1>;
366 #size-cells = <0>;
367 compatible = "samsung,s3c2440-i2c";
368 reg = <0x138B0000 0x100>;
369 interrupts = <0 118 0>;
370 clocks = <&cmu CLK_I2C5>;
371 clock-names = "i2c";
372 pinctrl-names = "default";
373 pinctrl-0 = <&i2c5_bus>;
374 status = "disabled";
375 };
376
377 i2c_6: i2c@138C0000 {
378 #address-cells = <1>;
379 #size-cells = <0>;
380 compatible = "samsung,s3c2440-i2c";
381 reg = <0x138C0000 0x100>;
382 interrupts = <0 119 0>;
383 clocks = <&cmu CLK_I2C6>;
384 clock-names = "i2c";
385 pinctrl-names = "default";
386 pinctrl-0 = <&i2c6_bus>;
387 status = "disabled";
388 };
389
390 i2c_7: i2c@138D0000 {
391 #address-cells = <1>;
392 #size-cells = <0>;
393 compatible = "samsung,s3c2440-i2c";
394 reg = <0x138D0000 0x100>;
395 interrupts = <0 120 0>;
396 clocks = <&cmu CLK_I2C7>;
397 clock-names = "i2c";
398 pinctrl-names = "default";
399 pinctrl-0 = <&i2c7_bus>;
400 status = "disabled";
401 };
402
403 spi_0: spi@13920000 {
404 compatible = "samsung,exynos4210-spi";
405 reg = <0x13920000 0x100>;
406 interrupts = <0 121 0>;
407 dmas = <&pdma0 7>, <&pdma0 6>;
408 dma-names = "tx", "rx";
409 #address-cells = <1>;
410 #size-cells = <0>;
411 clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
412 clock-names = "spi", "spi_busclk0";
413 samsung,spi-src-clk = <0>;
414 pinctrl-names = "default";
415 pinctrl-0 = <&spi0_bus>;
416 status = "disabled";
417 };
418
419 spi_1: spi@13930000 {
420 compatible = "samsung,exynos4210-spi";
421 reg = <0x13930000 0x100>;
422 interrupts = <0 122 0>;
423 dmas = <&pdma1 7>, <&pdma1 6>;
424 dma-names = "tx", "rx";
425 #address-cells = <1>;
426 #size-cells = <0>;
427 clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
428 clock-names = "spi", "spi_busclk0";
429 samsung,spi-src-clk = <0>;
430 pinctrl-names = "default";
431 pinctrl-0 = <&spi1_bus>;
432 status = "disabled";
433 };
434
435 i2s2: i2s@13970000 {
436 compatible = "samsung,s3c6410-i2s";
437 reg = <0x13970000 0x100>;
438 interrupts = <0 126 0>;
439 clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
440 clock-names = "iis", "i2s_opclk0";
441 dmas = <&pdma0 14>, <&pdma0 13>;
442 dma-names = "tx", "rx";
443 pinctrl-0 = <&i2s2_bus>;
444 pinctrl-names = "default";
445 status = "disabled";
446 };
447
448 pwm: pwm@139D0000 {
449 compatible = "samsung,exynos4210-pwm";
450 reg = <0x139D0000 0x1000>;
451 interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
452 <0 107 0>, <0 108 0>;
453 #pwm-cells = <3>;
454 status = "disabled";
455 };
456
457 pmu {
458 compatible = "arm,cortex-a7-pmu";
459 interrupts = <0 18 0>, <0 19 0>;
460 };
461 };
462 };
463
464 #include "exynos3250-pinctrl.dtsi"
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