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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
[deliverable/linux.git] / arch / arm / boot / dts / exynos3250.dtsi
1 /*
2 * Samsung's Exynos3250 SoC device tree source
3 *
4 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
8 * based board files can include this file and provide values for board specfic
9 * bindings.
10 *
11 * Note: This file does not include device nodes for all the controllers in
12 * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
13 * nodes can be added to this file.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20 #include "skeleton.dtsi"
21 #include "exynos4-cpu-thermal.dtsi"
22 #include <dt-bindings/clock/exynos3250.h>
23
24 / {
25 compatible = "samsung,exynos3250";
26 interrupt-parent = <&gic>;
27
28 aliases {
29 pinctrl0 = &pinctrl_0;
30 pinctrl1 = &pinctrl_1;
31 mshc0 = &mshc_0;
32 mshc1 = &mshc_1;
33 spi0 = &spi_0;
34 spi1 = &spi_1;
35 i2c0 = &i2c_0;
36 i2c1 = &i2c_1;
37 i2c2 = &i2c_2;
38 i2c3 = &i2c_3;
39 i2c4 = &i2c_4;
40 i2c5 = &i2c_5;
41 i2c6 = &i2c_6;
42 i2c7 = &i2c_7;
43 serial0 = &serial_0;
44 serial1 = &serial_1;
45 };
46
47 cpus {
48 #address-cells = <1>;
49 #size-cells = <0>;
50
51 cpu0: cpu@0 {
52 device_type = "cpu";
53 compatible = "arm,cortex-a7";
54 reg = <0>;
55 clock-frequency = <1000000000>;
56 };
57
58 cpu1: cpu@1 {
59 device_type = "cpu";
60 compatible = "arm,cortex-a7";
61 reg = <1>;
62 clock-frequency = <1000000000>;
63 };
64 };
65
66 soc: soc {
67 compatible = "simple-bus";
68 #address-cells = <1>;
69 #size-cells = <1>;
70 ranges;
71
72 fixed-rate-clocks {
73 #address-cells = <1>;
74 #size-cells = <0>;
75
76 xusbxti: clock@0 {
77 compatible = "fixed-clock";
78 #address-cells = <1>;
79 #size-cells = <0>;
80 reg = <0>;
81 clock-frequency = <0>;
82 #clock-cells = <0>;
83 clock-output-names = "xusbxti";
84 };
85
86 xxti: clock@1 {
87 compatible = "fixed-clock";
88 reg = <1>;
89 clock-frequency = <0>;
90 #clock-cells = <0>;
91 clock-output-names = "xxti";
92 };
93
94 xtcxo: clock@2 {
95 compatible = "fixed-clock";
96 reg = <2>;
97 clock-frequency = <0>;
98 #clock-cells = <0>;
99 clock-output-names = "xtcxo";
100 };
101 };
102
103 sysram@02020000 {
104 compatible = "mmio-sram";
105 reg = <0x02020000 0x40000>;
106 #address-cells = <1>;
107 #size-cells = <1>;
108 ranges = <0 0x02020000 0x40000>;
109
110 smp-sysram@0 {
111 compatible = "samsung,exynos4210-sysram";
112 reg = <0x0 0x1000>;
113 };
114
115 smp-sysram@3f000 {
116 compatible = "samsung,exynos4210-sysram-ns";
117 reg = <0x3f000 0x1000>;
118 };
119 };
120
121 chipid@10000000 {
122 compatible = "samsung,exynos4210-chipid";
123 reg = <0x10000000 0x100>;
124 };
125
126 sys_reg: syscon@10010000 {
127 compatible = "samsung,exynos3-sysreg", "syscon";
128 reg = <0x10010000 0x400>;
129 };
130
131 pmu_system_controller: system-controller@10020000 {
132 compatible = "samsung,exynos3250-pmu", "syscon";
133 reg = <0x10020000 0x4000>;
134 };
135
136 mipi_phy: video-phy@10020710 {
137 compatible = "samsung,s5pv210-mipi-video-phy";
138 reg = <0x10020710 8>;
139 #phy-cells = <1>;
140 };
141
142 pd_cam: cam-power-domain@10023C00 {
143 compatible = "samsung,exynos4210-pd";
144 reg = <0x10023C00 0x20>;
145 #power-domain-cells = <0>;
146 };
147
148 pd_mfc: mfc-power-domain@10023C40 {
149 compatible = "samsung,exynos4210-pd";
150 reg = <0x10023C40 0x20>;
151 #power-domain-cells = <0>;
152 };
153
154 pd_g3d: g3d-power-domain@10023C60 {
155 compatible = "samsung,exynos4210-pd";
156 reg = <0x10023C60 0x20>;
157 #power-domain-cells = <0>;
158 };
159
160 pd_lcd0: lcd0-power-domain@10023C80 {
161 compatible = "samsung,exynos4210-pd";
162 reg = <0x10023C80 0x20>;
163 #power-domain-cells = <0>;
164 };
165
166 pd_isp: isp-power-domain@10023CA0 {
167 compatible = "samsung,exynos4210-pd";
168 reg = <0x10023CA0 0x20>;
169 #power-domain-cells = <0>;
170 };
171
172 cmu: clock-controller@10030000 {
173 compatible = "samsung,exynos3250-cmu";
174 reg = <0x10030000 0x20000>;
175 #clock-cells = <1>;
176 };
177
178 cmu_dmc: clock-controller@105C0000 {
179 compatible = "samsung,exynos3250-cmu-dmc";
180 reg = <0x105C0000 0x2000>;
181 #clock-cells = <1>;
182 };
183
184 rtc: rtc@10070000 {
185 compatible = "samsung,exynos3250-rtc";
186 reg = <0x10070000 0x100>;
187 interrupts = <0 73 0>, <0 74 0>;
188 status = "disabled";
189 };
190
191 tmu: tmu@100C0000 {
192 compatible = "samsung,exynos3250-tmu";
193 reg = <0x100C0000 0x100>;
194 interrupts = <0 216 0>;
195 clocks = <&cmu CLK_TMU_APBIF>;
196 clock-names = "tmu_apbif";
197 #include "exynos4412-tmu-sensor-conf.dtsi"
198 status = "disabled";
199 };
200
201 gic: interrupt-controller@10481000 {
202 compatible = "arm,cortex-a15-gic";
203 #interrupt-cells = <3>;
204 interrupt-controller;
205 reg = <0x10481000 0x1000>,
206 <0x10482000 0x1000>,
207 <0x10484000 0x2000>,
208 <0x10486000 0x2000>;
209 interrupts = <1 9 0xf04>;
210 };
211
212 mct@10050000 {
213 compatible = "samsung,exynos4210-mct";
214 reg = <0x10050000 0x800>;
215 interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
216 <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
217 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
218 clock-names = "fin_pll", "mct";
219 };
220
221 pinctrl_1: pinctrl@11000000 {
222 compatible = "samsung,exynos3250-pinctrl";
223 reg = <0x11000000 0x1000>;
224 interrupts = <0 225 0>;
225
226 wakeup-interrupt-controller {
227 compatible = "samsung,exynos4210-wakeup-eint";
228 interrupts = <0 48 0>;
229 };
230 };
231
232 pinctrl_0: pinctrl@11400000 {
233 compatible = "samsung,exynos3250-pinctrl";
234 reg = <0x11400000 0x1000>;
235 interrupts = <0 240 0>;
236 };
237
238 fimd: fimd@11c00000 {
239 compatible = "samsung,exynos3250-fimd";
240 reg = <0x11c00000 0x30000>;
241 interrupt-names = "fifo", "vsync", "lcd_sys";
242 interrupts = <0 84 0>, <0 85 0>, <0 86 0>;
243 clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
244 clock-names = "sclk_fimd", "fimd";
245 power-domains = <&pd_lcd0>;
246 samsung,sysreg = <&sys_reg>;
247 status = "disabled";
248 };
249
250 dsi_0: dsi@11C80000 {
251 compatible = "samsung,exynos3250-mipi-dsi";
252 reg = <0x11C80000 0x10000>;
253 interrupts = <0 83 0>;
254 samsung,phy-type = <0>;
255 power-domains = <&pd_lcd0>;
256 phys = <&mipi_phy 1>;
257 phy-names = "dsim";
258 clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
259 clock-names = "bus_clk", "pll_clk";
260 #address-cells = <1>;
261 #size-cells = <0>;
262 status = "disabled";
263 };
264
265 hsotg: hsotg@12480000 {
266 compatible = "snps,dwc2";
267 reg = <0x12480000 0x20000>;
268 interrupts = <0 141 0>;
269 clocks = <&cmu CLK_USBOTG>;
270 clock-names = "otg";
271 phys = <&exynos_usbphy 0>;
272 phy-names = "usb2-phy";
273 status = "disabled";
274 };
275
276 mshc_0: mshc@12510000 {
277 compatible = "samsung,exynos5250-dw-mshc";
278 reg = <0x12510000 0x1000>;
279 interrupts = <0 142 0>;
280 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
281 clock-names = "biu", "ciu";
282 fifo-depth = <0x80>;
283 #address-cells = <1>;
284 #size-cells = <0>;
285 status = "disabled";
286 };
287
288 mshc_1: mshc@12520000 {
289 compatible = "samsung,exynos5250-dw-mshc";
290 reg = <0x12520000 0x1000>;
291 interrupts = <0 143 0>;
292 clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
293 clock-names = "biu", "ciu";
294 fifo-depth = <0x80>;
295 #address-cells = <1>;
296 #size-cells = <0>;
297 status = "disabled";
298 };
299
300 exynos_usbphy: exynos-usbphy@125B0000 {
301 compatible = "samsung,exynos3250-usb2-phy";
302 reg = <0x125B0000 0x100>;
303 samsung,pmureg-phandle = <&pmu_system_controller>;
304 clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>;
305 clock-names = "phy", "ref";
306 #phy-cells = <1>;
307 status = "disabled";
308 };
309
310 amba {
311 compatible = "arm,amba-bus";
312 #address-cells = <1>;
313 #size-cells = <1>;
314 ranges;
315
316 pdma0: pdma@12680000 {
317 compatible = "arm,pl330", "arm,primecell";
318 reg = <0x12680000 0x1000>;
319 interrupts = <0 138 0>;
320 clocks = <&cmu CLK_PDMA0>;
321 clock-names = "apb_pclk";
322 #dma-cells = <1>;
323 #dma-channels = <8>;
324 #dma-requests = <32>;
325 };
326
327 pdma1: pdma@12690000 {
328 compatible = "arm,pl330", "arm,primecell";
329 reg = <0x12690000 0x1000>;
330 interrupts = <0 139 0>;
331 clocks = <&cmu CLK_PDMA1>;
332 clock-names = "apb_pclk";
333 #dma-cells = <1>;
334 #dma-channels = <8>;
335 #dma-requests = <32>;
336 };
337 };
338
339 adc: adc@126C0000 {
340 compatible = "samsung,exynos3250-adc",
341 "samsung,exynos-adc-v2";
342 reg = <0x126C0000 0x100>;
343 interrupts = <0 137 0>;
344 clock-names = "adc", "sclk";
345 clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
346 #io-channel-cells = <1>;
347 io-channel-ranges;
348 samsung,syscon-phandle = <&pmu_system_controller>;
349 status = "disabled";
350 };
351
352 mfc: codec@13400000 {
353 compatible = "samsung,mfc-v7";
354 reg = <0x13400000 0x10000>;
355 interrupts = <0 102 0>;
356 clock-names = "mfc", "sclk_mfc";
357 clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
358 power-domains = <&pd_mfc>;
359 status = "disabled";
360 };
361
362 serial_0: serial@13800000 {
363 compatible = "samsung,exynos4210-uart";
364 reg = <0x13800000 0x100>;
365 interrupts = <0 109 0>;
366 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
367 clock-names = "uart", "clk_uart_baud0";
368 pinctrl-names = "default";
369 pinctrl-0 = <&uart0_data &uart0_fctl>;
370 status = "disabled";
371 };
372
373 serial_1: serial@13810000 {
374 compatible = "samsung,exynos4210-uart";
375 reg = <0x13810000 0x100>;
376 interrupts = <0 110 0>;
377 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
378 clock-names = "uart", "clk_uart_baud0";
379 pinctrl-names = "default";
380 pinctrl-0 = <&uart1_data>;
381 status = "disabled";
382 };
383
384 i2c_0: i2c@13860000 {
385 #address-cells = <1>;
386 #size-cells = <0>;
387 compatible = "samsung,s3c2440-i2c";
388 reg = <0x13860000 0x100>;
389 interrupts = <0 113 0>;
390 clocks = <&cmu CLK_I2C0>;
391 clock-names = "i2c";
392 pinctrl-names = "default";
393 pinctrl-0 = <&i2c0_bus>;
394 status = "disabled";
395 };
396
397 i2c_1: i2c@13870000 {
398 #address-cells = <1>;
399 #size-cells = <0>;
400 compatible = "samsung,s3c2440-i2c";
401 reg = <0x13870000 0x100>;
402 interrupts = <0 114 0>;
403 clocks = <&cmu CLK_I2C1>;
404 clock-names = "i2c";
405 pinctrl-names = "default";
406 pinctrl-0 = <&i2c1_bus>;
407 status = "disabled";
408 };
409
410 i2c_2: i2c@13880000 {
411 #address-cells = <1>;
412 #size-cells = <0>;
413 compatible = "samsung,s3c2440-i2c";
414 reg = <0x13880000 0x100>;
415 interrupts = <0 115 0>;
416 clocks = <&cmu CLK_I2C2>;
417 clock-names = "i2c";
418 pinctrl-names = "default";
419 pinctrl-0 = <&i2c2_bus>;
420 status = "disabled";
421 };
422
423 i2c_3: i2c@13890000 {
424 #address-cells = <1>;
425 #size-cells = <0>;
426 compatible = "samsung,s3c2440-i2c";
427 reg = <0x13890000 0x100>;
428 interrupts = <0 116 0>;
429 clocks = <&cmu CLK_I2C3>;
430 clock-names = "i2c";
431 pinctrl-names = "default";
432 pinctrl-0 = <&i2c3_bus>;
433 status = "disabled";
434 };
435
436 i2c_4: i2c@138A0000 {
437 #address-cells = <1>;
438 #size-cells = <0>;
439 compatible = "samsung,s3c2440-i2c";
440 reg = <0x138A0000 0x100>;
441 interrupts = <0 117 0>;
442 clocks = <&cmu CLK_I2C4>;
443 clock-names = "i2c";
444 pinctrl-names = "default";
445 pinctrl-0 = <&i2c4_bus>;
446 status = "disabled";
447 };
448
449 i2c_5: i2c@138B0000 {
450 #address-cells = <1>;
451 #size-cells = <0>;
452 compatible = "samsung,s3c2440-i2c";
453 reg = <0x138B0000 0x100>;
454 interrupts = <0 118 0>;
455 clocks = <&cmu CLK_I2C5>;
456 clock-names = "i2c";
457 pinctrl-names = "default";
458 pinctrl-0 = <&i2c5_bus>;
459 status = "disabled";
460 };
461
462 i2c_6: i2c@138C0000 {
463 #address-cells = <1>;
464 #size-cells = <0>;
465 compatible = "samsung,s3c2440-i2c";
466 reg = <0x138C0000 0x100>;
467 interrupts = <0 119 0>;
468 clocks = <&cmu CLK_I2C6>;
469 clock-names = "i2c";
470 pinctrl-names = "default";
471 pinctrl-0 = <&i2c6_bus>;
472 status = "disabled";
473 };
474
475 i2c_7: i2c@138D0000 {
476 #address-cells = <1>;
477 #size-cells = <0>;
478 compatible = "samsung,s3c2440-i2c";
479 reg = <0x138D0000 0x100>;
480 interrupts = <0 120 0>;
481 clocks = <&cmu CLK_I2C7>;
482 clock-names = "i2c";
483 pinctrl-names = "default";
484 pinctrl-0 = <&i2c7_bus>;
485 status = "disabled";
486 };
487
488 spi_0: spi@13920000 {
489 compatible = "samsung,exynos4210-spi";
490 reg = <0x13920000 0x100>;
491 interrupts = <0 121 0>;
492 dmas = <&pdma0 7>, <&pdma0 6>;
493 dma-names = "tx", "rx";
494 #address-cells = <1>;
495 #size-cells = <0>;
496 clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
497 clock-names = "spi", "spi_busclk0";
498 samsung,spi-src-clk = <0>;
499 pinctrl-names = "default";
500 pinctrl-0 = <&spi0_bus>;
501 status = "disabled";
502 };
503
504 spi_1: spi@13930000 {
505 compatible = "samsung,exynos4210-spi";
506 reg = <0x13930000 0x100>;
507 interrupts = <0 122 0>;
508 dmas = <&pdma1 7>, <&pdma1 6>;
509 dma-names = "tx", "rx";
510 #address-cells = <1>;
511 #size-cells = <0>;
512 clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
513 clock-names = "spi", "spi_busclk0";
514 samsung,spi-src-clk = <0>;
515 pinctrl-names = "default";
516 pinctrl-0 = <&spi1_bus>;
517 status = "disabled";
518 };
519
520 i2s2: i2s@13970000 {
521 compatible = "samsung,s3c6410-i2s";
522 reg = <0x13970000 0x100>;
523 interrupts = <0 126 0>;
524 clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
525 clock-names = "iis", "i2s_opclk0";
526 dmas = <&pdma0 14>, <&pdma0 13>;
527 dma-names = "tx", "rx";
528 pinctrl-0 = <&i2s2_bus>;
529 pinctrl-names = "default";
530 status = "disabled";
531 };
532
533 pwm: pwm@139D0000 {
534 compatible = "samsung,exynos4210-pwm";
535 reg = <0x139D0000 0x1000>;
536 interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
537 <0 107 0>, <0 108 0>;
538 #pwm-cells = <3>;
539 status = "disabled";
540 };
541
542 pmu {
543 compatible = "arm,cortex-a7-pmu";
544 interrupts = <0 18 0>, <0 19 0>;
545 };
546
547 ppmu_dmc0: ppmu_dmc0@106a0000 {
548 compatible = "samsung,exynos-ppmu";
549 reg = <0x106a0000 0x2000>;
550 status = "disabled";
551 };
552
553 ppmu_dmc1: ppmu_dmc1@106b0000 {
554 compatible = "samsung,exynos-ppmu";
555 reg = <0x106b0000 0x2000>;
556 status = "disabled";
557 };
558
559 ppmu_cpu: ppmu_cpu@106c0000 {
560 compatible = "samsung,exynos-ppmu";
561 reg = <0x106c0000 0x2000>;
562 status = "disabled";
563 };
564
565 ppmu_rightbus: ppmu_rightbus@112a0000 {
566 compatible = "samsung,exynos-ppmu";
567 reg = <0x112a0000 0x2000>;
568 clocks = <&cmu CLK_PPMURIGHT>;
569 clock-names = "ppmu";
570 status = "disabled";
571 };
572
573 ppmu_leftbus: ppmu_leftbus0@116a0000 {
574 compatible = "samsung,exynos-ppmu";
575 reg = <0x116a0000 0x2000>;
576 clocks = <&cmu CLK_PPMULEFT>;
577 clock-names = "ppmu";
578 status = "disabled";
579 };
580
581 ppmu_camif: ppmu_camif@11ac0000 {
582 compatible = "samsung,exynos-ppmu";
583 reg = <0x11ac0000 0x2000>;
584 clocks = <&cmu CLK_PPMUCAMIF>;
585 clock-names = "ppmu";
586 status = "disabled";
587 };
588
589 ppmu_lcd0: ppmu_lcd0@11e40000 {
590 compatible = "samsung,exynos-ppmu";
591 reg = <0x11e40000 0x2000>;
592 clocks = <&cmu CLK_PPMULCD0>;
593 clock-names = "ppmu";
594 status = "disabled";
595 };
596
597 ppmu_fsys: ppmu_fsys@12630000 {
598 compatible = "samsung,exynos-ppmu";
599 reg = <0x12630000 0x2000>;
600 clocks = <&cmu CLK_PPMUFILE>;
601 clock-names = "ppmu";
602 status = "disabled";
603 };
604
605 ppmu_g3d: ppmu_g3d@13220000 {
606 compatible = "samsung,exynos-ppmu";
607 reg = <0x13220000 0x2000>;
608 clocks = <&cmu CLK_PPMUG3D>;
609 clock-names = "ppmu";
610 status = "disabled";
611 };
612
613 ppmu_mfc: ppmu_mfc@13660000 {
614 compatible = "samsung,exynos-ppmu";
615 reg = <0x13660000 0x2000>;
616 clocks = <&cmu CLK_PPMUMFC_L>;
617 clock-names = "ppmu";
618 status = "disabled";
619 };
620 };
621 };
622
623 #include "exynos3250-pinctrl.dtsi"
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