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Merge tag 'armsoc-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
[deliverable/linux.git] / arch / arm / boot / dts / exynos3250.dtsi
1 /*
2 * Samsung's Exynos3250 SoC device tree source
3 *
4 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
8 * based board files can include this file and provide values for board specfic
9 * bindings.
10 *
11 * Note: This file does not include device nodes for all the controllers in
12 * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
13 * nodes can be added to this file.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20 #include "skeleton.dtsi"
21 #include "exynos4-cpu-thermal.dtsi"
22 #include <dt-bindings/clock/exynos3250.h>
23
24 / {
25 compatible = "samsung,exynos3250";
26 interrupt-parent = <&gic>;
27
28 aliases {
29 pinctrl0 = &pinctrl_0;
30 pinctrl1 = &pinctrl_1;
31 mshc0 = &mshc_0;
32 mshc1 = &mshc_1;
33 spi0 = &spi_0;
34 spi1 = &spi_1;
35 i2c0 = &i2c_0;
36 i2c1 = &i2c_1;
37 i2c2 = &i2c_2;
38 i2c3 = &i2c_3;
39 i2c4 = &i2c_4;
40 i2c5 = &i2c_5;
41 i2c6 = &i2c_6;
42 i2c7 = &i2c_7;
43 serial0 = &serial_0;
44 serial1 = &serial_1;
45 };
46
47 cpus {
48 #address-cells = <1>;
49 #size-cells = <0>;
50
51 cpu0: cpu@0 {
52 device_type = "cpu";
53 compatible = "arm,cortex-a7";
54 reg = <0>;
55 clock-frequency = <1000000000>;
56 };
57
58 cpu1: cpu@1 {
59 device_type = "cpu";
60 compatible = "arm,cortex-a7";
61 reg = <1>;
62 clock-frequency = <1000000000>;
63 };
64 };
65
66 soc: soc {
67 compatible = "simple-bus";
68 #address-cells = <1>;
69 #size-cells = <1>;
70 ranges;
71
72 fixed-rate-clocks {
73 #address-cells = <1>;
74 #size-cells = <0>;
75
76 xusbxti: clock@0 {
77 compatible = "fixed-clock";
78 #address-cells = <1>;
79 #size-cells = <0>;
80 reg = <0>;
81 clock-frequency = <0>;
82 #clock-cells = <0>;
83 clock-output-names = "xusbxti";
84 };
85
86 xxti: clock@1 {
87 compatible = "fixed-clock";
88 reg = <1>;
89 clock-frequency = <0>;
90 #clock-cells = <0>;
91 clock-output-names = "xxti";
92 };
93
94 xtcxo: clock@2 {
95 compatible = "fixed-clock";
96 reg = <2>;
97 clock-frequency = <0>;
98 #clock-cells = <0>;
99 clock-output-names = "xtcxo";
100 };
101 };
102
103 sysram@02020000 {
104 compatible = "mmio-sram";
105 reg = <0x02020000 0x40000>;
106 #address-cells = <1>;
107 #size-cells = <1>;
108 ranges = <0 0x02020000 0x40000>;
109
110 smp-sysram@0 {
111 compatible = "samsung,exynos4210-sysram";
112 reg = <0x0 0x1000>;
113 };
114
115 smp-sysram@3f000 {
116 compatible = "samsung,exynos4210-sysram-ns";
117 reg = <0x3f000 0x1000>;
118 };
119 };
120
121 chipid@10000000 {
122 compatible = "samsung,exynos4210-chipid";
123 reg = <0x10000000 0x100>;
124 };
125
126 sys_reg: syscon@10010000 {
127 compatible = "samsung,exynos3-sysreg", "syscon";
128 reg = <0x10010000 0x400>;
129 };
130
131 pmu_system_controller: system-controller@10020000 {
132 compatible = "samsung,exynos3250-pmu", "syscon";
133 reg = <0x10020000 0x4000>;
134 interrupt-controller;
135 #interrupt-cells = <3>;
136 interrupt-parent = <&gic>;
137 };
138
139 mipi_phy: video-phy@10020710 {
140 compatible = "samsung,s5pv210-mipi-video-phy";
141 reg = <0x10020710 8>;
142 #phy-cells = <1>;
143 };
144
145 pd_cam: cam-power-domain@10023C00 {
146 compatible = "samsung,exynos4210-pd";
147 reg = <0x10023C00 0x20>;
148 #power-domain-cells = <0>;
149 };
150
151 pd_mfc: mfc-power-domain@10023C40 {
152 compatible = "samsung,exynos4210-pd";
153 reg = <0x10023C40 0x20>;
154 #power-domain-cells = <0>;
155 };
156
157 pd_g3d: g3d-power-domain@10023C60 {
158 compatible = "samsung,exynos4210-pd";
159 reg = <0x10023C60 0x20>;
160 #power-domain-cells = <0>;
161 };
162
163 pd_lcd0: lcd0-power-domain@10023C80 {
164 compatible = "samsung,exynos4210-pd";
165 reg = <0x10023C80 0x20>;
166 #power-domain-cells = <0>;
167 };
168
169 pd_isp: isp-power-domain@10023CA0 {
170 compatible = "samsung,exynos4210-pd";
171 reg = <0x10023CA0 0x20>;
172 #power-domain-cells = <0>;
173 };
174
175 cmu: clock-controller@10030000 {
176 compatible = "samsung,exynos3250-cmu";
177 reg = <0x10030000 0x20000>;
178 #clock-cells = <1>;
179 };
180
181 cmu_dmc: clock-controller@105C0000 {
182 compatible = "samsung,exynos3250-cmu-dmc";
183 reg = <0x105C0000 0x2000>;
184 #clock-cells = <1>;
185 };
186
187 rtc: rtc@10070000 {
188 compatible = "samsung,exynos3250-rtc";
189 reg = <0x10070000 0x100>;
190 interrupts = <0 73 0>, <0 74 0>;
191 interrupt-parent = <&pmu_system_controller>;
192 status = "disabled";
193 };
194
195 tmu: tmu@100C0000 {
196 compatible = "samsung,exynos3250-tmu";
197 reg = <0x100C0000 0x100>;
198 interrupts = <0 216 0>;
199 clocks = <&cmu CLK_TMU_APBIF>;
200 clock-names = "tmu_apbif";
201 #include "exynos4412-tmu-sensor-conf.dtsi"
202 status = "disabled";
203 };
204
205 gic: interrupt-controller@10481000 {
206 compatible = "arm,cortex-a15-gic";
207 #interrupt-cells = <3>;
208 interrupt-controller;
209 reg = <0x10481000 0x1000>,
210 <0x10482000 0x1000>,
211 <0x10484000 0x2000>,
212 <0x10486000 0x2000>;
213 interrupts = <1 9 0xf04>;
214 };
215
216 mct@10050000 {
217 compatible = "samsung,exynos4210-mct";
218 reg = <0x10050000 0x800>;
219 interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
220 <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
221 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
222 clock-names = "fin_pll", "mct";
223 };
224
225 pinctrl_1: pinctrl@11000000 {
226 compatible = "samsung,exynos3250-pinctrl";
227 reg = <0x11000000 0x1000>;
228 interrupts = <0 225 0>;
229
230 wakeup-interrupt-controller {
231 compatible = "samsung,exynos4210-wakeup-eint";
232 interrupts = <0 48 0>;
233 };
234 };
235
236 pinctrl_0: pinctrl@11400000 {
237 compatible = "samsung,exynos3250-pinctrl";
238 reg = <0x11400000 0x1000>;
239 interrupts = <0 240 0>;
240 };
241
242 fimd: fimd@11c00000 {
243 compatible = "samsung,exynos3250-fimd";
244 reg = <0x11c00000 0x30000>;
245 interrupt-names = "fifo", "vsync", "lcd_sys";
246 interrupts = <0 84 0>, <0 85 0>, <0 86 0>;
247 clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
248 clock-names = "sclk_fimd", "fimd";
249 power-domains = <&pd_lcd0>;
250 samsung,sysreg = <&sys_reg>;
251 status = "disabled";
252 };
253
254 dsi_0: dsi@11C80000 {
255 compatible = "samsung,exynos3250-mipi-dsi";
256 reg = <0x11C80000 0x10000>;
257 interrupts = <0 83 0>;
258 samsung,phy-type = <0>;
259 power-domains = <&pd_lcd0>;
260 phys = <&mipi_phy 1>;
261 phy-names = "dsim";
262 clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
263 clock-names = "bus_clk", "pll_clk";
264 #address-cells = <1>;
265 #size-cells = <0>;
266 status = "disabled";
267 };
268
269 hsotg: hsotg@12480000 {
270 compatible = "snps,dwc2";
271 reg = <0x12480000 0x20000>;
272 interrupts = <0 141 0>;
273 clocks = <&cmu CLK_USBOTG>;
274 clock-names = "otg";
275 phys = <&exynos_usbphy 0>;
276 phy-names = "usb2-phy";
277 status = "disabled";
278 };
279
280 mshc_0: mshc@12510000 {
281 compatible = "samsung,exynos5250-dw-mshc";
282 reg = <0x12510000 0x1000>;
283 interrupts = <0 142 0>;
284 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
285 clock-names = "biu", "ciu";
286 fifo-depth = <0x80>;
287 #address-cells = <1>;
288 #size-cells = <0>;
289 status = "disabled";
290 };
291
292 mshc_1: mshc@12520000 {
293 compatible = "samsung,exynos5250-dw-mshc";
294 reg = <0x12520000 0x1000>;
295 interrupts = <0 143 0>;
296 clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
297 clock-names = "biu", "ciu";
298 fifo-depth = <0x80>;
299 #address-cells = <1>;
300 #size-cells = <0>;
301 status = "disabled";
302 };
303
304 exynos_usbphy: exynos-usbphy@125B0000 {
305 compatible = "samsung,exynos3250-usb2-phy";
306 reg = <0x125B0000 0x100>;
307 samsung,pmureg-phandle = <&pmu_system_controller>;
308 clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>;
309 clock-names = "phy", "ref";
310 #phy-cells = <1>;
311 status = "disabled";
312 };
313
314 amba {
315 compatible = "arm,amba-bus";
316 #address-cells = <1>;
317 #size-cells = <1>;
318 ranges;
319
320 pdma0: pdma@12680000 {
321 compatible = "arm,pl330", "arm,primecell";
322 reg = <0x12680000 0x1000>;
323 interrupts = <0 138 0>;
324 clocks = <&cmu CLK_PDMA0>;
325 clock-names = "apb_pclk";
326 #dma-cells = <1>;
327 #dma-channels = <8>;
328 #dma-requests = <32>;
329 };
330
331 pdma1: pdma@12690000 {
332 compatible = "arm,pl330", "arm,primecell";
333 reg = <0x12690000 0x1000>;
334 interrupts = <0 139 0>;
335 clocks = <&cmu CLK_PDMA1>;
336 clock-names = "apb_pclk";
337 #dma-cells = <1>;
338 #dma-channels = <8>;
339 #dma-requests = <32>;
340 };
341 };
342
343 adc: adc@126C0000 {
344 compatible = "samsung,exynos3250-adc",
345 "samsung,exynos-adc-v2";
346 reg = <0x126C0000 0x100>;
347 interrupts = <0 137 0>;
348 clock-names = "adc", "sclk";
349 clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
350 #io-channel-cells = <1>;
351 io-channel-ranges;
352 samsung,syscon-phandle = <&pmu_system_controller>;
353 status = "disabled";
354 };
355
356 mfc: codec@13400000 {
357 compatible = "samsung,mfc-v7";
358 reg = <0x13400000 0x10000>;
359 interrupts = <0 102 0>;
360 clock-names = "mfc", "sclk_mfc";
361 clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
362 power-domains = <&pd_mfc>;
363 status = "disabled";
364 };
365
366 serial_0: serial@13800000 {
367 compatible = "samsung,exynos4210-uart";
368 reg = <0x13800000 0x100>;
369 interrupts = <0 109 0>;
370 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
371 clock-names = "uart", "clk_uart_baud0";
372 pinctrl-names = "default";
373 pinctrl-0 = <&uart0_data &uart0_fctl>;
374 status = "disabled";
375 };
376
377 serial_1: serial@13810000 {
378 compatible = "samsung,exynos4210-uart";
379 reg = <0x13810000 0x100>;
380 interrupts = <0 110 0>;
381 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
382 clock-names = "uart", "clk_uart_baud0";
383 pinctrl-names = "default";
384 pinctrl-0 = <&uart1_data>;
385 status = "disabled";
386 };
387
388 i2c_0: i2c@13860000 {
389 #address-cells = <1>;
390 #size-cells = <0>;
391 compatible = "samsung,s3c2440-i2c";
392 reg = <0x13860000 0x100>;
393 interrupts = <0 113 0>;
394 clocks = <&cmu CLK_I2C0>;
395 clock-names = "i2c";
396 pinctrl-names = "default";
397 pinctrl-0 = <&i2c0_bus>;
398 status = "disabled";
399 };
400
401 i2c_1: i2c@13870000 {
402 #address-cells = <1>;
403 #size-cells = <0>;
404 compatible = "samsung,s3c2440-i2c";
405 reg = <0x13870000 0x100>;
406 interrupts = <0 114 0>;
407 clocks = <&cmu CLK_I2C1>;
408 clock-names = "i2c";
409 pinctrl-names = "default";
410 pinctrl-0 = <&i2c1_bus>;
411 status = "disabled";
412 };
413
414 i2c_2: i2c@13880000 {
415 #address-cells = <1>;
416 #size-cells = <0>;
417 compatible = "samsung,s3c2440-i2c";
418 reg = <0x13880000 0x100>;
419 interrupts = <0 115 0>;
420 clocks = <&cmu CLK_I2C2>;
421 clock-names = "i2c";
422 pinctrl-names = "default";
423 pinctrl-0 = <&i2c2_bus>;
424 status = "disabled";
425 };
426
427 i2c_3: i2c@13890000 {
428 #address-cells = <1>;
429 #size-cells = <0>;
430 compatible = "samsung,s3c2440-i2c";
431 reg = <0x13890000 0x100>;
432 interrupts = <0 116 0>;
433 clocks = <&cmu CLK_I2C3>;
434 clock-names = "i2c";
435 pinctrl-names = "default";
436 pinctrl-0 = <&i2c3_bus>;
437 status = "disabled";
438 };
439
440 i2c_4: i2c@138A0000 {
441 #address-cells = <1>;
442 #size-cells = <0>;
443 compatible = "samsung,s3c2440-i2c";
444 reg = <0x138A0000 0x100>;
445 interrupts = <0 117 0>;
446 clocks = <&cmu CLK_I2C4>;
447 clock-names = "i2c";
448 pinctrl-names = "default";
449 pinctrl-0 = <&i2c4_bus>;
450 status = "disabled";
451 };
452
453 i2c_5: i2c@138B0000 {
454 #address-cells = <1>;
455 #size-cells = <0>;
456 compatible = "samsung,s3c2440-i2c";
457 reg = <0x138B0000 0x100>;
458 interrupts = <0 118 0>;
459 clocks = <&cmu CLK_I2C5>;
460 clock-names = "i2c";
461 pinctrl-names = "default";
462 pinctrl-0 = <&i2c5_bus>;
463 status = "disabled";
464 };
465
466 i2c_6: i2c@138C0000 {
467 #address-cells = <1>;
468 #size-cells = <0>;
469 compatible = "samsung,s3c2440-i2c";
470 reg = <0x138C0000 0x100>;
471 interrupts = <0 119 0>;
472 clocks = <&cmu CLK_I2C6>;
473 clock-names = "i2c";
474 pinctrl-names = "default";
475 pinctrl-0 = <&i2c6_bus>;
476 status = "disabled";
477 };
478
479 i2c_7: i2c@138D0000 {
480 #address-cells = <1>;
481 #size-cells = <0>;
482 compatible = "samsung,s3c2440-i2c";
483 reg = <0x138D0000 0x100>;
484 interrupts = <0 120 0>;
485 clocks = <&cmu CLK_I2C7>;
486 clock-names = "i2c";
487 pinctrl-names = "default";
488 pinctrl-0 = <&i2c7_bus>;
489 status = "disabled";
490 };
491
492 spi_0: spi@13920000 {
493 compatible = "samsung,exynos4210-spi";
494 reg = <0x13920000 0x100>;
495 interrupts = <0 121 0>;
496 dmas = <&pdma0 7>, <&pdma0 6>;
497 dma-names = "tx", "rx";
498 #address-cells = <1>;
499 #size-cells = <0>;
500 clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
501 clock-names = "spi", "spi_busclk0";
502 samsung,spi-src-clk = <0>;
503 pinctrl-names = "default";
504 pinctrl-0 = <&spi0_bus>;
505 status = "disabled";
506 };
507
508 spi_1: spi@13930000 {
509 compatible = "samsung,exynos4210-spi";
510 reg = <0x13930000 0x100>;
511 interrupts = <0 122 0>;
512 dmas = <&pdma1 7>, <&pdma1 6>;
513 dma-names = "tx", "rx";
514 #address-cells = <1>;
515 #size-cells = <0>;
516 clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
517 clock-names = "spi", "spi_busclk0";
518 samsung,spi-src-clk = <0>;
519 pinctrl-names = "default";
520 pinctrl-0 = <&spi1_bus>;
521 status = "disabled";
522 };
523
524 i2s2: i2s@13970000 {
525 compatible = "samsung,s3c6410-i2s";
526 reg = <0x13970000 0x100>;
527 interrupts = <0 126 0>;
528 clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
529 clock-names = "iis", "i2s_opclk0";
530 dmas = <&pdma0 14>, <&pdma0 13>;
531 dma-names = "tx", "rx";
532 pinctrl-0 = <&i2s2_bus>;
533 pinctrl-names = "default";
534 status = "disabled";
535 };
536
537 pwm: pwm@139D0000 {
538 compatible = "samsung,exynos4210-pwm";
539 reg = <0x139D0000 0x1000>;
540 interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
541 <0 107 0>, <0 108 0>;
542 #pwm-cells = <3>;
543 status = "disabled";
544 };
545
546 pmu {
547 compatible = "arm,cortex-a7-pmu";
548 interrupts = <0 18 0>, <0 19 0>;
549 };
550
551 ppmu_dmc0: ppmu_dmc0@106a0000 {
552 compatible = "samsung,exynos-ppmu";
553 reg = <0x106a0000 0x2000>;
554 status = "disabled";
555 };
556
557 ppmu_dmc1: ppmu_dmc1@106b0000 {
558 compatible = "samsung,exynos-ppmu";
559 reg = <0x106b0000 0x2000>;
560 status = "disabled";
561 };
562
563 ppmu_cpu: ppmu_cpu@106c0000 {
564 compatible = "samsung,exynos-ppmu";
565 reg = <0x106c0000 0x2000>;
566 status = "disabled";
567 };
568
569 ppmu_rightbus: ppmu_rightbus@112a0000 {
570 compatible = "samsung,exynos-ppmu";
571 reg = <0x112a0000 0x2000>;
572 clocks = <&cmu CLK_PPMURIGHT>;
573 clock-names = "ppmu";
574 status = "disabled";
575 };
576
577 ppmu_leftbus: ppmu_leftbus0@116a0000 {
578 compatible = "samsung,exynos-ppmu";
579 reg = <0x116a0000 0x2000>;
580 clocks = <&cmu CLK_PPMULEFT>;
581 clock-names = "ppmu";
582 status = "disabled";
583 };
584
585 ppmu_camif: ppmu_camif@11ac0000 {
586 compatible = "samsung,exynos-ppmu";
587 reg = <0x11ac0000 0x2000>;
588 clocks = <&cmu CLK_PPMUCAMIF>;
589 clock-names = "ppmu";
590 status = "disabled";
591 };
592
593 ppmu_lcd0: ppmu_lcd0@11e40000 {
594 compatible = "samsung,exynos-ppmu";
595 reg = <0x11e40000 0x2000>;
596 clocks = <&cmu CLK_PPMULCD0>;
597 clock-names = "ppmu";
598 status = "disabled";
599 };
600
601 ppmu_fsys: ppmu_fsys@12630000 {
602 compatible = "samsung,exynos-ppmu";
603 reg = <0x12630000 0x2000>;
604 clocks = <&cmu CLK_PPMUFILE>;
605 clock-names = "ppmu";
606 status = "disabled";
607 };
608
609 ppmu_g3d: ppmu_g3d@13220000 {
610 compatible = "samsung,exynos-ppmu";
611 reg = <0x13220000 0x2000>;
612 clocks = <&cmu CLK_PPMUG3D>;
613 clock-names = "ppmu";
614 status = "disabled";
615 };
616
617 ppmu_mfc: ppmu_mfc@13660000 {
618 compatible = "samsung,exynos-ppmu";
619 reg = <0x13660000 0x2000>;
620 clocks = <&cmu CLK_PPMUMFC_L>;
621 clock-names = "ppmu";
622 status = "disabled";
623 };
624 };
625 };
626
627 #include "exynos3250-pinctrl.dtsi"
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