arch/arm/boot/dts/exynos5420-cpus.dtsi

   1 /*
   2  * SAMSUNG EXYNOS5420 SoC cpu device tree source
   3  *
   4  * Copyright (c) 2015 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * This file provides desired ordering for Exynos5420 and Exynos5800
   8  * boards: CPU[0123] being the A15.
   9  *
  10  * The Exynos5420, 5422 and 5800 actually share the same CPU configuration
  11  * but particular boards choose different booting order.
  12  *
  13  * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
  14  * booting cluster (big or LITTLE) is chosen by IROM code by reading
  15  * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
  16  * from the LITTLE: Cortex-A7.
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License version 2 as
  20  * published by the Free Software Foundation.
  21  */
  22
  23 / {
  24         cpus {
  25                 #address-cells = <1>;
  26                 #size-cells = <0>;
  27
  28                 cpu0: cpu@0 {
  29                         device_type = "cpu";
  30                         compatible = "arm,cortex-a15";
  31                         reg = <0x0>;
  32                         clocks = <&clock CLK_ARM_CLK>;
  33                         clock-frequency = <1800000000>;
  34                         cci-control-port = <&cci_control1>;
  35                         operating-points-v2 = <&cluster_a15_opp_table>;
  36                         cooling-min-level = <0>;
  37                         cooling-max-level = <11>;
  38                         #cooling-cells = <2>; /* min followed by max */
  39                 };
  40
  41                 cpu1: cpu@1 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a15";
  44                         reg = <0x1>;
  45                         clock-frequency = <1800000000>;
  46                         cci-control-port = <&cci_control1>;
  47                         operating-points-v2 = <&cluster_a15_opp_table>;
  48                         cooling-min-level = <0>;
  49                         cooling-max-level = <11>;
  50                         #cooling-cells = <2>; /* min followed by max */
  51                 };
  52
  53                 cpu2: cpu@2 {
  54                         device_type = "cpu";
  55                         compatible = "arm,cortex-a15";
  56                         reg = <0x2>;
  57                         clock-frequency = <1800000000>;
  58                         cci-control-port = <&cci_control1>;
  59                         operating-points-v2 = <&cluster_a15_opp_table>;
  60                         cooling-min-level = <0>;
  61                         cooling-max-level = <11>;
  62                         #cooling-cells = <2>; /* min followed by max */
  63                 };
  64
  65                 cpu3: cpu@3 {
  66                         device_type = "cpu";
  67                         compatible = "arm,cortex-a15";
  68                         reg = <0x3>;
  69                         clock-frequency = <1800000000>;
  70                         cci-control-port = <&cci_control1>;
  71                         operating-points-v2 = <&cluster_a15_opp_table>;
  72                         cooling-min-level = <0>;
  73                         cooling-max-level = <11>;
  74                         #cooling-cells = <2>; /* min followed by max */
  75                 };
  76
  77                 cpu4: cpu@100 {
  78                         device_type = "cpu";
  79                         compatible = "arm,cortex-a7";
  80                         reg = <0x100>;
  81                         clocks = <&clock CLK_KFC_CLK>;
  82                         clock-frequency = <1000000000>;
  83                         cci-control-port = <&cci_control0>;
  84                         operating-points-v2 = <&cluster_a7_opp_table>;
  85                         cooling-min-level = <0>;
  86                         cooling-max-level = <7>;
  87                         #cooling-cells = <2>; /* min followed by max */
  88                 };
  89
  90                 cpu5: cpu@101 {
  91                         device_type = "cpu";
  92                         compatible = "arm,cortex-a7";
  93                         reg = <0x101>;
  94                         clock-frequency = <1000000000>;
  95                         cci-control-port = <&cci_control0>;
  96                         operating-points-v2 = <&cluster_a7_opp_table>;
  97                         cooling-min-level = <0>;
  98                         cooling-max-level = <7>;
  99                         #cooling-cells = <2>; /* min followed by max */
 100                 };
 101
 102                 cpu6: cpu@102 {
 103                         device_type = "cpu";
 104                         compatible = "arm,cortex-a7";
 105                         reg = <0x102>;
 106                         clock-frequency = <1000000000>;
 107                         cci-control-port = <&cci_control0>;
 108                         operating-points-v2 = <&cluster_a7_opp_table>;
 109                         cooling-min-level = <0>;
 110                         cooling-max-level = <7>;
 111                         #cooling-cells = <2>; /* min followed by max */
 112                 };
 113
 114                 cpu7: cpu@103 {
 115                         device_type = "cpu";
 116                         compatible = "arm,cortex-a7";
 117                         reg = <0x103>;
 118                         clock-frequency = <1000000000>;
 119                         cci-control-port = <&cci_control0>;
 120                         operating-points-v2 = <&cluster_a7_opp_table>;
 121                         cooling-min-level = <0>;
 122                         cooling-max-level = <7>;
 123                         #cooling-cells = <2>; /* min followed by max */
 124                 };
 125         };
 126 };