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ARM: dts: exynos: Move Exynos5250 and Exynos5420 nodes under soc
[deliverable/linux.git] / arch / arm / boot / dts / exynos5420.dtsi
1 /*
2 * SAMSUNG EXYNOS5420 SoC device tree source
3 *
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
8 * EXYNOS5420 based board files can include this file and provide
9 * values for board specfic bindings.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16 #include <dt-bindings/clock/exynos5420.h>
17 #include "exynos5.dtsi"
18
19 #include <dt-bindings/clock/exynos-audss-clk.h>
20
21 / {
22 compatible = "samsung,exynos5420", "samsung,exynos5";
23
24 aliases {
25 mshc0 = &mmc_0;
26 mshc1 = &mmc_1;
27 mshc2 = &mmc_2;
28 pinctrl0 = &pinctrl_0;
29 pinctrl1 = &pinctrl_1;
30 pinctrl2 = &pinctrl_2;
31 pinctrl3 = &pinctrl_3;
32 pinctrl4 = &pinctrl_4;
33 i2c4 = &hsi2c_4;
34 i2c5 = &hsi2c_5;
35 i2c6 = &hsi2c_6;
36 i2c7 = &hsi2c_7;
37 i2c8 = &hsi2c_8;
38 i2c9 = &hsi2c_9;
39 i2c10 = &hsi2c_10;
40 gsc0 = &gsc_0;
41 gsc1 = &gsc_1;
42 spi0 = &spi_0;
43 spi1 = &spi_1;
44 spi2 = &spi_2;
45 usbdrdphy0 = &usbdrd_phy0;
46 usbdrdphy1 = &usbdrd_phy1;
47 };
48
49 /*
50 * The 'cpus' node is not present here but instead it is provided
51 * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.
52 */
53
54 soc: soc {
55 cluster_a15_opp_table: opp_table0 {
56 compatible = "operating-points-v2";
57 opp-shared;
58 opp@1800000000 {
59 opp-hz = /bits/ 64 <1800000000>;
60 opp-microvolt = <1250000>;
61 clock-latency-ns = <140000>;
62 };
63 opp@1700000000 {
64 opp-hz = /bits/ 64 <1700000000>;
65 opp-microvolt = <1212500>;
66 clock-latency-ns = <140000>;
67 };
68 opp@1600000000 {
69 opp-hz = /bits/ 64 <1600000000>;
70 opp-microvolt = <1175000>;
71 clock-latency-ns = <140000>;
72 };
73 opp@1500000000 {
74 opp-hz = /bits/ 64 <1500000000>;
75 opp-microvolt = <1137500>;
76 clock-latency-ns = <140000>;
77 };
78 opp@1400000000 {
79 opp-hz = /bits/ 64 <1400000000>;
80 opp-microvolt = <1112500>;
81 clock-latency-ns = <140000>;
82 };
83 opp@1300000000 {
84 opp-hz = /bits/ 64 <1300000000>;
85 opp-microvolt = <1062500>;
86 clock-latency-ns = <140000>;
87 };
88 opp@1200000000 {
89 opp-hz = /bits/ 64 <1200000000>;
90 opp-microvolt = <1037500>;
91 clock-latency-ns = <140000>;
92 };
93 opp@1100000000 {
94 opp-hz = /bits/ 64 <1100000000>;
95 opp-microvolt = <1012500>;
96 clock-latency-ns = <140000>;
97 };
98 opp@1000000000 {
99 opp-hz = /bits/ 64 <1000000000>;
100 opp-microvolt = < 987500>;
101 clock-latency-ns = <140000>;
102 };
103 opp@900000000 {
104 opp-hz = /bits/ 64 <900000000>;
105 opp-microvolt = < 962500>;
106 clock-latency-ns = <140000>;
107 };
108 opp@800000000 {
109 opp-hz = /bits/ 64 <800000000>;
110 opp-microvolt = < 937500>;
111 clock-latency-ns = <140000>;
112 };
113 opp@700000000 {
114 opp-hz = /bits/ 64 <700000000>;
115 opp-microvolt = < 912500>;
116 clock-latency-ns = <140000>;
117 };
118 };
119
120 cluster_a7_opp_table: opp_table1 {
121 compatible = "operating-points-v2";
122 opp-shared;
123 opp@1300000000 {
124 opp-hz = /bits/ 64 <1300000000>;
125 opp-microvolt = <1275000>;
126 clock-latency-ns = <140000>;
127 };
128 opp@1200000000 {
129 opp-hz = /bits/ 64 <1200000000>;
130 opp-microvolt = <1212500>;
131 clock-latency-ns = <140000>;
132 };
133 opp@1100000000 {
134 opp-hz = /bits/ 64 <1100000000>;
135 opp-microvolt = <1162500>;
136 clock-latency-ns = <140000>;
137 };
138 opp@1000000000 {
139 opp-hz = /bits/ 64 <1000000000>;
140 opp-microvolt = <1112500>;
141 clock-latency-ns = <140000>;
142 };
143 opp@900000000 {
144 opp-hz = /bits/ 64 <900000000>;
145 opp-microvolt = <1062500>;
146 clock-latency-ns = <140000>;
147 };
148 opp@800000000 {
149 opp-hz = /bits/ 64 <800000000>;
150 opp-microvolt = <1025000>;
151 clock-latency-ns = <140000>;
152 };
153 opp@700000000 {
154 opp-hz = /bits/ 64 <700000000>;
155 opp-microvolt = <975000>;
156 clock-latency-ns = <140000>;
157 };
158 opp@600000000 {
159 opp-hz = /bits/ 64 <600000000>;
160 opp-microvolt = <937500>;
161 clock-latency-ns = <140000>;
162 };
163 };
164
165 cci: cci@10d20000 {
166 compatible = "arm,cci-400";
167 #address-cells = <1>;
168 #size-cells = <1>;
169 reg = <0x10d20000 0x1000>;
170 ranges = <0x0 0x10d20000 0x6000>;
171
172 cci_control0: slave-if@4000 {
173 compatible = "arm,cci-400-ctrl-if";
174 interface-type = "ace";
175 reg = <0x4000 0x1000>;
176 };
177 cci_control1: slave-if@5000 {
178 compatible = "arm,cci-400-ctrl-if";
179 interface-type = "ace";
180 reg = <0x5000 0x1000>;
181 };
182 };
183
184 sysram@02020000 {
185 compatible = "mmio-sram";
186 reg = <0x02020000 0x54000>;
187 #address-cells = <1>;
188 #size-cells = <1>;
189 ranges = <0 0x02020000 0x54000>;
190
191 smp-sysram@0 {
192 compatible = "samsung,exynos4210-sysram";
193 reg = <0x0 0x1000>;
194 };
195
196 smp-sysram@53000 {
197 compatible = "samsung,exynos4210-sysram-ns";
198 reg = <0x53000 0x1000>;
199 };
200 };
201
202 clock: clock-controller@10010000 {
203 compatible = "samsung,exynos5420-clock";
204 reg = <0x10010000 0x30000>;
205 #clock-cells = <1>;
206 };
207
208 clock_audss: audss-clock-controller@3810000 {
209 compatible = "samsung,exynos5420-audss-clock";
210 reg = <0x03810000 0x0C>;
211 #clock-cells = <1>;
212 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
213 <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
214 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
215 };
216
217 mfc: codec@11000000 {
218 compatible = "samsung,mfc-v7";
219 reg = <0x11000000 0x10000>;
220 interrupts = <0 96 0>;
221 clocks = <&clock CLK_MFC>;
222 clock-names = "mfc";
223 power-domains = <&mfc_pd>;
224 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
225 iommu-names = "left", "right";
226 };
227
228 mmc_0: mmc@12200000 {
229 compatible = "samsung,exynos5420-dw-mshc-smu";
230 interrupts = <0 75 0>;
231 #address-cells = <1>;
232 #size-cells = <0>;
233 reg = <0x12200000 0x2000>;
234 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
235 clock-names = "biu", "ciu";
236 fifo-depth = <0x40>;
237 status = "disabled";
238 };
239
240 mmc_1: mmc@12210000 {
241 compatible = "samsung,exynos5420-dw-mshc-smu";
242 interrupts = <0 76 0>;
243 #address-cells = <1>;
244 #size-cells = <0>;
245 reg = <0x12210000 0x2000>;
246 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
247 clock-names = "biu", "ciu";
248 fifo-depth = <0x40>;
249 status = "disabled";
250 };
251
252 mmc_2: mmc@12220000 {
253 compatible = "samsung,exynos5420-dw-mshc";
254 interrupts = <0 77 0>;
255 #address-cells = <1>;
256 #size-cells = <0>;
257 reg = <0x12220000 0x1000>;
258 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
259 clock-names = "biu", "ciu";
260 fifo-depth = <0x40>;
261 status = "disabled";
262 };
263
264 mct: mct@101C0000 {
265 compatible = "samsung,exynos4210-mct";
266 reg = <0x101C0000 0x800>;
267 interrupt-controller;
268 #interrupt-cells = <1>;
269 interrupt-parent = <&mct_map>;
270 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
271 <8>, <9>, <10>, <11>;
272 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
273 clock-names = "fin_pll", "mct";
274
275 mct_map: mct-map {
276 #interrupt-cells = <1>;
277 #address-cells = <0>;
278 #size-cells = <0>;
279 interrupt-map = <0 &combiner 23 3>,
280 <1 &combiner 23 4>,
281 <2 &combiner 25 2>,
282 <3 &combiner 25 3>,
283 <4 &gic 0 120 0>,
284 <5 &gic 0 121 0>,
285 <6 &gic 0 122 0>,
286 <7 &gic 0 123 0>,
287 <8 &gic 0 128 0>,
288 <9 &gic 0 129 0>,
289 <10 &gic 0 130 0>,
290 <11 &gic 0 131 0>;
291 };
292 };
293
294 nocp_mem0_0: nocp@10CA1000 {
295 compatible = "samsung,exynos5420-nocp";
296 reg = <0x10CA1000 0x200>;
297 status = "disabled";
298 };
299
300 nocp_mem0_1: nocp@10CA1400 {
301 compatible = "samsung,exynos5420-nocp";
302 reg = <0x10CA1400 0x200>;
303 status = "disabled";
304 };
305
306 nocp_mem1_0: nocp@10CA1800 {
307 compatible = "samsung,exynos5420-nocp";
308 reg = <0x10CA1800 0x200>;
309 status = "disabled";
310 };
311
312 nocp_mem1_1: nocp@10CA1C00 {
313 compatible = "samsung,exynos5420-nocp";
314 reg = <0x10CA1C00 0x200>;
315 status = "disabled";
316 };
317
318 nocp_g3d_0: nocp@11A51000 {
319 compatible = "samsung,exynos5420-nocp";
320 reg = <0x11A51000 0x200>;
321 status = "disabled";
322 };
323
324 nocp_g3d_1: nocp@11A51400 {
325 compatible = "samsung,exynos5420-nocp";
326 reg = <0x11A51400 0x200>;
327 status = "disabled";
328 };
329
330 gsc_pd: power-domain@10044000 {
331 compatible = "samsung,exynos4210-pd";
332 reg = <0x10044000 0x20>;
333 #power-domain-cells = <0>;
334 clocks = <&clock CLK_FIN_PLL>,
335 <&clock CLK_MOUT_USER_ACLK300_GSCL>,
336 <&clock CLK_GSCL0>, <&clock CLK_GSCL1>;
337 clock-names = "oscclk", "clk0", "asb0", "asb1";
338 };
339
340 isp_pd: power-domain@10044020 {
341 compatible = "samsung,exynos4210-pd";
342 reg = <0x10044020 0x20>;
343 #power-domain-cells = <0>;
344 };
345
346 mfc_pd: power-domain@10044060 {
347 compatible = "samsung,exynos4210-pd";
348 reg = <0x10044060 0x20>;
349 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>;
350 clock-names = "oscclk", "clk0";
351 #power-domain-cells = <0>;
352 };
353
354 msc_pd: power-domain@10044120 {
355 compatible = "samsung,exynos4210-pd";
356 reg = <0x10044120 0x20>;
357 #power-domain-cells = <0>;
358 };
359
360 disp_pd: power-domain@100440C0 {
361 compatible = "samsung,exynos4210-pd";
362 reg = <0x100440C0 0x20>;
363 #power-domain-cells = <0>;
364 clocks = <&clock CLK_FIN_PLL>,
365 <&clock CLK_MOUT_USER_ACLK200_DISP1>,
366 <&clock CLK_MOUT_USER_ACLK300_DISP1>,
367 <&clock CLK_MOUT_USER_ACLK400_DISP1>,
368 <&clock CLK_FIMD1>, <&clock CLK_MIXER>;
369 clock-names = "oscclk", "clk0", "clk1", "clk2", "asb0", "asb1";
370 };
371
372 pinctrl_0: pinctrl@13400000 {
373 compatible = "samsung,exynos5420-pinctrl";
374 reg = <0x13400000 0x1000>;
375 interrupts = <0 45 0>;
376
377 wakeup-interrupt-controller {
378 compatible = "samsung,exynos4210-wakeup-eint";
379 interrupt-parent = <&gic>;
380 interrupts = <0 32 0>;
381 };
382 };
383
384 pinctrl_1: pinctrl@13410000 {
385 compatible = "samsung,exynos5420-pinctrl";
386 reg = <0x13410000 0x1000>;
387 interrupts = <0 78 0>;
388 };
389
390 pinctrl_2: pinctrl@14000000 {
391 compatible = "samsung,exynos5420-pinctrl";
392 reg = <0x14000000 0x1000>;
393 interrupts = <0 46 0>;
394 };
395
396 pinctrl_3: pinctrl@14010000 {
397 compatible = "samsung,exynos5420-pinctrl";
398 reg = <0x14010000 0x1000>;
399 interrupts = <0 50 0>;
400 };
401
402 pinctrl_4: pinctrl@03860000 {
403 compatible = "samsung,exynos5420-pinctrl";
404 reg = <0x03860000 0x1000>;
405 interrupts = <0 47 0>;
406 };
407
408 amba {
409 #address-cells = <1>;
410 #size-cells = <1>;
411 compatible = "simple-bus";
412 interrupt-parent = <&gic>;
413 ranges;
414
415 adma: adma@03880000 {
416 compatible = "arm,pl330", "arm,primecell";
417 reg = <0x03880000 0x1000>;
418 interrupts = <0 110 0>;
419 clocks = <&clock_audss EXYNOS_ADMA>;
420 clock-names = "apb_pclk";
421 #dma-cells = <1>;
422 #dma-channels = <6>;
423 #dma-requests = <16>;
424 };
425
426 pdma0: pdma@121A0000 {
427 compatible = "arm,pl330", "arm,primecell";
428 reg = <0x121A0000 0x1000>;
429 interrupts = <0 34 0>;
430 clocks = <&clock CLK_PDMA0>;
431 clock-names = "apb_pclk";
432 #dma-cells = <1>;
433 #dma-channels = <8>;
434 #dma-requests = <32>;
435 };
436
437 pdma1: pdma@121B0000 {
438 compatible = "arm,pl330", "arm,primecell";
439 reg = <0x121B0000 0x1000>;
440 interrupts = <0 35 0>;
441 clocks = <&clock CLK_PDMA1>;
442 clock-names = "apb_pclk";
443 #dma-cells = <1>;
444 #dma-channels = <8>;
445 #dma-requests = <32>;
446 };
447
448 mdma0: mdma@10800000 {
449 compatible = "arm,pl330", "arm,primecell";
450 reg = <0x10800000 0x1000>;
451 interrupts = <0 33 0>;
452 clocks = <&clock CLK_MDMA0>;
453 clock-names = "apb_pclk";
454 #dma-cells = <1>;
455 #dma-channels = <8>;
456 #dma-requests = <1>;
457 };
458
459 mdma1: mdma@11C10000 {
460 compatible = "arm,pl330", "arm,primecell";
461 reg = <0x11C10000 0x1000>;
462 interrupts = <0 124 0>;
463 clocks = <&clock CLK_MDMA1>;
464 clock-names = "apb_pclk";
465 #dma-cells = <1>;
466 #dma-channels = <8>;
467 #dma-requests = <1>;
468 /*
469 * MDMA1 can support both secure and non-secure
470 * AXI transactions. When this is enabled in
471 * the kernel for boards that run in secure
472 * mode, we are getting imprecise external
473 * aborts causing the kernel to oops.
474 */
475 status = "disabled";
476 };
477 };
478
479 i2s0: i2s@03830000 {
480 compatible = "samsung,exynos5420-i2s";
481 reg = <0x03830000 0x100>;
482 dmas = <&adma 0
483 &adma 2
484 &adma 1>;
485 dma-names = "tx", "rx", "tx-sec";
486 clocks = <&clock_audss EXYNOS_I2S_BUS>,
487 <&clock_audss EXYNOS_I2S_BUS>,
488 <&clock_audss EXYNOS_SCLK_I2S>;
489 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
490 #clock-cells = <1>;
491 clock-output-names = "i2s_cdclk0";
492 #sound-dai-cells = <1>;
493 samsung,idma-addr = <0x03000000>;
494 pinctrl-names = "default";
495 pinctrl-0 = <&i2s0_bus>;
496 status = "disabled";
497 };
498
499 i2s1: i2s@12D60000 {
500 compatible = "samsung,exynos5420-i2s";
501 reg = <0x12D60000 0x100>;
502 dmas = <&pdma1 12
503 &pdma1 11>;
504 dma-names = "tx", "rx";
505 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
506 clock-names = "iis", "i2s_opclk0";
507 #clock-cells = <1>;
508 clock-output-names = "i2s_cdclk1";
509 #sound-dai-cells = <1>;
510 pinctrl-names = "default";
511 pinctrl-0 = <&i2s1_bus>;
512 status = "disabled";
513 };
514
515 i2s2: i2s@12D70000 {
516 compatible = "samsung,exynos5420-i2s";
517 reg = <0x12D70000 0x100>;
518 dmas = <&pdma0 12
519 &pdma0 11>;
520 dma-names = "tx", "rx";
521 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
522 clock-names = "iis", "i2s_opclk0";
523 #clock-cells = <1>;
524 clock-output-names = "i2s_cdclk2";
525 #sound-dai-cells = <1>;
526 pinctrl-names = "default";
527 pinctrl-0 = <&i2s2_bus>;
528 status = "disabled";
529 };
530
531 spi_0: spi@12d20000 {
532 compatible = "samsung,exynos4210-spi";
533 reg = <0x12d20000 0x100>;
534 interrupts = <0 68 0>;
535 dmas = <&pdma0 5
536 &pdma0 4>;
537 dma-names = "tx", "rx";
538 #address-cells = <1>;
539 #size-cells = <0>;
540 pinctrl-names = "default";
541 pinctrl-0 = <&spi0_bus>;
542 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
543 clock-names = "spi", "spi_busclk0";
544 status = "disabled";
545 };
546
547 spi_1: spi@12d30000 {
548 compatible = "samsung,exynos4210-spi";
549 reg = <0x12d30000 0x100>;
550 interrupts = <0 69 0>;
551 dmas = <&pdma1 5
552 &pdma1 4>;
553 dma-names = "tx", "rx";
554 #address-cells = <1>;
555 #size-cells = <0>;
556 pinctrl-names = "default";
557 pinctrl-0 = <&spi1_bus>;
558 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
559 clock-names = "spi", "spi_busclk0";
560 status = "disabled";
561 };
562
563 spi_2: spi@12d40000 {
564 compatible = "samsung,exynos4210-spi";
565 reg = <0x12d40000 0x100>;
566 interrupts = <0 70 0>;
567 dmas = <&pdma0 7
568 &pdma0 6>;
569 dma-names = "tx", "rx";
570 #address-cells = <1>;
571 #size-cells = <0>;
572 pinctrl-names = "default";
573 pinctrl-0 = <&spi2_bus>;
574 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
575 clock-names = "spi", "spi_busclk0";
576 status = "disabled";
577 };
578
579 dp_phy: dp-video-phy {
580 compatible = "samsung,exynos5420-dp-video-phy";
581 samsung,pmu-syscon = <&pmu_system_controller>;
582 #phy-cells = <0>;
583 };
584
585 mipi_phy: mipi-video-phy {
586 compatible = "samsung,s5pv210-mipi-video-phy";
587 syscon = <&pmu_system_controller>;
588 #phy-cells = <1>;
589 };
590
591 dsi@14500000 {
592 compatible = "samsung,exynos5410-mipi-dsi";
593 reg = <0x14500000 0x10000>;
594 interrupts = <0 82 0>;
595 phys = <&mipi_phy 1>;
596 phy-names = "dsim";
597 clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
598 clock-names = "bus_clk", "pll_clk";
599 #address-cells = <1>;
600 #size-cells = <0>;
601 status = "disabled";
602 };
603
604 adc: adc@12D10000 {
605 compatible = "samsung,exynos-adc-v2";
606 reg = <0x12D10000 0x100>;
607 interrupts = <0 106 0>;
608 clocks = <&clock CLK_TSADC>;
609 clock-names = "adc";
610 #io-channel-cells = <1>;
611 io-channel-ranges;
612 samsung,syscon-phandle = <&pmu_system_controller>;
613 status = "disabled";
614 };
615
616 /* i2c_0-3 are defined in exynos5.dtsi */
617 hsi2c_4: i2c@12CA0000 {
618 compatible = "samsung,exynos5250-hsi2c";
619 reg = <0x12CA0000 0x1000>;
620 interrupts = <0 60 0>;
621 #address-cells = <1>;
622 #size-cells = <0>;
623 pinctrl-names = "default";
624 pinctrl-0 = <&i2c4_hs_bus>;
625 clocks = <&clock CLK_USI0>;
626 clock-names = "hsi2c";
627 status = "disabled";
628 };
629
630 hsi2c_5: i2c@12CB0000 {
631 compatible = "samsung,exynos5250-hsi2c";
632 reg = <0x12CB0000 0x1000>;
633 interrupts = <0 61 0>;
634 #address-cells = <1>;
635 #size-cells = <0>;
636 pinctrl-names = "default";
637 pinctrl-0 = <&i2c5_hs_bus>;
638 clocks = <&clock CLK_USI1>;
639 clock-names = "hsi2c";
640 status = "disabled";
641 };
642
643 hsi2c_6: i2c@12CC0000 {
644 compatible = "samsung,exynos5250-hsi2c";
645 reg = <0x12CC0000 0x1000>;
646 interrupts = <0 62 0>;
647 #address-cells = <1>;
648 #size-cells = <0>;
649 pinctrl-names = "default";
650 pinctrl-0 = <&i2c6_hs_bus>;
651 clocks = <&clock CLK_USI2>;
652 clock-names = "hsi2c";
653 status = "disabled";
654 };
655
656 hsi2c_7: i2c@12CD0000 {
657 compatible = "samsung,exynos5250-hsi2c";
658 reg = <0x12CD0000 0x1000>;
659 interrupts = <0 63 0>;
660 #address-cells = <1>;
661 #size-cells = <0>;
662 pinctrl-names = "default";
663 pinctrl-0 = <&i2c7_hs_bus>;
664 clocks = <&clock CLK_USI3>;
665 clock-names = "hsi2c";
666 status = "disabled";
667 };
668
669 hsi2c_8: i2c@12E00000 {
670 compatible = "samsung,exynos5250-hsi2c";
671 reg = <0x12E00000 0x1000>;
672 interrupts = <0 87 0>;
673 #address-cells = <1>;
674 #size-cells = <0>;
675 pinctrl-names = "default";
676 pinctrl-0 = <&i2c8_hs_bus>;
677 clocks = <&clock CLK_USI4>;
678 clock-names = "hsi2c";
679 status = "disabled";
680 };
681
682 hsi2c_9: i2c@12E10000 {
683 compatible = "samsung,exynos5250-hsi2c";
684 reg = <0x12E10000 0x1000>;
685 interrupts = <0 88 0>;
686 #address-cells = <1>;
687 #size-cells = <0>;
688 pinctrl-names = "default";
689 pinctrl-0 = <&i2c9_hs_bus>;
690 clocks = <&clock CLK_USI5>;
691 clock-names = "hsi2c";
692 status = "disabled";
693 };
694
695 hsi2c_10: i2c@12E20000 {
696 compatible = "samsung,exynos5250-hsi2c";
697 reg = <0x12E20000 0x1000>;
698 interrupts = <0 203 0>;
699 #address-cells = <1>;
700 #size-cells = <0>;
701 pinctrl-names = "default";
702 pinctrl-0 = <&i2c10_hs_bus>;
703 clocks = <&clock CLK_USI6>;
704 clock-names = "hsi2c";
705 status = "disabled";
706 };
707
708 hdmi: hdmi@14530000 {
709 compatible = "samsung,exynos5420-hdmi";
710 reg = <0x14530000 0x70000>;
711 interrupts = <0 95 0>;
712 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
713 <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
714 <&clock CLK_MOUT_HDMI>;
715 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
716 "sclk_hdmiphy", "mout_hdmi";
717 phy = <&hdmiphy>;
718 samsung,syscon-phandle = <&pmu_system_controller>;
719 status = "disabled";
720 power-domains = <&disp_pd>;
721 };
722
723 hdmiphy: hdmiphy@145D0000 {
724 reg = <0x145D0000 0x20>;
725 };
726
727 mixer: mixer@14450000 {
728 compatible = "samsung,exynos5420-mixer";
729 reg = <0x14450000 0x10000>;
730 interrupts = <0 94 0>;
731 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
732 <&clock CLK_SCLK_HDMI>;
733 clock-names = "mixer", "hdmi", "sclk_hdmi";
734 power-domains = <&disp_pd>;
735 iommus = <&sysmmu_tv>;
736 };
737
738 rotator: rotator@11C00000 {
739 compatible = "samsung,exynos5250-rotator";
740 reg = <0x11C00000 0x64>;
741 interrupts = <0 84 0>;
742 clocks = <&clock CLK_ROTATOR>;
743 clock-names = "rotator";
744 iommus = <&sysmmu_rotator>;
745 };
746
747 gsc_0: video-scaler@13e00000 {
748 compatible = "samsung,exynos5-gsc";
749 reg = <0x13e00000 0x1000>;
750 interrupts = <0 85 0>;
751 clocks = <&clock CLK_GSCL0>;
752 clock-names = "gscl";
753 power-domains = <&gsc_pd>;
754 iommus = <&sysmmu_gscl0>;
755 };
756
757 gsc_1: video-scaler@13e10000 {
758 compatible = "samsung,exynos5-gsc";
759 reg = <0x13e10000 0x1000>;
760 interrupts = <0 86 0>;
761 clocks = <&clock CLK_GSCL1>;
762 clock-names = "gscl";
763 power-domains = <&gsc_pd>;
764 iommus = <&sysmmu_gscl1>;
765 };
766
767 jpeg_0: jpeg@11F50000 {
768 compatible = "samsung,exynos5420-jpeg";
769 reg = <0x11F50000 0x1000>;
770 interrupts = <0 89 0>;
771 clock-names = "jpeg";
772 clocks = <&clock CLK_JPEG>;
773 iommus = <&sysmmu_jpeg0>;
774 };
775
776 jpeg_1: jpeg@11F60000 {
777 compatible = "samsung,exynos5420-jpeg";
778 reg = <0x11F60000 0x1000>;
779 interrupts = <0 168 0>;
780 clock-names = "jpeg";
781 clocks = <&clock CLK_JPEG2>;
782 iommus = <&sysmmu_jpeg1>;
783 };
784
785 pmu_system_controller: system-controller@10040000 {
786 compatible = "samsung,exynos5420-pmu", "syscon";
787 reg = <0x10040000 0x5000>;
788 clock-names = "clkout16";
789 clocks = <&clock CLK_FIN_PLL>;
790 #clock-cells = <1>;
791 interrupt-controller;
792 #interrupt-cells = <3>;
793 interrupt-parent = <&gic>;
794 };
795
796 tmu_cpu0: tmu@10060000 {
797 compatible = "samsung,exynos5420-tmu";
798 reg = <0x10060000 0x100>;
799 interrupts = <0 65 0>;
800 clocks = <&clock CLK_TMU>;
801 clock-names = "tmu_apbif";
802 #include "exynos4412-tmu-sensor-conf.dtsi"
803 };
804
805 tmu_cpu1: tmu@10064000 {
806 compatible = "samsung,exynos5420-tmu";
807 reg = <0x10064000 0x100>;
808 interrupts = <0 183 0>;
809 clocks = <&clock CLK_TMU>;
810 clock-names = "tmu_apbif";
811 #include "exynos4412-tmu-sensor-conf.dtsi"
812 };
813
814 tmu_cpu2: tmu@10068000 {
815 compatible = "samsung,exynos5420-tmu-ext-triminfo";
816 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
817 interrupts = <0 184 0>;
818 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
819 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
820 #include "exynos4412-tmu-sensor-conf.dtsi"
821 };
822
823 tmu_cpu3: tmu@1006c000 {
824 compatible = "samsung,exynos5420-tmu-ext-triminfo";
825 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
826 interrupts = <0 185 0>;
827 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
828 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
829 #include "exynos4412-tmu-sensor-conf.dtsi"
830 };
831
832 tmu_gpu: tmu@100a0000 {
833 compatible = "samsung,exynos5420-tmu-ext-triminfo";
834 reg = <0x100a0000 0x100>, <0x10068000 0x4>;
835 interrupts = <0 215 0>;
836 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
837 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
838 #include "exynos4412-tmu-sensor-conf.dtsi"
839 };
840
841 watchdog: watchdog@101D0000 {
842 compatible = "samsung,exynos5420-wdt";
843 reg = <0x101D0000 0x100>;
844 interrupts = <0 42 0>;
845 clocks = <&clock CLK_WDT>;
846 clock-names = "watchdog";
847 samsung,syscon-phandle = <&pmu_system_controller>;
848 };
849
850 sss: sss@10830000 {
851 compatible = "samsung,exynos4210-secss";
852 reg = <0x10830000 0x300>;
853 interrupts = <0 112 0>;
854 clocks = <&clock CLK_SSS>;
855 clock-names = "secss";
856 };
857
858 usbdrd3_0: usb3-0 {
859 compatible = "samsung,exynos5250-dwusb3";
860 clocks = <&clock CLK_USBD300>;
861 clock-names = "usbdrd30";
862 #address-cells = <1>;
863 #size-cells = <1>;
864 ranges;
865
866 usbdrd_dwc3_0: dwc3@12000000 {
867 compatible = "snps,dwc3";
868 reg = <0x12000000 0x10000>;
869 interrupts = <0 72 0>;
870 phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
871 phy-names = "usb2-phy", "usb3-phy";
872 };
873 };
874
875 usbdrd_phy0: phy@12100000 {
876 compatible = "samsung,exynos5420-usbdrd-phy";
877 reg = <0x12100000 0x100>;
878 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
879 clock-names = "phy", "ref";
880 samsung,pmu-syscon = <&pmu_system_controller>;
881 #phy-cells = <1>;
882 };
883
884 usbdrd3_1: usb3-1 {
885 compatible = "samsung,exynos5250-dwusb3";
886 clocks = <&clock CLK_USBD301>;
887 clock-names = "usbdrd30";
888 #address-cells = <1>;
889 #size-cells = <1>;
890 ranges;
891
892 usbdrd_dwc3_1: dwc3@12400000 {
893 compatible = "snps,dwc3";
894 reg = <0x12400000 0x10000>;
895 interrupts = <0 73 0>;
896 phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
897 phy-names = "usb2-phy", "usb3-phy";
898 };
899 };
900
901 usbdrd_phy1: phy@12500000 {
902 compatible = "samsung,exynos5420-usbdrd-phy";
903 reg = <0x12500000 0x100>;
904 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
905 clock-names = "phy", "ref";
906 samsung,pmu-syscon = <&pmu_system_controller>;
907 #phy-cells = <1>;
908 };
909
910 usbhost2: usb@12110000 {
911 compatible = "samsung,exynos4210-ehci";
912 reg = <0x12110000 0x100>;
913 interrupts = <0 71 0>;
914
915 clocks = <&clock CLK_USBH20>;
916 clock-names = "usbhost";
917 #address-cells = <1>;
918 #size-cells = <0>;
919 port@0 {
920 reg = <0>;
921 phys = <&usb2_phy 1>;
922 };
923 };
924
925 usbhost1: usb@12120000 {
926 compatible = "samsung,exynos4210-ohci";
927 reg = <0x12120000 0x100>;
928 interrupts = <0 71 0>;
929
930 clocks = <&clock CLK_USBH20>;
931 clock-names = "usbhost";
932 #address-cells = <1>;
933 #size-cells = <0>;
934 port@0 {
935 reg = <0>;
936 phys = <&usb2_phy 1>;
937 };
938 };
939
940 usb2_phy: phy@12130000 {
941 compatible = "samsung,exynos5250-usb2-phy";
942 reg = <0x12130000 0x100>;
943 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
944 clock-names = "phy", "ref";
945 #phy-cells = <1>;
946 samsung,sysreg-phandle = <&sysreg_system_controller>;
947 samsung,pmureg-phandle = <&pmu_system_controller>;
948 };
949
950 sysmmu_g2dr: sysmmu@0x10A60000 {
951 compatible = "samsung,exynos-sysmmu";
952 reg = <0x10A60000 0x1000>;
953 interrupt-parent = <&combiner>;
954 interrupts = <24 5>;
955 clock-names = "sysmmu", "master";
956 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
957 #iommu-cells = <0>;
958 };
959
960 sysmmu_g2dw: sysmmu@0x10A70000 {
961 compatible = "samsung,exynos-sysmmu";
962 reg = <0x10A70000 0x1000>;
963 interrupt-parent = <&combiner>;
964 interrupts = <22 2>;
965 clock-names = "sysmmu", "master";
966 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
967 #iommu-cells = <0>;
968 };
969
970 sysmmu_tv: sysmmu@0x14650000 {
971 compatible = "samsung,exynos-sysmmu";
972 reg = <0x14650000 0x1000>;
973 interrupt-parent = <&combiner>;
974 interrupts = <7 4>;
975 clock-names = "sysmmu", "master";
976 clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>;
977 power-domains = <&disp_pd>;
978 #iommu-cells = <0>;
979 };
980
981 sysmmu_gscl0: sysmmu@0x13E80000 {
982 compatible = "samsung,exynos-sysmmu";
983 reg = <0x13E80000 0x1000>;
984 interrupt-parent = <&combiner>;
985 interrupts = <2 0>;
986 clock-names = "sysmmu", "master";
987 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
988 power-domains = <&gsc_pd>;
989 #iommu-cells = <0>;
990 };
991
992 sysmmu_gscl1: sysmmu@0x13E90000 {
993 compatible = "samsung,exynos-sysmmu";
994 reg = <0x13E90000 0x1000>;
995 interrupt-parent = <&combiner>;
996 interrupts = <2 2>;
997 clock-names = "sysmmu", "master";
998 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
999 power-domains = <&gsc_pd>;
1000 #iommu-cells = <0>;
1001 };
1002
1003 sysmmu_scaler0r: sysmmu@0x12880000 {
1004 compatible = "samsung,exynos-sysmmu";
1005 reg = <0x12880000 0x1000>;
1006 interrupt-parent = <&combiner>;
1007 interrupts = <22 4>;
1008 clock-names = "sysmmu", "master";
1009 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
1010 #iommu-cells = <0>;
1011 };
1012
1013 sysmmu_scaler1r: sysmmu@0x12890000 {
1014 compatible = "samsung,exynos-sysmmu";
1015 reg = <0x12890000 0x1000>;
1016 interrupts = <0 186 0>;
1017 clock-names = "sysmmu", "master";
1018 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
1019 #iommu-cells = <0>;
1020 };
1021
1022 sysmmu_scaler2r: sysmmu@0x128A0000 {
1023 compatible = "samsung,exynos-sysmmu";
1024 reg = <0x128A0000 0x1000>;
1025 interrupts = <0 188 0>;
1026 clock-names = "sysmmu", "master";
1027 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
1028 #iommu-cells = <0>;
1029 };
1030
1031 sysmmu_scaler0w: sysmmu@0x128C0000 {
1032 compatible = "samsung,exynos-sysmmu";
1033 reg = <0x128C0000 0x1000>;
1034 interrupt-parent = <&combiner>;
1035 interrupts = <27 2>;
1036 clock-names = "sysmmu", "master";
1037 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
1038 #iommu-cells = <0>;
1039 };
1040
1041 sysmmu_scaler1w: sysmmu@0x128D0000 {
1042 compatible = "samsung,exynos-sysmmu";
1043 reg = <0x128D0000 0x1000>;
1044 interrupt-parent = <&combiner>;
1045 interrupts = <22 6>;
1046 clock-names = "sysmmu", "master";
1047 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
1048 #iommu-cells = <0>;
1049 };
1050
1051 sysmmu_scaler2w: sysmmu@0x128E0000 {
1052 compatible = "samsung,exynos-sysmmu";
1053 reg = <0x128E0000 0x1000>;
1054 interrupt-parent = <&combiner>;
1055 interrupts = <19 6>;
1056 clock-names = "sysmmu", "master";
1057 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
1058 #iommu-cells = <0>;
1059 };
1060
1061 sysmmu_rotator: sysmmu@0x11D40000 {
1062 compatible = "samsung,exynos-sysmmu";
1063 reg = <0x11D40000 0x1000>;
1064 interrupt-parent = <&combiner>;
1065 interrupts = <4 0>;
1066 clock-names = "sysmmu", "master";
1067 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
1068 #iommu-cells = <0>;
1069 };
1070
1071 sysmmu_jpeg0: sysmmu@0x11F10000 {
1072 compatible = "samsung,exynos-sysmmu";
1073 reg = <0x11F10000 0x1000>;
1074 interrupt-parent = <&combiner>;
1075 interrupts = <4 2>;
1076 clock-names = "sysmmu", "master";
1077 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
1078 #iommu-cells = <0>;
1079 };
1080
1081 sysmmu_jpeg1: sysmmu@0x11F20000 {
1082 compatible = "samsung,exynos-sysmmu";
1083 reg = <0x11F20000 0x1000>;
1084 interrupts = <0 169 0>;
1085 clock-names = "sysmmu", "master";
1086 clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>;
1087 #iommu-cells = <0>;
1088 };
1089
1090 sysmmu_mfc_l: sysmmu@0x11200000 {
1091 compatible = "samsung,exynos-sysmmu";
1092 reg = <0x11200000 0x1000>;
1093 interrupt-parent = <&combiner>;
1094 interrupts = <6 2>;
1095 clock-names = "sysmmu", "master";
1096 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
1097 power-domains = <&mfc_pd>;
1098 #iommu-cells = <0>;
1099 };
1100
1101 sysmmu_mfc_r: sysmmu@0x11210000 {
1102 compatible = "samsung,exynos-sysmmu";
1103 reg = <0x11210000 0x1000>;
1104 interrupt-parent = <&combiner>;
1105 interrupts = <8 5>;
1106 clock-names = "sysmmu", "master";
1107 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
1108 power-domains = <&mfc_pd>;
1109 #iommu-cells = <0>;
1110 };
1111
1112 sysmmu_fimd1_0: sysmmu@0x14640000 {
1113 compatible = "samsung,exynos-sysmmu";
1114 reg = <0x14640000 0x1000>;
1115 interrupt-parent = <&combiner>;
1116 interrupts = <3 2>;
1117 clock-names = "sysmmu", "master";
1118 clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>;
1119 power-domains = <&disp_pd>;
1120 #iommu-cells = <0>;
1121 };
1122
1123 sysmmu_fimd1_1: sysmmu@0x14680000 {
1124 compatible = "samsung,exynos-sysmmu";
1125 reg = <0x14680000 0x1000>;
1126 interrupt-parent = <&combiner>;
1127 interrupts = <3 0>;
1128 clock-names = "sysmmu", "master";
1129 clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>;
1130 power-domains = <&disp_pd>;
1131 #iommu-cells = <0>;
1132 };
1133
1134 bus_wcore: bus_wcore {
1135 compatible = "samsung,exynos-bus";
1136 clocks = <&clock CLK_DOUT_ACLK400_WCORE>;
1137 clock-names = "bus";
1138 operating-points-v2 = <&bus_wcore_opp_table>;
1139 status = "disabled";
1140 };
1141
1142 bus_noc: bus_noc {
1143 compatible = "samsung,exynos-bus";
1144 clocks = <&clock CLK_DOUT_ACLK100_NOC>;
1145 clock-names = "bus";
1146 operating-points-v2 = <&bus_noc_opp_table>;
1147 status = "disabled";
1148 };
1149
1150 bus_fsys_apb: bus_fsys_apb {
1151 compatible = "samsung,exynos-bus";
1152 clocks = <&clock CLK_DOUT_PCLK200_FSYS>;
1153 clock-names = "bus";
1154 operating-points-v2 = <&bus_fsys_apb_opp_table>;
1155 status = "disabled";
1156 };
1157
1158 bus_fsys: bus_fsys {
1159 compatible = "samsung,exynos-bus";
1160 clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
1161 clock-names = "bus";
1162 operating-points-v2 = <&bus_fsys_apb_opp_table>;
1163 status = "disabled";
1164 };
1165
1166 bus_fsys2: bus_fsys2 {
1167 compatible = "samsung,exynos-bus";
1168 clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
1169 clock-names = "bus";
1170 operating-points-v2 = <&bus_fsys2_opp_table>;
1171 status = "disabled";
1172 };
1173
1174 bus_mfc: bus_mfc {
1175 compatible = "samsung,exynos-bus";
1176 clocks = <&clock CLK_DOUT_ACLK333>;
1177 clock-names = "bus";
1178 operating-points-v2 = <&bus_mfc_opp_table>;
1179 status = "disabled";
1180 };
1181
1182 bus_gen: bus_gen {
1183 compatible = "samsung,exynos-bus";
1184 clocks = <&clock CLK_DOUT_ACLK266>;
1185 clock-names = "bus";
1186 operating-points-v2 = <&bus_gen_opp_table>;
1187 status = "disabled";
1188 };
1189
1190 bus_peri: bus_peri {
1191 compatible = "samsung,exynos-bus";
1192 clocks = <&clock CLK_DOUT_ACLK66>;
1193 clock-names = "bus";
1194 operating-points-v2 = <&bus_peri_opp_table>;
1195 status = "disabled";
1196 };
1197
1198 bus_g2d: bus_g2d {
1199 compatible = "samsung,exynos-bus";
1200 clocks = <&clock CLK_DOUT_ACLK333_G2D>;
1201 clock-names = "bus";
1202 operating-points-v2 = <&bus_g2d_opp_table>;
1203 status = "disabled";
1204 };
1205
1206 bus_g2d_acp: bus_g2d_acp {
1207 compatible = "samsung,exynos-bus";
1208 clocks = <&clock CLK_DOUT_ACLK266_G2D>;
1209 clock-names = "bus";
1210 operating-points-v2 = <&bus_g2d_acp_opp_table>;
1211 status = "disabled";
1212 };
1213
1214 bus_jpeg: bus_jpeg {
1215 compatible = "samsung,exynos-bus";
1216 clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
1217 clock-names = "bus";
1218 operating-points-v2 = <&bus_jpeg_opp_table>;
1219 status = "disabled";
1220 };
1221
1222 bus_jpeg_apb: bus_jpeg_apb {
1223 compatible = "samsung,exynos-bus";
1224 clocks = <&clock CLK_DOUT_ACLK166>;
1225 clock-names = "bus";
1226 operating-points-v2 = <&bus_jpeg_apb_opp_table>;
1227 status = "disabled";
1228 };
1229
1230 bus_disp1_fimd: bus_disp1_fimd {
1231 compatible = "samsung,exynos-bus";
1232 clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
1233 clock-names = "bus";
1234 operating-points-v2 = <&bus_disp1_fimd_opp_table>;
1235 status = "disabled";
1236 };
1237
1238 bus_disp1: bus_disp1 {
1239 compatible = "samsung,exynos-bus";
1240 clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
1241 clock-names = "bus";
1242 operating-points-v2 = <&bus_disp1_opp_table>;
1243 status = "disabled";
1244 };
1245
1246 bus_gscl_scaler: bus_gscl_scaler {
1247 compatible = "samsung,exynos-bus";
1248 clocks = <&clock CLK_DOUT_ACLK300_GSCL>;
1249 clock-names = "bus";
1250 operating-points-v2 = <&bus_gscl_opp_table>;
1251 status = "disabled";
1252 };
1253
1254 bus_mscl: bus_mscl {
1255 compatible = "samsung,exynos-bus";
1256 clocks = <&clock CLK_DOUT_ACLK400_MSCL>;
1257 clock-names = "bus";
1258 operating-points-v2 = <&bus_mscl_opp_table>;
1259 status = "disabled";
1260 };
1261
1262 bus_wcore_opp_table: opp_table2 {
1263 compatible = "operating-points-v2";
1264
1265 opp00 {
1266 opp-hz = /bits/ 64 <84000000>;
1267 opp-microvolt = <925000>;
1268 };
1269 opp01 {
1270 opp-hz = /bits/ 64 <111000000>;
1271 opp-microvolt = <950000>;
1272 };
1273 opp02 {
1274 opp-hz = /bits/ 64 <222000000>;
1275 opp-microvolt = <950000>;
1276 };
1277 opp03 {
1278 opp-hz = /bits/ 64 <333000000>;
1279 opp-microvolt = <950000>;
1280 };
1281 opp04 {
1282 opp-hz = /bits/ 64 <400000000>;
1283 opp-microvolt = <987500>;
1284 };
1285 };
1286
1287 bus_noc_opp_table: opp_table3 {
1288 compatible = "operating-points-v2";
1289
1290 opp00 {
1291 opp-hz = /bits/ 64 <67000000>;
1292 };
1293 opp01 {
1294 opp-hz = /bits/ 64 <75000000>;
1295 };
1296 opp02 {
1297 opp-hz = /bits/ 64 <86000000>;
1298 };
1299 opp03 {
1300 opp-hz = /bits/ 64 <100000000>;
1301 };
1302 };
1303
1304 bus_fsys_apb_opp_table: opp_table4 {
1305 compatible = "operating-points-v2";
1306 opp-shared;
1307
1308 opp00 {
1309 opp-hz = /bits/ 64 <100000000>;
1310 };
1311 opp01 {
1312 opp-hz = /bits/ 64 <200000000>;
1313 };
1314 };
1315
1316 bus_fsys2_opp_table: opp_table5 {
1317 compatible = "operating-points-v2";
1318
1319 opp00 {
1320 opp-hz = /bits/ 64 <75000000>;
1321 };
1322 opp01 {
1323 opp-hz = /bits/ 64 <100000000>;
1324 };
1325 opp02 {
1326 opp-hz = /bits/ 64 <150000000>;
1327 };
1328 };
1329
1330 bus_mfc_opp_table: opp_table6 {
1331 compatible = "operating-points-v2";
1332
1333 opp00 {
1334 opp-hz = /bits/ 64 <96000000>;
1335 };
1336 opp01 {
1337 opp-hz = /bits/ 64 <111000000>;
1338 };
1339 opp02 {
1340 opp-hz = /bits/ 64 <167000000>;
1341 };
1342 opp03 {
1343 opp-hz = /bits/ 64 <222000000>;
1344 };
1345 opp04 {
1346 opp-hz = /bits/ 64 <333000000>;
1347 };
1348 };
1349
1350 bus_gen_opp_table: opp_table7 {
1351 compatible = "operating-points-v2";
1352
1353 opp00 {
1354 opp-hz = /bits/ 64 <89000000>;
1355 };
1356 opp01 {
1357 opp-hz = /bits/ 64 <133000000>;
1358 };
1359 opp02 {
1360 opp-hz = /bits/ 64 <178000000>;
1361 };
1362 opp03 {
1363 opp-hz = /bits/ 64 <267000000>;
1364 };
1365 };
1366
1367 bus_peri_opp_table: opp_table8 {
1368 compatible = "operating-points-v2";
1369
1370 opp00 {
1371 opp-hz = /bits/ 64 <67000000>;
1372 };
1373 };
1374
1375 bus_g2d_opp_table: opp_table9 {
1376 compatible = "operating-points-v2";
1377
1378 opp00 {
1379 opp-hz = /bits/ 64 <84000000>;
1380 };
1381 opp01 {
1382 opp-hz = /bits/ 64 <167000000>;
1383 };
1384 opp02 {
1385 opp-hz = /bits/ 64 <222000000>;
1386 };
1387 opp03 {
1388 opp-hz = /bits/ 64 <300000000>;
1389 };
1390 opp04 {
1391 opp-hz = /bits/ 64 <333000000>;
1392 };
1393 };
1394
1395 bus_g2d_acp_opp_table: opp_table10 {
1396 compatible = "operating-points-v2";
1397
1398 opp00 {
1399 opp-hz = /bits/ 64 <67000000>;
1400 };
1401 opp01 {
1402 opp-hz = /bits/ 64 <133000000>;
1403 };
1404 opp02 {
1405 opp-hz = /bits/ 64 <178000000>;
1406 };
1407 opp03 {
1408 opp-hz = /bits/ 64 <267000000>;
1409 };
1410 };
1411
1412 bus_jpeg_opp_table: opp_table11 {
1413 compatible = "operating-points-v2";
1414
1415 opp00 {
1416 opp-hz = /bits/ 64 <75000000>;
1417 };
1418 opp01 {
1419 opp-hz = /bits/ 64 <150000000>;
1420 };
1421 opp02 {
1422 opp-hz = /bits/ 64 <200000000>;
1423 };
1424 opp03 {
1425 opp-hz = /bits/ 64 <300000000>;
1426 };
1427 };
1428
1429 bus_jpeg_apb_opp_table: opp_table12 {
1430 compatible = "operating-points-v2";
1431
1432 opp00 {
1433 opp-hz = /bits/ 64 <84000000>;
1434 };
1435 opp01 {
1436 opp-hz = /bits/ 64 <111000000>;
1437 };
1438 opp02 {
1439 opp-hz = /bits/ 64 <134000000>;
1440 };
1441 opp03 {
1442 opp-hz = /bits/ 64 <167000000>;
1443 };
1444 };
1445
1446 bus_disp1_fimd_opp_table: opp_table13 {
1447 compatible = "operating-points-v2";
1448
1449 opp00 {
1450 opp-hz = /bits/ 64 <120000000>;
1451 };
1452 opp01 {
1453 opp-hz = /bits/ 64 <200000000>;
1454 };
1455 };
1456
1457 bus_disp1_opp_table: opp_table14 {
1458 compatible = "operating-points-v2";
1459
1460 opp00 {
1461 opp-hz = /bits/ 64 <120000000>;
1462 };
1463 opp01 {
1464 opp-hz = /bits/ 64 <200000000>;
1465 };
1466 opp02 {
1467 opp-hz = /bits/ 64 <300000000>;
1468 };
1469 };
1470
1471 bus_gscl_opp_table: opp_table15 {
1472 compatible = "operating-points-v2";
1473
1474 opp00 {
1475 opp-hz = /bits/ 64 <150000000>;
1476 };
1477 opp01 {
1478 opp-hz = /bits/ 64 <200000000>;
1479 };
1480 opp02 {
1481 opp-hz = /bits/ 64 <300000000>;
1482 };
1483 };
1484
1485 bus_mscl_opp_table: opp_table16 {
1486 compatible = "operating-points-v2";
1487
1488 opp00 {
1489 opp-hz = /bits/ 64 <84000000>;
1490 };
1491 opp01 {
1492 opp-hz = /bits/ 64 <167000000>;
1493 };
1494 opp02 {
1495 opp-hz = /bits/ 64 <222000000>;
1496 };
1497 opp03 {
1498 opp-hz = /bits/ 64 <333000000>;
1499 };
1500 opp04 {
1501 opp-hz = /bits/ 64 <400000000>;
1502 };
1503 };
1504 };
1505
1506 thermal-zones {
1507 cpu0_thermal: cpu0-thermal {
1508 thermal-sensors = <&tmu_cpu0>;
1509 #include "exynos5420-trip-points.dtsi"
1510 };
1511 cpu1_thermal: cpu1-thermal {
1512 thermal-sensors = <&tmu_cpu1>;
1513 #include "exynos5420-trip-points.dtsi"
1514 };
1515 cpu2_thermal: cpu2-thermal {
1516 thermal-sensors = <&tmu_cpu2>;
1517 #include "exynos5420-trip-points.dtsi"
1518 };
1519 cpu3_thermal: cpu3-thermal {
1520 thermal-sensors = <&tmu_cpu3>;
1521 #include "exynos5420-trip-points.dtsi"
1522 };
1523 gpu_thermal: gpu-thermal {
1524 thermal-sensors = <&tmu_gpu>;
1525 #include "exynos5420-trip-points.dtsi"
1526 };
1527 };
1528 };
1529
1530 &dp {
1531 clocks = <&clock CLK_DP1>;
1532 clock-names = "dp";
1533 phys = <&dp_phy>;
1534 phy-names = "dp";
1535 power-domains = <&disp_pd>;
1536 };
1537
1538 &fimd {
1539 compatible = "samsung,exynos5420-fimd";
1540 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1541 clock-names = "sclk_fimd", "fimd";
1542 power-domains = <&disp_pd>;
1543 iommus = <&sysmmu_fimd1_0>, <&sysmmu_fimd1_1>;
1544 iommu-names = "m0", "m1";
1545 };
1546
1547 &i2c_0 {
1548 clocks = <&clock CLK_I2C0>;
1549 clock-names = "i2c";
1550 pinctrl-names = "default";
1551 pinctrl-0 = <&i2c0_bus>;
1552 };
1553
1554 &i2c_1 {
1555 clocks = <&clock CLK_I2C1>;
1556 clock-names = "i2c";
1557 pinctrl-names = "default";
1558 pinctrl-0 = <&i2c1_bus>;
1559 };
1560
1561 &i2c_2 {
1562 clocks = <&clock CLK_I2C2>;
1563 clock-names = "i2c";
1564 pinctrl-names = "default";
1565 pinctrl-0 = <&i2c2_bus>;
1566 };
1567
1568 &i2c_3 {
1569 clocks = <&clock CLK_I2C3>;
1570 clock-names = "i2c";
1571 pinctrl-names = "default";
1572 pinctrl-0 = <&i2c3_bus>;
1573 };
1574
1575 &pwm {
1576 clocks = <&clock CLK_PWM>;
1577 clock-names = "timers";
1578 };
1579
1580 &rtc {
1581 clocks = <&clock CLK_RTC>;
1582 clock-names = "rtc";
1583 interrupt-parent = <&pmu_system_controller>;
1584 status = "disabled";
1585 };
1586
1587 &serial_0 {
1588 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1589 clock-names = "uart", "clk_uart_baud0";
1590 };
1591
1592 &serial_1 {
1593 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1594 clock-names = "uart", "clk_uart_baud0";
1595 };
1596
1597 &serial_2 {
1598 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1599 clock-names = "uart", "clk_uart_baud0";
1600 };
1601
1602 &serial_3 {
1603 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1604 clock-names = "uart", "clk_uart_baud0";
1605 };
1606
1607 #include "exynos5420-pinctrl.dtsi"
Linux kernel - Deliverables
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