arch/arm/boot/dts/highbank.dts

   1 /*
   2  * Copyright 2011-2012 Calxeda, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 /dts-v1/;
  18
  19 /* First 4KB has pen for secondary cores. */
  20 /memreserve/ 0x00000000 0x0001000;
  21
  22 / {
  23         model = "Calxeda Highbank";
  24         compatible = "calxeda,highbank";
  25         #address-cells = <1>;
  26         #size-cells = <1>;
  27         clock-ranges;
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 cpu@900 {
  34                         compatible = "arm,cortex-a9";
  35                         device_type = "cpu";
  36                         reg = <0x900>;
  37                         next-level-cache = <&L2>;
  38                         clocks = <&a9pll>;
  39                         clock-names = "cpu";
  40                         operating-points = <
  41                                 /* kHz    ignored */
  42                                  1300000  1000000
  43                                  1200000  1000000
  44                                  1100000  1000000
  45                                   800000  1000000
  46                                   400000  1000000
  47                                   200000  1000000
  48                         >;
  49                         clock-latency = <100000>;
  50                 };
  51
  52                 cpu@901 {
  53                         compatible = "arm,cortex-a9";
  54                         device_type = "cpu";
  55                         reg = <0x901>;
  56                         next-level-cache = <&L2>;
  57                         clocks = <&a9pll>;
  58                         clock-names = "cpu";
  59                 };
  60
  61                 cpu@902 {
  62                         compatible = "arm,cortex-a9";
  63                         device_type = "cpu";
  64                         reg = <0x902>;
  65                         next-level-cache = <&L2>;
  66                         clocks = <&a9pll>;
  67                         clock-names = "cpu";
  68                 };
  69
  70                 cpu@903 {
  71                         compatible = "arm,cortex-a9";
  72                         device_type = "cpu";
  73                         reg = <0x903>;
  74                         next-level-cache = <&L2>;
  75                         clocks = <&a9pll>;
  76                         clock-names = "cpu";
  77                 };
  78         };
  79
  80         memory {
  81                 name = "memory";
  82                 device_type = "memory";
  83                 reg = <0x00000000 0xff900000>;
  84         };
  85
  86         soc {
  87                 ranges = <0x00000000 0x00000000 0xffffffff>;
  88
  89                 timer@fff10600 {
  90                         compatible = "arm,cortex-a9-twd-timer";
  91                         reg = <0xfff10600 0x20>;
  92                         interrupts = <1 13 0xf01>;
  93                         clocks = <&a9periphclk>;
  94                 };
  95
  96                 watchdog@fff10620 {
  97                         compatible = "arm,cortex-a9-twd-wdt";
  98                         reg = <0xfff10620 0x20>;
  99                         interrupts = <1 14 0xf01>;
 100                         clocks = <&a9periphclk>;
 101                 };
 102
 103                 intc: interrupt-controller@fff11000 {
 104                         compatible = "arm,cortex-a9-gic";
 105                         #interrupt-cells = <3>;
 106                         #size-cells = <0>;
 107                         #address-cells = <1>;
 108                         interrupt-controller;
 109                         reg = <0xfff11000 0x1000>,
 110                               <0xfff10100 0x100>;
 111                 };
 112
 113                 L2: l2-cache {
 114                         compatible = "arm,pl310-cache";
 115                         reg = <0xfff12000 0x1000>;
 116                         interrupts = <0 70 4>;
 117                         cache-unified;
 118                         cache-level = <2>;
 119                 };
 120
 121                 pmu {
 122                         compatible = "arm,cortex-a9-pmu";
 123                         interrupts = <0 76 4  0 75 4  0 74 4  0 73 4>;
 124                 };
 125
 126
 127                 sregs@fff3c200 {
 128                         compatible = "calxeda,hb-sregs-l2-ecc";
 129                         reg = <0xfff3c200 0x100>;
 130                         interrupts = <0 71 4  0 72 4>;
 131                 };
 132
 133         };
 134 };
 135
 136 /include/ "ecx-common.dtsi"