ARM: dts: STi: STih407: Switch LPC mode from RTC to Clocksource
[deliverable/linux.git] / arch / arm / boot / dts / imx27-phytec-phycard-s-rdk.dts
1 /*
2 * Copyright 2012 Markus Pargmann, Pengutronix
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12 #include "imx27-phytec-phycard-s-som.dtsi"
13
14 / {
15 model = "Phytec pca100 rapid development kit";
16 compatible = "phytec,imx27-pca100-rdk", "phytec,imx27-pca100", "fsl,imx27";
17
18 chosen {
19 stdout-path = &uart1;
20 };
21
22 display: display {
23 model = "Primeview-PD050VL1";
24 native-mode = <&timing0>;
25 bits-per-pixel = <16>; /* non-standard but required */
26 fsl,pcr = <0xf0c88080>; /* non-standard but required */
27 display-timings {
28 timing0: 640x480 {
29 hactive = <640>;
30 vactive = <480>;
31 hback-porch = <112>;
32 hfront-porch = <36>;
33 hsync-len = <32>;
34 vback-porch = <33>;
35 vfront-porch = <33>;
36 vsync-len = <2>;
37 clock-frequency = <25000000>;
38 };
39 };
40 };
41
42 regulators {
43 compatible = "simple-bus";
44 #address-cells = <1>;
45 #size-cells = <0>;
46
47 reg_3v3: regulator@0 {
48 compatible = "regulator-fixed";
49 reg = <0>;
50 regulator-name = "3V3";
51 regulator-min-microvolt = <3300000>;
52 regulator-max-microvolt = <3300000>;
53 regulator-always-on;
54 };
55 };
56 };
57
58 &fb {
59 display = <&display>;
60 status = "okay";
61 };
62
63 &i2c1 {
64 pinctrl-names = "default";
65 pinctrl-0 = <&pinctrl_i2c1>;
66 status = "okay";
67
68 rtc@51 {
69 compatible = "nxp,pcf8563";
70 reg = <0x51>;
71 };
72
73 adc@64 {
74 compatible = "maxim,max1037";
75 vcc-supply = <&reg_3v3>;
76 reg = <0x64>;
77 };
78 };
79
80 &iomuxc {
81 imx27-phycard-s-rdk {
82 pinctrl_i2c1: i2c1grp {
83 fsl,pins = <
84 MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
85 MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
86 >;
87 };
88
89 pinctrl_owire1: owire1grp {
90 fsl,pins = <
91 MX27_PAD_RTCK__OWIRE 0x0
92 >;
93 };
94
95 pinctrl_sdhc2: sdhc2grp {
96 fsl,pins = <
97 MX27_PAD_SD2_CLK__SD2_CLK 0x0
98 MX27_PAD_SD2_CMD__SD2_CMD 0x0
99 MX27_PAD_SD2_D0__SD2_D0 0x0
100 MX27_PAD_SD2_D1__SD2_D1 0x0
101 MX27_PAD_SD2_D2__SD2_D2 0x0
102 MX27_PAD_SD2_D3__SD2_D3 0x0
103 MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */
104 >;
105 };
106
107 pinctrl_uart1: uart1grp {
108 fsl,pins = <
109 MX27_PAD_UART1_TXD__UART1_TXD 0x0
110 MX27_PAD_UART1_RXD__UART1_RXD 0x0
111 MX27_PAD_UART1_CTS__UART1_CTS 0x0
112 MX27_PAD_UART1_RTS__UART1_RTS 0x0
113 >;
114 };
115
116 pinctrl_uart2: uart2grp {
117 fsl,pins = <
118 MX27_PAD_UART2_TXD__UART2_TXD 0x0
119 MX27_PAD_UART2_RXD__UART2_RXD 0x0
120 MX27_PAD_UART2_CTS__UART2_CTS 0x0
121 MX27_PAD_UART2_RTS__UART2_RTS 0x0
122 >;
123 };
124
125 pinctrl_uart3: uart3grp {
126 fsl,pins = <
127 MX27_PAD_UART3_TXD__UART3_TXD 0x0
128 MX27_PAD_UART3_RXD__UART3_RXD 0x0
129 MX27_PAD_UART3_CTS__UART3_CTS 0x0
130 MX27_PAD_UART3_RTS__UART3_RTS 0x0
131 >;
132 };
133 };
134 };
135
136 &owire {
137 pinctrl-names = "default";
138 pinctrl-0 = <&pinctrl_owire1>;
139 status = "okay";
140 };
141
142 &sdhci2 {
143 pinctrl-names = "default";
144 pinctrl-0 = <&pinctrl_sdhc2>;
145 cd-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
146 status = "okay";
147 };
148
149 &uart1 {
150 fsl,uart-has-rtscts;
151 pinctrl-names = "default";
152 pinctrl-0 = <&pinctrl_uart1>;
153 status = "okay";
154 };
155
156 &uart2 {
157 fsl,uart-has-rtscts;
158 pinctrl-names = "default";
159 pinctrl-0 = <&pinctrl_uart2>;
160 status = "okay";
161 };
162
163 &uart3 {
164 fsl,uart-has-rtscts;
165 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_uart3>;
167 status = "okay";
168 };
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