2 * Copyright 2012 Freescale Semiconductor, Inc.
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
12 /include/ "skeleton.dtsi"
15 interrupt-parent = <&icoll>;
34 compatible = "arm,arm926ejs";
39 compatible = "simple-bus";
42 reg = <0x80000000 0x80000>;
46 compatible = "simple-bus";
49 reg = <0x80000000 0x3c900>;
52 icoll: interrupt-controller@80000000 {
53 compatible = "fsl,imx28-icoll", "fsl,mxs-icoll";
55 #interrupt-cells = <1>;
56 reg = <0x80000000 0x2000>;
60 reg = <0x80002000 0x2000>;
66 compatible = "fsl,imx28-dma-apbh";
67 reg = <0x80004000 0x2000>;
71 reg = <0x80006000 0x800>;
77 compatible = "fsl,imx28-gpmi-nand";
80 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
81 reg-names = "gpmi-nand", "bch";
82 interrupts = <88>, <41>;
83 interrupt-names = "gpmi-dma", "bch";
84 fsl,gpmi-dma-channel = <4>;
91 reg = <0x80010000 0x2000>;
93 fsl,ssp-dma-channel = <0>;
100 reg = <0x80012000 0x2000>;
101 interrupts = <97 83>;
102 fsl,ssp-dma-channel = <1>;
107 #address-cells = <1>;
109 reg = <0x80014000 0x2000>;
110 interrupts = <98 84>;
111 fsl,ssp-dma-channel = <2>;
116 #address-cells = <1>;
118 reg = <0x80016000 0x2000>;
119 interrupts = <99 85>;
120 fsl,ssp-dma-channel = <3>;
125 #address-cells = <1>;
127 compatible = "fsl,imx28-pinctrl", "simple-bus";
128 reg = <0x80018000 0x2000>;
131 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
135 interrupt-controller;
136 #interrupt-cells = <2>;
140 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
144 interrupt-controller;
145 #interrupt-cells = <2>;
149 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
153 interrupt-controller;
154 #interrupt-cells = <2>;
158 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
162 interrupt-controller;
163 #interrupt-cells = <2>;
167 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
171 interrupt-controller;
172 #interrupt-cells = <2>;
175 duart_pins_a: duart@0 {
178 0x3102 /* MX28_PAD_PWM0__DUART_RX */
179 0x3112 /* MX28_PAD_PWM1__DUART_TX */
181 fsl,drive-strength = <0>;
186 duart_pins_b: duart@1 {
189 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
190 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
192 fsl,drive-strength = <0>;
197 duart_4pins_a: duart-4pins@0 {
200 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
201 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
202 0x3002 /* MX28_PAD_AUART0_RX__DUART_CTS */
203 0x3012 /* MX28_PAD_AUART0_TX__DUART_RTS */
205 fsl,drive-strength = <0>;
210 gpmi_pins_a: gpmi-nand@0 {
213 0x0000 /* MX28_PAD_GPMI_D00__GPMI_D0 */
214 0x0010 /* MX28_PAD_GPMI_D01__GPMI_D1 */
215 0x0020 /* MX28_PAD_GPMI_D02__GPMI_D2 */
216 0x0030 /* MX28_PAD_GPMI_D03__GPMI_D3 */
217 0x0040 /* MX28_PAD_GPMI_D04__GPMI_D4 */
218 0x0050 /* MX28_PAD_GPMI_D05__GPMI_D5 */
219 0x0060 /* MX28_PAD_GPMI_D06__GPMI_D6 */
220 0x0070 /* MX28_PAD_GPMI_D07__GPMI_D7 */
221 0x0100 /* MX28_PAD_GPMI_CE0N__GPMI_CE0N */
222 0x0140 /* MX28_PAD_GPMI_RDY0__GPMI_READY0 */
223 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
224 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
225 0x01a0 /* MX28_PAD_GPMI_ALE__GPMI_ALE */
226 0x01b0 /* MX28_PAD_GPMI_CLE__GPMI_CLE */
227 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
229 fsl,drive-strength = <0>;
234 gpmi_status_cfg: gpmi-status-cfg {
236 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
237 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
238 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
240 fsl,drive-strength = <2>;
243 auart0_pins_a: auart0@0 {
246 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
247 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
248 0x3020 /* MX28_PAD_AUART0_CTS__AUART0_CTS */
249 0x3030 /* MX28_PAD_AUART0_RTS__AUART0_RTS */
251 fsl,drive-strength = <0>;
256 auart0_2pins_a: auart0-2pins@0 {
259 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
260 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
262 fsl,drive-strength = <0>;
267 auart1_pins_a: auart1@0 {
270 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
271 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
272 0x3060 /* MX28_PAD_AUART1_CTS__AUART1_CTS */
273 0x3070 /* MX28_PAD_AUART1_RTS__AUART1_RTS */
275 fsl,drive-strength = <0>;
280 auart1_2pins_a: auart1-2pins@0 {
283 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
284 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
286 fsl,drive-strength = <0>;
291 auart2_2pins_a: auart2-2pins@0 {
294 0x2101 /* MX28_PAD_SSP2_SCK__AUART2_RX */
295 0x2111 /* MX28_PAD_SSP2_MOSI__AUART2_TX */
297 fsl,drive-strength = <0>;
302 auart3_pins_a: auart3@0 {
305 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */
306 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */
307 0x30e0 /* MX28_PAD_AUART3_CTS__AUART3_CTS */
308 0x30f0 /* MX28_PAD_AUART3_RTS__AUART3_RTS */
310 fsl,drive-strength = <0>;
315 auart3_2pins_a: auart3-2pins@0 {
318 0x2121 /* MX28_PAD_SSP2_MISO__AUART3_RX */
319 0x2131 /* MX28_PAD_SSP2_SS0__AUART3_TX */
321 fsl,drive-strength = <0>;
326 mac0_pins_a: mac0@0 {
329 0x4000 /* MX28_PAD_ENET0_MDC__ENET0_MDC */
330 0x4010 /* MX28_PAD_ENET0_MDIO__ENET0_MDIO */
331 0x4020 /* MX28_PAD_ENET0_RX_EN__ENET0_RX_EN */
332 0x4030 /* MX28_PAD_ENET0_RXD0__ENET0_RXD0 */
333 0x4040 /* MX28_PAD_ENET0_RXD1__ENET0_RXD1 */
334 0x4060 /* MX28_PAD_ENET0_TX_EN__ENET0_TX_EN */
335 0x4070 /* MX28_PAD_ENET0_TXD0__ENET0_TXD0 */
336 0x4080 /* MX28_PAD_ENET0_TXD1__ENET0_TXD1 */
337 0x4100 /* MX28_PAD_ENET_CLK__CLKCTRL_ENET */
339 fsl,drive-strength = <1>;
344 mac1_pins_a: mac1@0 {
347 0x40f1 /* MX28_PAD_ENET0_CRS__ENET1_RX_EN */
348 0x4091 /* MX28_PAD_ENET0_RXD2__ENET1_RXD0 */
349 0x40a1 /* MX28_PAD_ENET0_RXD3__ENET1_RXD1 */
350 0x40e1 /* MX28_PAD_ENET0_COL__ENET1_TX_EN */
351 0x40b1 /* MX28_PAD_ENET0_TXD2__ENET1_TXD0 */
352 0x40c1 /* MX28_PAD_ENET0_TXD3__ENET1_TXD1 */
354 fsl,drive-strength = <1>;
359 mmc0_8bit_pins_a: mmc0-8bit@0 {
362 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
363 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
364 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
365 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
366 0x2040 /* MX28_PAD_SSP0_DATA4__SSP0_D4 */
367 0x2050 /* MX28_PAD_SSP0_DATA5__SSP0_D5 */
368 0x2060 /* MX28_PAD_SSP0_DATA6__SSP0_D6 */
369 0x2070 /* MX28_PAD_SSP0_DATA7__SSP0_D7 */
370 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
371 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
372 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
374 fsl,drive-strength = <1>;
379 mmc0_4bit_pins_a: mmc0-4bit@0 {
382 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
383 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
384 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
385 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
386 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
387 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
388 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
390 fsl,drive-strength = <1>;
395 mmc0_cd_cfg: mmc0-cd-cfg {
397 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
402 mmc0_sck_cfg: mmc0-sck-cfg {
404 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
406 fsl,drive-strength = <2>;
410 i2c0_pins_a: i2c0@0 {
413 0x3180 /* MX28_PAD_I2C0_SCL__I2C0_SCL */
414 0x3190 /* MX28_PAD_I2C0_SDA__I2C0_SDA */
416 fsl,drive-strength = <1>;
421 i2c0_pins_b: i2c0@1 {
424 0x3001 /* MX28_PAD_AUART0_RX__I2C0_SCL */
425 0x3011 /* MX28_PAD_AUART0_TX__I2C0_SDA */
427 fsl,drive-strength = <1>;
432 i2c1_pins_a: i2c1@0 {
435 0x3101 /* MX28_PAD_PWM0__I2C1_SCL */
436 0x3111 /* MX28_PAD_PWM1__I2C1_SDA */
438 fsl,drive-strength = <1>;
443 saif0_pins_a: saif0@0 {
446 0x3140 /* MX28_PAD_SAIF0_MCLK__SAIF0_MCLK */
447 0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */
448 0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */
449 0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */
451 fsl,drive-strength = <2>;
456 saif1_pins_a: saif1@0 {
459 0x31a0 /* MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 */
461 fsl,drive-strength = <2>;
466 pwm0_pins_a: pwm0@0 {
469 0x3100 /* MX28_PAD_PWM0__PWM_0 */
471 fsl,drive-strength = <0>;
476 pwm2_pins_a: pwm2@0 {
479 0x3120 /* MX28_PAD_PWM2__PWM_2 */
481 fsl,drive-strength = <0>;
486 pwm4_pins_a: pwm4@0 {
489 0x31d0 /* MX28_PAD_PWM4__PWM_4 */
491 fsl,drive-strength = <0>;
496 lcdif_24bit_pins_a: lcdif-24bit@0 {
499 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
500 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
501 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
502 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
503 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
504 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
505 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
506 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
507 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
508 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
509 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
510 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
511 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
512 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
513 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
514 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
515 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */
516 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */
517 0x1120 /* MX28_PAD_LCD_D18__LCD_D18 */
518 0x1130 /* MX28_PAD_LCD_D19__LCD_D19 */
519 0x1140 /* MX28_PAD_LCD_D20__LCD_D20 */
520 0x1150 /* MX28_PAD_LCD_D21__LCD_D21 */
521 0x1160 /* MX28_PAD_LCD_D22__LCD_D22 */
522 0x1170 /* MX28_PAD_LCD_D23__LCD_D23 */
524 fsl,drive-strength = <0>;
529 can0_pins_a: can0@0 {
532 0x0161 /* MX28_PAD_GPMI_RDY2__CAN0_TX */
533 0x0171 /* MX28_PAD_GPMI_RDY3__CAN0_RX */
535 fsl,drive-strength = <0>;
540 can1_pins_a: can1@0 {
543 0x0121 /* MX28_PAD_GPMI_CE2N__CAN1_TX */
544 0x0131 /* MX28_PAD_GPMI_CE3N__CAN1_RX */
546 fsl,drive-strength = <0>;
551 spi2_pins_a: spi2@0 {
554 0x2100 /* MX28_PAD_SSP2_SCK__SSP2_SCK */
555 0x2110 /* MX28_PAD_SSP2_MOSI__SSP2_CMD */
556 0x2120 /* MX28_PAD_SSP2_MISO__SSP2_D0 */
557 0x2130 /* MX28_PAD_SSP2_SS0__SSP2_D3 */
559 fsl,drive-strength = <1>;
564 usbphy0_pins_a: usbphy0@0 {
567 0x2152 /* MX28_PAD_SSP2_SS2__USB0_OVERCURRENT */
569 fsl,drive-strength = <2>;
574 usbphy0_pins_b: usbphy0@1 {
577 0x3061 /* MX28_PAD_AUART1_CTS__USB0_OVERCURRENT */
579 fsl,drive-strength = <2>;
584 usbphy1_pins_a: usbphy1@0 {
587 0x2142 /* MX28_PAD_SSP2_SS1__USB1_OVERCURRENT */
589 fsl,drive-strength = <2>;
596 reg = <0x8001c000 0x2000>;
602 reg = <0x80022000 0x2000>;
607 compatible = "fsl,imx28-dma-apbx";
608 reg = <0x80024000 0x2000>;
612 reg = <0x80028000 0x2000>;
613 interrupts = <52 53 54>;
618 reg = <0x8002a000 0x2000>;
624 reg = <0x8002c000 0x2000>;
629 reg = <0x8002e000 0x2000>;
634 compatible = "fsl,imx28-lcdif";
635 reg = <0x80030000 0x2000>;
636 interrupts = <38 86>;
641 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
642 reg = <0x80032000 0x2000>;
648 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
649 reg = <0x80034000 0x2000>;
655 reg = <0x8003c000 0x200>;
659 simgpmisel@8003c200 {
660 reg = <0x8003c200 0x100>;
665 reg = <0x8003c300 0x100>;
670 reg = <0x8003c400 0x100>;
675 reg = <0x8003c500 0x100>;
680 reg = <0x8003c700 0x100>;
685 reg = <0x8003c800 0x100>;
691 compatible = "simple-bus";
692 #address-cells = <1>;
694 reg = <0x80040000 0x40000>;
698 reg = <0x80040000 0x2000>;
702 saif0: saif@80042000 {
703 compatible = "fsl,imx28-saif";
704 reg = <0x80042000 0x2000>;
705 interrupts = <59 80>;
706 fsl,saif-dma-channel = <4>;
711 reg = <0x80044000 0x2000>;
715 saif1: saif@80046000 {
716 compatible = "fsl,imx28-saif";
717 reg = <0x80046000 0x2000>;
718 interrupts = <58 81>;
719 fsl,saif-dma-channel = <5>;
724 compatible = "fsl,imx28-lradc";
725 reg = <0x80050000 0x2000>;
726 interrupts = <10 14 15 16 17 18 19
732 reg = <0x80054000 0x2000>;
733 interrupts = <45 66>;
738 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
739 reg = <0x80056000 0x2000>;
744 #address-cells = <1>;
746 compatible = "fsl,imx28-i2c";
747 reg = <0x80058000 0x2000>;
748 interrupts = <111 68>;
749 clock-frequency = <100000>;
754 #address-cells = <1>;
756 compatible = "fsl,imx28-i2c";
757 reg = <0x8005a000 0x2000>;
758 interrupts = <110 69>;
759 clock-frequency = <100000>;
764 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
765 reg = <0x80064000 0x2000>;
767 fsl,pwm-number = <8>;
772 reg = <0x80068000 0x2000>;
776 auart0: serial@8006a000 {
777 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
778 reg = <0x8006a000 0x2000>;
779 interrupts = <112 70 71>;
783 auart1: serial@8006c000 {
784 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
785 reg = <0x8006c000 0x2000>;
786 interrupts = <113 72 73>;
790 auart2: serial@8006e000 {
791 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
792 reg = <0x8006e000 0x2000>;
793 interrupts = <114 74 75>;
797 auart3: serial@80070000 {
798 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
799 reg = <0x80070000 0x2000>;
800 interrupts = <115 76 77>;
804 auart4: serial@80072000 {
805 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
806 reg = <0x80072000 0x2000>;
807 interrupts = <116 78 79>;
811 duart: serial@80074000 {
812 compatible = "arm,pl011", "arm,primecell";
813 reg = <0x80074000 0x1000>;
818 usbphy0: usbphy@8007c000 {
819 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
820 reg = <0x8007c000 0x2000>;
824 usbphy1: usbphy@8007e000 {
825 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
826 reg = <0x8007e000 0x2000>;
833 compatible = "simple-bus";
834 #address-cells = <1>;
836 reg = <0x80080000 0x80000>;
840 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
841 reg = <0x80080000 0x10000>;
843 fsl,usbphy = <&usbphy0>;
848 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
849 reg = <0x80090000 0x10000>;
851 fsl,usbphy = <&usbphy1>;
856 reg = <0x800c0000 0x10000>;
860 mac0: ethernet@800f0000 {
861 compatible = "fsl,imx28-fec";
862 reg = <0x800f0000 0x4000>;
867 mac1: ethernet@800f4000 {
868 compatible = "fsl,imx28-fec";
869 reg = <0x800f4000 0x4000>;
875 reg = <0x800f8000 0x8000>;