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a95cc5358ff460cc688d97535bccc8722c9f0358
[deliverable/linux.git] / arch / arm / boot / dts / imx28.dtsi
1 /*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12 #include <dt-bindings/gpio/gpio.h>
13 #include "skeleton.dtsi"
14 #include "imx28-pinfunc.h"
15
16 / {
17 interrupt-parent = <&icoll>;
18
19 aliases {
20 ethernet0 = &mac0;
21 ethernet1 = &mac1;
22 gpio0 = &gpio0;
23 gpio1 = &gpio1;
24 gpio2 = &gpio2;
25 gpio3 = &gpio3;
26 gpio4 = &gpio4;
27 saif0 = &saif0;
28 saif1 = &saif1;
29 serial0 = &auart0;
30 serial1 = &auart1;
31 serial2 = &auart2;
32 serial3 = &auart3;
33 serial4 = &auart4;
34 spi0 = &ssp1;
35 spi1 = &ssp2;
36 usbphy0 = &usbphy0;
37 usbphy1 = &usbphy1;
38 };
39
40 cpus {
41 #address-cells = <0>;
42 #size-cells = <0>;
43
44 cpu {
45 compatible = "arm,arm926ej-s";
46 device_type = "cpu";
47 };
48 };
49
50 apb@80000000 {
51 compatible = "simple-bus";
52 #address-cells = <1>;
53 #size-cells = <1>;
54 reg = <0x80000000 0x80000>;
55 ranges;
56
57 apbh@80000000 {
58 compatible = "simple-bus";
59 #address-cells = <1>;
60 #size-cells = <1>;
61 reg = <0x80000000 0x3c900>;
62 ranges;
63
64 icoll: interrupt-controller@80000000 {
65 compatible = "fsl,imx28-icoll", "fsl,icoll";
66 interrupt-controller;
67 #interrupt-cells = <1>;
68 reg = <0x80000000 0x2000>;
69 };
70
71 hsadc: hsadc@80002000 {
72 reg = <0x80002000 0x2000>;
73 interrupts = <13>;
74 dmas = <&dma_apbh 12>;
75 dma-names = "rx";
76 status = "disabled";
77 };
78
79 dma_apbh: dma-apbh@80004000 {
80 compatible = "fsl,imx28-dma-apbh";
81 reg = <0x80004000 0x2000>;
82 interrupts = <82 83 84 85
83 88 88 88 88
84 88 88 88 88
85 87 86 0 0>;
86 interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
87 "gpmi0", "gmpi1", "gpmi2", "gmpi3",
88 "gpmi4", "gmpi5", "gpmi6", "gmpi7",
89 "hsadc", "lcdif", "empty", "empty";
90 #dma-cells = <1>;
91 dma-channels = <16>;
92 clocks = <&clks 25>;
93 };
94
95 perfmon: perfmon@80006000 {
96 reg = <0x80006000 0x800>;
97 interrupts = <27>;
98 status = "disabled";
99 };
100
101 gpmi: gpmi-nand@8000c000 {
102 compatible = "fsl,imx28-gpmi-nand";
103 #address-cells = <1>;
104 #size-cells = <1>;
105 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
106 reg-names = "gpmi-nand", "bch";
107 interrupts = <41>;
108 interrupt-names = "bch";
109 clocks = <&clks 50>;
110 clock-names = "gpmi_io";
111 dmas = <&dma_apbh 4>;
112 dma-names = "rx-tx";
113 status = "disabled";
114 };
115
116 ssp0: ssp@80010000 {
117 #address-cells = <1>;
118 #size-cells = <0>;
119 reg = <0x80010000 0x2000>;
120 interrupts = <96>;
121 clocks = <&clks 46>;
122 dmas = <&dma_apbh 0>;
123 dma-names = "rx-tx";
124 status = "disabled";
125 };
126
127 ssp1: ssp@80012000 {
128 #address-cells = <1>;
129 #size-cells = <0>;
130 reg = <0x80012000 0x2000>;
131 interrupts = <97>;
132 clocks = <&clks 47>;
133 dmas = <&dma_apbh 1>;
134 dma-names = "rx-tx";
135 status = "disabled";
136 };
137
138 ssp2: ssp@80014000 {
139 #address-cells = <1>;
140 #size-cells = <0>;
141 reg = <0x80014000 0x2000>;
142 interrupts = <98>;
143 clocks = <&clks 48>;
144 dmas = <&dma_apbh 2>;
145 dma-names = "rx-tx";
146 status = "disabled";
147 };
148
149 ssp3: ssp@80016000 {
150 #address-cells = <1>;
151 #size-cells = <0>;
152 reg = <0x80016000 0x2000>;
153 interrupts = <99>;
154 clocks = <&clks 49>;
155 dmas = <&dma_apbh 3>;
156 dma-names = "rx-tx";
157 status = "disabled";
158 };
159
160 pinctrl: pinctrl@80018000 {
161 #address-cells = <1>;
162 #size-cells = <0>;
163 compatible = "fsl,imx28-pinctrl", "simple-bus";
164 reg = <0x80018000 0x2000>;
165
166 gpio0: gpio@0 {
167 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
168 interrupts = <127>;
169 gpio-controller;
170 #gpio-cells = <2>;
171 interrupt-controller;
172 #interrupt-cells = <2>;
173 };
174
175 gpio1: gpio@1 {
176 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
177 interrupts = <126>;
178 gpio-controller;
179 #gpio-cells = <2>;
180 interrupt-controller;
181 #interrupt-cells = <2>;
182 };
183
184 gpio2: gpio@2 {
185 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
186 interrupts = <125>;
187 gpio-controller;
188 #gpio-cells = <2>;
189 interrupt-controller;
190 #interrupt-cells = <2>;
191 };
192
193 gpio3: gpio@3 {
194 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
195 interrupts = <124>;
196 gpio-controller;
197 #gpio-cells = <2>;
198 interrupt-controller;
199 #interrupt-cells = <2>;
200 };
201
202 gpio4: gpio@4 {
203 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
204 interrupts = <123>;
205 gpio-controller;
206 #gpio-cells = <2>;
207 interrupt-controller;
208 #interrupt-cells = <2>;
209 };
210
211 duart_pins_a: duart@0 {
212 reg = <0>;
213 fsl,pinmux-ids = <
214 MX28_PAD_PWM0__DUART_RX
215 MX28_PAD_PWM1__DUART_TX
216 >;
217 fsl,drive-strength = <MXS_DRIVE_4mA>;
218 fsl,voltage = <MXS_VOLTAGE_HIGH>;
219 fsl,pull-up = <MXS_PULL_DISABLE>;
220 };
221
222 duart_pins_b: duart@1 {
223 reg = <1>;
224 fsl,pinmux-ids = <
225 MX28_PAD_AUART0_CTS__DUART_RX
226 MX28_PAD_AUART0_RTS__DUART_TX
227 >;
228 fsl,drive-strength = <MXS_DRIVE_4mA>;
229 fsl,voltage = <MXS_VOLTAGE_HIGH>;
230 fsl,pull-up = <MXS_PULL_DISABLE>;
231 };
232
233 duart_4pins_a: duart-4pins@0 {
234 reg = <0>;
235 fsl,pinmux-ids = <
236 MX28_PAD_AUART0_CTS__DUART_RX
237 MX28_PAD_AUART0_RTS__DUART_TX
238 MX28_PAD_AUART0_RX__DUART_CTS
239 MX28_PAD_AUART0_TX__DUART_RTS
240 >;
241 fsl,drive-strength = <MXS_DRIVE_4mA>;
242 fsl,voltage = <MXS_VOLTAGE_HIGH>;
243 fsl,pull-up = <MXS_PULL_DISABLE>;
244 };
245
246 gpmi_pins_a: gpmi-nand@0 {
247 reg = <0>;
248 fsl,pinmux-ids = <
249 MX28_PAD_GPMI_D00__GPMI_D0
250 MX28_PAD_GPMI_D01__GPMI_D1
251 MX28_PAD_GPMI_D02__GPMI_D2
252 MX28_PAD_GPMI_D03__GPMI_D3
253 MX28_PAD_GPMI_D04__GPMI_D4
254 MX28_PAD_GPMI_D05__GPMI_D5
255 MX28_PAD_GPMI_D06__GPMI_D6
256 MX28_PAD_GPMI_D07__GPMI_D7
257 MX28_PAD_GPMI_CE0N__GPMI_CE0N
258 MX28_PAD_GPMI_RDY0__GPMI_READY0
259 MX28_PAD_GPMI_RDN__GPMI_RDN
260 MX28_PAD_GPMI_WRN__GPMI_WRN
261 MX28_PAD_GPMI_ALE__GPMI_ALE
262 MX28_PAD_GPMI_CLE__GPMI_CLE
263 MX28_PAD_GPMI_RESETN__GPMI_RESETN
264 >;
265 fsl,drive-strength = <MXS_DRIVE_4mA>;
266 fsl,voltage = <MXS_VOLTAGE_HIGH>;
267 fsl,pull-up = <MXS_PULL_DISABLE>;
268 };
269
270 gpmi_status_cfg: gpmi-status-cfg {
271 fsl,pinmux-ids = <
272 MX28_PAD_GPMI_RDN__GPMI_RDN
273 MX28_PAD_GPMI_WRN__GPMI_WRN
274 MX28_PAD_GPMI_RESETN__GPMI_RESETN
275 >;
276 fsl,drive-strength = <MXS_DRIVE_12mA>;
277 };
278
279 auart0_pins_a: auart0@0 {
280 reg = <0>;
281 fsl,pinmux-ids = <
282 MX28_PAD_AUART0_RX__AUART0_RX
283 MX28_PAD_AUART0_TX__AUART0_TX
284 MX28_PAD_AUART0_CTS__AUART0_CTS
285 MX28_PAD_AUART0_RTS__AUART0_RTS
286 >;
287 fsl,drive-strength = <MXS_DRIVE_4mA>;
288 fsl,voltage = <MXS_VOLTAGE_HIGH>;
289 fsl,pull-up = <MXS_PULL_DISABLE>;
290 };
291
292 auart0_2pins_a: auart0-2pins@0 {
293 reg = <0>;
294 fsl,pinmux-ids = <
295 MX28_PAD_AUART0_RX__AUART0_RX
296 MX28_PAD_AUART0_TX__AUART0_TX
297 >;
298 fsl,drive-strength = <MXS_DRIVE_4mA>;
299 fsl,voltage = <MXS_VOLTAGE_HIGH>;
300 fsl,pull-up = <MXS_PULL_DISABLE>;
301 };
302
303 auart1_pins_a: auart1@0 {
304 reg = <0>;
305 fsl,pinmux-ids = <
306 MX28_PAD_AUART1_RX__AUART1_RX
307 MX28_PAD_AUART1_TX__AUART1_TX
308 MX28_PAD_AUART1_CTS__AUART1_CTS
309 MX28_PAD_AUART1_RTS__AUART1_RTS
310 >;
311 fsl,drive-strength = <MXS_DRIVE_4mA>;
312 fsl,voltage = <MXS_VOLTAGE_HIGH>;
313 fsl,pull-up = <MXS_PULL_DISABLE>;
314 };
315
316 auart1_2pins_a: auart1-2pins@0 {
317 reg = <0>;
318 fsl,pinmux-ids = <
319 MX28_PAD_AUART1_RX__AUART1_RX
320 MX28_PAD_AUART1_TX__AUART1_TX
321 >;
322 fsl,drive-strength = <MXS_DRIVE_4mA>;
323 fsl,voltage = <MXS_VOLTAGE_HIGH>;
324 fsl,pull-up = <MXS_PULL_DISABLE>;
325 };
326
327 auart2_2pins_a: auart2-2pins@0 {
328 reg = <0>;
329 fsl,pinmux-ids = <
330 MX28_PAD_SSP2_SCK__AUART2_RX
331 MX28_PAD_SSP2_MOSI__AUART2_TX
332 >;
333 fsl,drive-strength = <MXS_DRIVE_4mA>;
334 fsl,voltage = <MXS_VOLTAGE_HIGH>;
335 fsl,pull-up = <MXS_PULL_DISABLE>;
336 };
337
338 auart2_2pins_b: auart2-2pins@1 {
339 reg = <1>;
340 fsl,pinmux-ids = <
341 MX28_PAD_AUART2_RX__AUART2_RX
342 MX28_PAD_AUART2_TX__AUART2_TX
343 >;
344 fsl,drive-strength = <MXS_DRIVE_4mA>;
345 fsl,voltage = <MXS_VOLTAGE_HIGH>;
346 fsl,pull-up = <MXS_PULL_DISABLE>;
347 };
348
349 auart2_pins_a: auart2-pins@0 {
350 reg = <0>;
351 fsl,pinmux-ids = <
352 MX28_PAD_AUART2_RX__AUART2_RX
353 MX28_PAD_AUART2_TX__AUART2_TX
354 MX28_PAD_AUART2_CTS__AUART2_CTS
355 MX28_PAD_AUART2_RTS__AUART2_RTS
356 >;
357 fsl,drive-strength = <MXS_DRIVE_4mA>;
358 fsl,voltage = <MXS_VOLTAGE_HIGH>;
359 fsl,pull-up = <MXS_PULL_DISABLE>;
360 };
361
362 auart3_pins_a: auart3@0 {
363 reg = <0>;
364 fsl,pinmux-ids = <
365 MX28_PAD_AUART3_RX__AUART3_RX
366 MX28_PAD_AUART3_TX__AUART3_TX
367 MX28_PAD_AUART3_CTS__AUART3_CTS
368 MX28_PAD_AUART3_RTS__AUART3_RTS
369 >;
370 fsl,drive-strength = <MXS_DRIVE_4mA>;
371 fsl,voltage = <MXS_VOLTAGE_HIGH>;
372 fsl,pull-up = <MXS_PULL_DISABLE>;
373 };
374
375 auart3_2pins_a: auart3-2pins@0 {
376 reg = <0>;
377 fsl,pinmux-ids = <
378 MX28_PAD_SSP2_MISO__AUART3_RX
379 MX28_PAD_SSP2_SS0__AUART3_TX
380 >;
381 fsl,drive-strength = <MXS_DRIVE_4mA>;
382 fsl,voltage = <MXS_VOLTAGE_HIGH>;
383 fsl,pull-up = <MXS_PULL_DISABLE>;
384 };
385
386 auart3_2pins_b: auart3-2pins@1 {
387 reg = <1>;
388 fsl,pinmux-ids = <
389 MX28_PAD_AUART3_RX__AUART3_RX
390 MX28_PAD_AUART3_TX__AUART3_TX
391 >;
392 fsl,drive-strength = <MXS_DRIVE_4mA>;
393 fsl,voltage = <MXS_VOLTAGE_HIGH>;
394 fsl,pull-up = <MXS_PULL_DISABLE>;
395 };
396
397 auart4_2pins_a: auart4@0 {
398 reg = <0>;
399 fsl,pinmux-ids = <
400 MX28_PAD_SSP3_SCK__AUART4_TX
401 MX28_PAD_SSP3_MOSI__AUART4_RX
402 >;
403 fsl,drive-strength = <MXS_DRIVE_4mA>;
404 fsl,voltage = <MXS_VOLTAGE_HIGH>;
405 fsl,pull-up = <MXS_PULL_DISABLE>;
406 };
407
408 mac0_pins_a: mac0@0 {
409 reg = <0>;
410 fsl,pinmux-ids = <
411 MX28_PAD_ENET0_MDC__ENET0_MDC
412 MX28_PAD_ENET0_MDIO__ENET0_MDIO
413 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
414 MX28_PAD_ENET0_RXD0__ENET0_RXD0
415 MX28_PAD_ENET0_RXD1__ENET0_RXD1
416 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
417 MX28_PAD_ENET0_TXD0__ENET0_TXD0
418 MX28_PAD_ENET0_TXD1__ENET0_TXD1
419 MX28_PAD_ENET_CLK__CLKCTRL_ENET
420 >;
421 fsl,drive-strength = <MXS_DRIVE_8mA>;
422 fsl,voltage = <MXS_VOLTAGE_HIGH>;
423 fsl,pull-up = <MXS_PULL_ENABLE>;
424 };
425
426 mac1_pins_a: mac1@0 {
427 reg = <0>;
428 fsl,pinmux-ids = <
429 MX28_PAD_ENET0_CRS__ENET1_RX_EN
430 MX28_PAD_ENET0_RXD2__ENET1_RXD0
431 MX28_PAD_ENET0_RXD3__ENET1_RXD1
432 MX28_PAD_ENET0_COL__ENET1_TX_EN
433 MX28_PAD_ENET0_TXD2__ENET1_TXD0
434 MX28_PAD_ENET0_TXD3__ENET1_TXD1
435 >;
436 fsl,drive-strength = <MXS_DRIVE_8mA>;
437 fsl,voltage = <MXS_VOLTAGE_HIGH>;
438 fsl,pull-up = <MXS_PULL_ENABLE>;
439 };
440
441 mmc0_8bit_pins_a: mmc0-8bit@0 {
442 reg = <0>;
443 fsl,pinmux-ids = <
444 MX28_PAD_SSP0_DATA0__SSP0_D0
445 MX28_PAD_SSP0_DATA1__SSP0_D1
446 MX28_PAD_SSP0_DATA2__SSP0_D2
447 MX28_PAD_SSP0_DATA3__SSP0_D3
448 MX28_PAD_SSP0_DATA4__SSP0_D4
449 MX28_PAD_SSP0_DATA5__SSP0_D5
450 MX28_PAD_SSP0_DATA6__SSP0_D6
451 MX28_PAD_SSP0_DATA7__SSP0_D7
452 MX28_PAD_SSP0_CMD__SSP0_CMD
453 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
454 MX28_PAD_SSP0_SCK__SSP0_SCK
455 >;
456 fsl,drive-strength = <MXS_DRIVE_8mA>;
457 fsl,voltage = <MXS_VOLTAGE_HIGH>;
458 fsl,pull-up = <MXS_PULL_ENABLE>;
459 };
460
461 mmc0_4bit_pins_a: mmc0-4bit@0 {
462 reg = <0>;
463 fsl,pinmux-ids = <
464 MX28_PAD_SSP0_DATA0__SSP0_D0
465 MX28_PAD_SSP0_DATA1__SSP0_D1
466 MX28_PAD_SSP0_DATA2__SSP0_D2
467 MX28_PAD_SSP0_DATA3__SSP0_D3
468 MX28_PAD_SSP0_CMD__SSP0_CMD
469 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
470 MX28_PAD_SSP0_SCK__SSP0_SCK
471 >;
472 fsl,drive-strength = <MXS_DRIVE_8mA>;
473 fsl,voltage = <MXS_VOLTAGE_HIGH>;
474 fsl,pull-up = <MXS_PULL_ENABLE>;
475 };
476
477 mmc0_cd_cfg: mmc0-cd-cfg {
478 fsl,pinmux-ids = <
479 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
480 >;
481 fsl,pull-up = <MXS_PULL_DISABLE>;
482 };
483
484 mmc0_sck_cfg: mmc0-sck-cfg {
485 fsl,pinmux-ids = <
486 MX28_PAD_SSP0_SCK__SSP0_SCK
487 >;
488 fsl,drive-strength = <MXS_DRIVE_12mA>;
489 fsl,pull-up = <MXS_PULL_DISABLE>;
490 };
491
492 mmc2_4bit_pins_a: mmc2-4bit@0 {
493 reg = <0>;
494 fsl,pinmux-ids = <
495 MX28_PAD_SSP0_DATA4__SSP2_D0
496 MX28_PAD_SSP1_SCK__SSP2_D1
497 MX28_PAD_SSP1_CMD__SSP2_D2
498 MX28_PAD_SSP0_DATA5__SSP2_D3
499 MX28_PAD_SSP0_DATA6__SSP2_CMD
500 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
501 MX28_PAD_SSP0_DATA7__SSP2_SCK
502 >;
503 fsl,drive-strength = <MXS_DRIVE_8mA>;
504 fsl,voltage = <MXS_VOLTAGE_HIGH>;
505 fsl,pull-up = <MXS_PULL_ENABLE>;
506 };
507
508 mmc2_cd_cfg: mmc2-cd-cfg {
509 fsl,pinmux-ids = <
510 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
511 >;
512 fsl,pull-up = <MXS_PULL_DISABLE>;
513 };
514
515 mmc2_sck_cfg: mmc2-sck-cfg {
516 fsl,pinmux-ids = <
517 MX28_PAD_SSP0_DATA7__SSP2_SCK
518 >;
519 fsl,drive-strength = <MXS_DRIVE_12mA>;
520 fsl,pull-up = <MXS_PULL_DISABLE>;
521 };
522
523 i2c0_pins_a: i2c0@0 {
524 reg = <0>;
525 fsl,pinmux-ids = <
526 MX28_PAD_I2C0_SCL__I2C0_SCL
527 MX28_PAD_I2C0_SDA__I2C0_SDA
528 >;
529 fsl,drive-strength = <MXS_DRIVE_8mA>;
530 fsl,voltage = <MXS_VOLTAGE_HIGH>;
531 fsl,pull-up = <MXS_PULL_ENABLE>;
532 };
533
534 i2c0_pins_b: i2c0@1 {
535 reg = <1>;
536 fsl,pinmux-ids = <
537 MX28_PAD_AUART0_RX__I2C0_SCL
538 MX28_PAD_AUART0_TX__I2C0_SDA
539 >;
540 fsl,drive-strength = <MXS_DRIVE_8mA>;
541 fsl,voltage = <MXS_VOLTAGE_HIGH>;
542 fsl,pull-up = <MXS_PULL_ENABLE>;
543 };
544
545 i2c1_pins_a: i2c1@0 {
546 reg = <0>;
547 fsl,pinmux-ids = <
548 MX28_PAD_PWM0__I2C1_SCL
549 MX28_PAD_PWM1__I2C1_SDA
550 >;
551 fsl,drive-strength = <MXS_DRIVE_8mA>;
552 fsl,voltage = <MXS_VOLTAGE_HIGH>;
553 fsl,pull-up = <MXS_PULL_ENABLE>;
554 };
555
556 saif0_pins_a: saif0@0 {
557 reg = <0>;
558 fsl,pinmux-ids = <
559 MX28_PAD_SAIF0_MCLK__SAIF0_MCLK
560 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
561 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
562 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
563 >;
564 fsl,drive-strength = <MXS_DRIVE_12mA>;
565 fsl,voltage = <MXS_VOLTAGE_HIGH>;
566 fsl,pull-up = <MXS_PULL_ENABLE>;
567 };
568
569 saif0_pins_b: saif0@1 {
570 reg = <1>;
571 fsl,pinmux-ids = <
572 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
573 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
574 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
575 >;
576 fsl,drive-strength = <MXS_DRIVE_12mA>;
577 fsl,voltage = <MXS_VOLTAGE_HIGH>;
578 fsl,pull-up = <MXS_PULL_ENABLE>;
579 };
580
581 saif1_pins_a: saif1@0 {
582 reg = <0>;
583 fsl,pinmux-ids = <
584 MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0
585 >;
586 fsl,drive-strength = <MXS_DRIVE_12mA>;
587 fsl,voltage = <MXS_VOLTAGE_HIGH>;
588 fsl,pull-up = <MXS_PULL_ENABLE>;
589 };
590
591 pwm0_pins_a: pwm0@0 {
592 reg = <0>;
593 fsl,pinmux-ids = <
594 MX28_PAD_PWM0__PWM_0
595 >;
596 fsl,drive-strength = <MXS_DRIVE_4mA>;
597 fsl,voltage = <MXS_VOLTAGE_HIGH>;
598 fsl,pull-up = <MXS_PULL_DISABLE>;
599 };
600
601 pwm2_pins_a: pwm2@0 {
602 reg = <0>;
603 fsl,pinmux-ids = <
604 MX28_PAD_PWM2__PWM_2
605 >;
606 fsl,drive-strength = <MXS_DRIVE_4mA>;
607 fsl,voltage = <MXS_VOLTAGE_HIGH>;
608 fsl,pull-up = <MXS_PULL_DISABLE>;
609 };
610
611 pwm3_pins_a: pwm3@0 {
612 reg = <0>;
613 fsl,pinmux-ids = <
614 MX28_PAD_PWM3__PWM_3
615 >;
616 fsl,drive-strength = <MXS_DRIVE_4mA>;
617 fsl,voltage = <MXS_VOLTAGE_HIGH>;
618 fsl,pull-up = <MXS_PULL_DISABLE>;
619 };
620
621 pwm3_pins_b: pwm3@1 {
622 reg = <1>;
623 fsl,pinmux-ids = <
624 MX28_PAD_SAIF0_MCLK__PWM_3
625 >;
626 fsl,drive-strength = <MXS_DRIVE_4mA>;
627 fsl,voltage = <MXS_VOLTAGE_HIGH>;
628 fsl,pull-up = <MXS_PULL_DISABLE>;
629 };
630
631 pwm4_pins_a: pwm4@0 {
632 reg = <0>;
633 fsl,pinmux-ids = <
634 MX28_PAD_PWM4__PWM_4
635 >;
636 fsl,drive-strength = <MXS_DRIVE_4mA>;
637 fsl,voltage = <MXS_VOLTAGE_HIGH>;
638 fsl,pull-up = <MXS_PULL_DISABLE>;
639 };
640
641 lcdif_24bit_pins_a: lcdif-24bit@0 {
642 reg = <0>;
643 fsl,pinmux-ids = <
644 MX28_PAD_LCD_D00__LCD_D0
645 MX28_PAD_LCD_D01__LCD_D1
646 MX28_PAD_LCD_D02__LCD_D2
647 MX28_PAD_LCD_D03__LCD_D3
648 MX28_PAD_LCD_D04__LCD_D4
649 MX28_PAD_LCD_D05__LCD_D5
650 MX28_PAD_LCD_D06__LCD_D6
651 MX28_PAD_LCD_D07__LCD_D7
652 MX28_PAD_LCD_D08__LCD_D8
653 MX28_PAD_LCD_D09__LCD_D9
654 MX28_PAD_LCD_D10__LCD_D10
655 MX28_PAD_LCD_D11__LCD_D11
656 MX28_PAD_LCD_D12__LCD_D12
657 MX28_PAD_LCD_D13__LCD_D13
658 MX28_PAD_LCD_D14__LCD_D14
659 MX28_PAD_LCD_D15__LCD_D15
660 MX28_PAD_LCD_D16__LCD_D16
661 MX28_PAD_LCD_D17__LCD_D17
662 MX28_PAD_LCD_D18__LCD_D18
663 MX28_PAD_LCD_D19__LCD_D19
664 MX28_PAD_LCD_D20__LCD_D20
665 MX28_PAD_LCD_D21__LCD_D21
666 MX28_PAD_LCD_D22__LCD_D22
667 MX28_PAD_LCD_D23__LCD_D23
668 >;
669 fsl,drive-strength = <MXS_DRIVE_4mA>;
670 fsl,voltage = <MXS_VOLTAGE_HIGH>;
671 fsl,pull-up = <MXS_PULL_DISABLE>;
672 };
673
674 lcdif_18bit_pins_a: lcdif-18bit@0 {
675 reg = <0>;
676 fsl,pinmux-ids = <
677 MX28_PAD_LCD_D00__LCD_D0
678 MX28_PAD_LCD_D01__LCD_D1
679 MX28_PAD_LCD_D02__LCD_D2
680 MX28_PAD_LCD_D03__LCD_D3
681 MX28_PAD_LCD_D04__LCD_D4
682 MX28_PAD_LCD_D05__LCD_D5
683 MX28_PAD_LCD_D06__LCD_D6
684 MX28_PAD_LCD_D07__LCD_D7
685 MX28_PAD_LCD_D08__LCD_D8
686 MX28_PAD_LCD_D09__LCD_D9
687 MX28_PAD_LCD_D10__LCD_D10
688 MX28_PAD_LCD_D11__LCD_D11
689 MX28_PAD_LCD_D12__LCD_D12
690 MX28_PAD_LCD_D13__LCD_D13
691 MX28_PAD_LCD_D14__LCD_D14
692 MX28_PAD_LCD_D15__LCD_D15
693 MX28_PAD_LCD_D16__LCD_D16
694 MX28_PAD_LCD_D17__LCD_D17
695 >;
696 fsl,drive-strength = <MXS_DRIVE_4mA>;
697 fsl,voltage = <MXS_VOLTAGE_HIGH>;
698 fsl,pull-up = <MXS_PULL_DISABLE>;
699 };
700
701 lcdif_16bit_pins_a: lcdif-16bit@0 {
702 reg = <0>;
703 fsl,pinmux-ids = <
704 MX28_PAD_LCD_D00__LCD_D0
705 MX28_PAD_LCD_D01__LCD_D1
706 MX28_PAD_LCD_D02__LCD_D2
707 MX28_PAD_LCD_D03__LCD_D3
708 MX28_PAD_LCD_D04__LCD_D4
709 MX28_PAD_LCD_D05__LCD_D5
710 MX28_PAD_LCD_D06__LCD_D6
711 MX28_PAD_LCD_D07__LCD_D7
712 MX28_PAD_LCD_D08__LCD_D8
713 MX28_PAD_LCD_D09__LCD_D9
714 MX28_PAD_LCD_D10__LCD_D10
715 MX28_PAD_LCD_D11__LCD_D11
716 MX28_PAD_LCD_D12__LCD_D12
717 MX28_PAD_LCD_D13__LCD_D13
718 MX28_PAD_LCD_D14__LCD_D14
719 MX28_PAD_LCD_D15__LCD_D15
720 >;
721 fsl,drive-strength = <MXS_DRIVE_4mA>;
722 fsl,voltage = <MXS_VOLTAGE_HIGH>;
723 fsl,pull-up = <MXS_PULL_DISABLE>;
724 };
725
726 lcdif_sync_pins_a: lcdif-sync@0 {
727 reg = <0>;
728 fsl,pinmux-ids = <
729 MX28_PAD_LCD_RS__LCD_DOTCLK
730 MX28_PAD_LCD_CS__LCD_ENABLE
731 MX28_PAD_LCD_RD_E__LCD_VSYNC
732 MX28_PAD_LCD_WR_RWN__LCD_HSYNC
733 >;
734 fsl,drive-strength = <MXS_DRIVE_4mA>;
735 fsl,voltage = <MXS_VOLTAGE_HIGH>;
736 fsl,pull-up = <MXS_PULL_DISABLE>;
737 };
738
739 can0_pins_a: can0@0 {
740 reg = <0>;
741 fsl,pinmux-ids = <
742 MX28_PAD_GPMI_RDY2__CAN0_TX
743 MX28_PAD_GPMI_RDY3__CAN0_RX
744 >;
745 fsl,drive-strength = <MXS_DRIVE_4mA>;
746 fsl,voltage = <MXS_VOLTAGE_HIGH>;
747 fsl,pull-up = <MXS_PULL_DISABLE>;
748 };
749
750 can1_pins_a: can1@0 {
751 reg = <0>;
752 fsl,pinmux-ids = <
753 MX28_PAD_GPMI_CE2N__CAN1_TX
754 MX28_PAD_GPMI_CE3N__CAN1_RX
755 >;
756 fsl,drive-strength = <MXS_DRIVE_4mA>;
757 fsl,voltage = <MXS_VOLTAGE_HIGH>;
758 fsl,pull-up = <MXS_PULL_DISABLE>;
759 };
760
761 spi2_pins_a: spi2@0 {
762 reg = <0>;
763 fsl,pinmux-ids = <
764 MX28_PAD_SSP2_SCK__SSP2_SCK
765 MX28_PAD_SSP2_MOSI__SSP2_CMD
766 MX28_PAD_SSP2_MISO__SSP2_D0
767 MX28_PAD_SSP2_SS0__SSP2_D3
768 >;
769 fsl,drive-strength = <MXS_DRIVE_8mA>;
770 fsl,voltage = <MXS_VOLTAGE_HIGH>;
771 fsl,pull-up = <MXS_PULL_ENABLE>;
772 };
773
774 spi3_pins_a: spi3@0 {
775 reg = <0>;
776 fsl,pinmux-ids = <
777 MX28_PAD_AUART2_RX__SSP3_D4
778 MX28_PAD_AUART2_TX__SSP3_D5
779 MX28_PAD_SSP3_SCK__SSP3_SCK
780 MX28_PAD_SSP3_MOSI__SSP3_CMD
781 MX28_PAD_SSP3_MISO__SSP3_D0
782 MX28_PAD_SSP3_SS0__SSP3_D3
783 >;
784 fsl,drive-strength = <MXS_DRIVE_8mA>;
785 fsl,voltage = <MXS_VOLTAGE_HIGH>;
786 fsl,pull-up = <MXS_PULL_DISABLE>;
787 };
788
789 usb0_pins_a: usb0@0 {
790 reg = <0>;
791 fsl,pinmux-ids = <
792 MX28_PAD_SSP2_SS2__USB0_OVERCURRENT
793 >;
794 fsl,drive-strength = <MXS_DRIVE_12mA>;
795 fsl,voltage = <MXS_VOLTAGE_HIGH>;
796 fsl,pull-up = <MXS_PULL_DISABLE>;
797 };
798
799 usb0_pins_b: usb0@1 {
800 reg = <1>;
801 fsl,pinmux-ids = <
802 MX28_PAD_AUART1_CTS__USB0_OVERCURRENT
803 >;
804 fsl,drive-strength = <MXS_DRIVE_12mA>;
805 fsl,voltage = <MXS_VOLTAGE_HIGH>;
806 fsl,pull-up = <MXS_PULL_DISABLE>;
807 };
808
809 usb1_pins_a: usb1@0 {
810 reg = <0>;
811 fsl,pinmux-ids = <
812 MX28_PAD_SSP2_SS1__USB1_OVERCURRENT
813 >;
814 fsl,drive-strength = <MXS_DRIVE_12mA>;
815 fsl,voltage = <MXS_VOLTAGE_HIGH>;
816 fsl,pull-up = <MXS_PULL_DISABLE>;
817 };
818
819 usb0_id_pins_a: usb0id@0 {
820 reg = <0>;
821 fsl,pinmux-ids = <
822 MX28_PAD_AUART1_RTS__USB0_ID
823 >;
824 fsl,drive-strength = <MXS_DRIVE_12mA>;
825 fsl,voltage = <MXS_VOLTAGE_HIGH>;
826 fsl,pull-up = <MXS_PULL_ENABLE>;
827 };
828
829 usb0_id_pins_b: usb0id1@0 {
830 reg = <0>;
831 fsl,pinmux-ids = <
832 MX28_PAD_PWM2__USB0_ID
833 >;
834 fsl,drive-strength = <MXS_DRIVE_12mA>;
835 fsl,voltage = <MXS_VOLTAGE_HIGH>;
836 fsl,pull-up = <MXS_PULL_ENABLE>;
837 };
838
839 };
840
841 digctl: digctl@8001c000 {
842 compatible = "fsl,imx28-digctl", "fsl,imx23-digctl";
843 reg = <0x8001c000 0x2000>;
844 interrupts = <89>;
845 status = "disabled";
846 };
847
848 etm: etm@80022000 {
849 reg = <0x80022000 0x2000>;
850 status = "disabled";
851 };
852
853 dma_apbx: dma-apbx@80024000 {
854 compatible = "fsl,imx28-dma-apbx";
855 reg = <0x80024000 0x2000>;
856 interrupts = <78 79 66 0
857 80 81 68 69
858 70 71 72 73
859 74 75 76 77>;
860 interrupt-names = "auart4-rx", "aurat4-tx", "spdif-tx", "empty",
861 "saif0", "saif1", "i2c0", "i2c1",
862 "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
863 "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
864 #dma-cells = <1>;
865 dma-channels = <16>;
866 clocks = <&clks 26>;
867 };
868
869 dcp: dcp@80028000 {
870 compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
871 reg = <0x80028000 0x2000>;
872 interrupts = <52 53 54>;
873 status = "okay";
874 };
875
876 pxp: pxp@8002a000 {
877 reg = <0x8002a000 0x2000>;
878 interrupts = <39>;
879 status = "disabled";
880 };
881
882 ocotp: ocotp@8002c000 {
883 compatible = "fsl,ocotp";
884 reg = <0x8002c000 0x2000>;
885 status = "disabled";
886 };
887
888 axi-ahb@8002e000 {
889 reg = <0x8002e000 0x2000>;
890 status = "disabled";
891 };
892
893 lcdif: lcdif@80030000 {
894 compatible = "fsl,imx28-lcdif";
895 reg = <0x80030000 0x2000>;
896 interrupts = <38>;
897 clocks = <&clks 55>;
898 dmas = <&dma_apbh 13>;
899 dma-names = "rx";
900 status = "disabled";
901 };
902
903 can0: can@80032000 {
904 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
905 reg = <0x80032000 0x2000>;
906 interrupts = <8>;
907 clocks = <&clks 58>, <&clks 58>;
908 clock-names = "ipg", "per";
909 status = "disabled";
910 };
911
912 can1: can@80034000 {
913 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
914 reg = <0x80034000 0x2000>;
915 interrupts = <9>;
916 clocks = <&clks 59>, <&clks 59>;
917 clock-names = "ipg", "per";
918 status = "disabled";
919 };
920
921 simdbg: simdbg@8003c000 {
922 reg = <0x8003c000 0x200>;
923 status = "disabled";
924 };
925
926 simgpmisel: simgpmisel@8003c200 {
927 reg = <0x8003c200 0x100>;
928 status = "disabled";
929 };
930
931 simsspsel: simsspsel@8003c300 {
932 reg = <0x8003c300 0x100>;
933 status = "disabled";
934 };
935
936 simmemsel: simmemsel@8003c400 {
937 reg = <0x8003c400 0x100>;
938 status = "disabled";
939 };
940
941 gpiomon: gpiomon@8003c500 {
942 reg = <0x8003c500 0x100>;
943 status = "disabled";
944 };
945
946 simenet: simenet@8003c700 {
947 reg = <0x8003c700 0x100>;
948 status = "disabled";
949 };
950
951 armjtag: armjtag@8003c800 {
952 reg = <0x8003c800 0x100>;
953 status = "disabled";
954 };
955 };
956
957 apbx@80040000 {
958 compatible = "simple-bus";
959 #address-cells = <1>;
960 #size-cells = <1>;
961 reg = <0x80040000 0x40000>;
962 ranges;
963
964 clks: clkctrl@80040000 {
965 compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
966 reg = <0x80040000 0x2000>;
967 #clock-cells = <1>;
968 };
969
970 saif0: saif@80042000 {
971 compatible = "fsl,imx28-saif";
972 reg = <0x80042000 0x2000>;
973 interrupts = <59>;
974 #clock-cells = <0>;
975 clocks = <&clks 53>;
976 dmas = <&dma_apbx 4>;
977 dma-names = "rx-tx";
978 status = "disabled";
979 };
980
981 power: power@80044000 {
982 reg = <0x80044000 0x2000>;
983 status = "disabled";
984 };
985
986 saif1: saif@80046000 {
987 compatible = "fsl,imx28-saif";
988 reg = <0x80046000 0x2000>;
989 interrupts = <58>;
990 clocks = <&clks 54>;
991 dmas = <&dma_apbx 5>;
992 dma-names = "rx-tx";
993 status = "disabled";
994 };
995
996 lradc: lradc@80050000 {
997 compatible = "fsl,imx28-lradc";
998 reg = <0x80050000 0x2000>;
999 interrupts = <10 14 15 16 17 18 19
1000 20 21 22 23 24 25>;
1001 status = "disabled";
1002 clocks = <&clks 41>;
1003 #io-channel-cells = <1>;
1004 };
1005
1006 spdif: spdif@80054000 {
1007 reg = <0x80054000 0x2000>;
1008 interrupts = <45>;
1009 dmas = <&dma_apbx 2>;
1010 dma-names = "tx";
1011 status = "disabled";
1012 };
1013
1014 mxs_rtc: rtc@80056000 {
1015 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
1016 reg = <0x80056000 0x2000>;
1017 interrupts = <29>;
1018 };
1019
1020 i2c0: i2c@80058000 {
1021 #address-cells = <1>;
1022 #size-cells = <0>;
1023 compatible = "fsl,imx28-i2c";
1024 reg = <0x80058000 0x2000>;
1025 interrupts = <111>;
1026 clock-frequency = <100000>;
1027 dmas = <&dma_apbx 6>;
1028 dma-names = "rx-tx";
1029 status = "disabled";
1030 };
1031
1032 i2c1: i2c@8005a000 {
1033 #address-cells = <1>;
1034 #size-cells = <0>;
1035 compatible = "fsl,imx28-i2c";
1036 reg = <0x8005a000 0x2000>;
1037 interrupts = <110>;
1038 clock-frequency = <100000>;
1039 dmas = <&dma_apbx 7>;
1040 dma-names = "rx-tx";
1041 status = "disabled";
1042 };
1043
1044 pwm: pwm@80064000 {
1045 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
1046 reg = <0x80064000 0x2000>;
1047 clocks = <&clks 44>;
1048 #pwm-cells = <2>;
1049 fsl,pwm-number = <8>;
1050 status = "disabled";
1051 };
1052
1053 timer: timrot@80068000 {
1054 compatible = "fsl,imx28-timrot", "fsl,timrot";
1055 reg = <0x80068000 0x2000>;
1056 interrupts = <48 49 50 51>;
1057 clocks = <&clks 26>;
1058 };
1059
1060 auart0: serial@8006a000 {
1061 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1062 reg = <0x8006a000 0x2000>;
1063 interrupts = <112>;
1064 dmas = <&dma_apbx 8>, <&dma_apbx 9>;
1065 dma-names = "rx", "tx";
1066 clocks = <&clks 45>;
1067 status = "disabled";
1068 };
1069
1070 auart1: serial@8006c000 {
1071 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1072 reg = <0x8006c000 0x2000>;
1073 interrupts = <113>;
1074 dmas = <&dma_apbx 10>, <&dma_apbx 11>;
1075 dma-names = "rx", "tx";
1076 clocks = <&clks 45>;
1077 status = "disabled";
1078 };
1079
1080 auart2: serial@8006e000 {
1081 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1082 reg = <0x8006e000 0x2000>;
1083 interrupts = <114>;
1084 dmas = <&dma_apbx 12>, <&dma_apbx 13>;
1085 dma-names = "rx", "tx";
1086 clocks = <&clks 45>;
1087 status = "disabled";
1088 };
1089
1090 auart3: serial@80070000 {
1091 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1092 reg = <0x80070000 0x2000>;
1093 interrupts = <115>;
1094 dmas = <&dma_apbx 14>, <&dma_apbx 15>;
1095 dma-names = "rx", "tx";
1096 clocks = <&clks 45>;
1097 status = "disabled";
1098 };
1099
1100 auart4: serial@80072000 {
1101 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1102 reg = <0x80072000 0x2000>;
1103 interrupts = <116>;
1104 dmas = <&dma_apbx 0>, <&dma_apbx 1>;
1105 dma-names = "rx", "tx";
1106 clocks = <&clks 45>;
1107 status = "disabled";
1108 };
1109
1110 duart: serial@80074000 {
1111 compatible = "arm,pl011", "arm,primecell";
1112 reg = <0x80074000 0x1000>;
1113 interrupts = <47>;
1114 clocks = <&clks 45>, <&clks 26>;
1115 clock-names = "uart", "apb_pclk";
1116 status = "disabled";
1117 };
1118
1119 usbphy0: usbphy@8007c000 {
1120 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
1121 reg = <0x8007c000 0x2000>;
1122 clocks = <&clks 62>;
1123 status = "disabled";
1124 };
1125
1126 usbphy1: usbphy@8007e000 {
1127 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
1128 reg = <0x8007e000 0x2000>;
1129 clocks = <&clks 63>;
1130 status = "disabled";
1131 };
1132 };
1133 };
1134
1135 ahb@80080000 {
1136 compatible = "simple-bus";
1137 #address-cells = <1>;
1138 #size-cells = <1>;
1139 reg = <0x80080000 0x80000>;
1140 ranges;
1141
1142 usb0: usb@80080000 {
1143 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
1144 reg = <0x80080000 0x10000>;
1145 interrupts = <93>;
1146 clocks = <&clks 60>;
1147 fsl,usbphy = <&usbphy0>;
1148 status = "disabled";
1149 };
1150
1151 usb1: usb@80090000 {
1152 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
1153 reg = <0x80090000 0x10000>;
1154 interrupts = <92>;
1155 clocks = <&clks 61>;
1156 fsl,usbphy = <&usbphy1>;
1157 status = "disabled";
1158 };
1159
1160 dflpt: dflpt@800c0000 {
1161 reg = <0x800c0000 0x10000>;
1162 status = "disabled";
1163 };
1164
1165 mac0: ethernet@800f0000 {
1166 compatible = "fsl,imx28-fec";
1167 reg = <0x800f0000 0x4000>;
1168 interrupts = <101>;
1169 clocks = <&clks 57>, <&clks 57>, <&clks 64>;
1170 clock-names = "ipg", "ahb", "enet_out";
1171 status = "disabled";
1172 };
1173
1174 mac1: ethernet@800f4000 {
1175 compatible = "fsl,imx28-fec";
1176 reg = <0x800f4000 0x4000>;
1177 interrupts = <102>;
1178 clocks = <&clks 57>, <&clks 57>;
1179 clock-names = "ipg", "ahb";
1180 status = "disabled";
1181 };
1182
1183 etn_switch: switch@800f8000 {
1184 reg = <0x800f8000 0x8000>;
1185 status = "disabled";
1186 };
1187 };
1188
1189 iio_hwmon {
1190 compatible = "iio-hwmon";
1191 io-channels = <&lradc 8>;
1192 };
1193 };
Linux kernel - Deliverables
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