6ff15a0eacb3ccfcb52ce450b189f6e0ebc51aa7
[deliverable/linux.git] / arch / arm / boot / dts / imx51-babbage.dts
1 /*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13 /dts-v1/;
14 #include "imx51.dtsi"
15
16 / {
17 model = "Freescale i.MX51 Babbage Board";
18 compatible = "fsl,imx51-babbage", "fsl,imx51";
19
20 memory {
21 reg = <0x90000000 0x20000000>;
22 };
23
24 display0: display@di0 {
25 compatible = "fsl,imx-parallel-display";
26 crtcs = <&ipu 0>;
27 interface-pix-fmt = "rgb24";
28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_ipu_disp1_1>;
30 display-timings {
31 native-mode = <&timing0>;
32 timing0: dvi {
33 clock-frequency = <65000000>;
34 hactive = <1024>;
35 vactive = <768>;
36 hback-porch = <220>;
37 hfront-porch = <40>;
38 vback-porch = <21>;
39 vfront-porch = <7>;
40 hsync-len = <60>;
41 vsync-len = <10>;
42 };
43 };
44 };
45
46 display1: display@di1 {
47 compatible = "fsl,imx-parallel-display";
48 crtcs = <&ipu 1>;
49 interface-pix-fmt = "rgb565";
50 pinctrl-names = "default";
51 pinctrl-0 = <&pinctrl_ipu_disp2_1>;
52 status = "disabled";
53 display-timings {
54 native-mode = <&timing1>;
55 timing1: claawvga {
56 clock-frequency = <27000000>;
57 hactive = <800>;
58 vactive = <480>;
59 hback-porch = <40>;
60 hfront-porch = <60>;
61 vback-porch = <10>;
62 vfront-porch = <10>;
63 hsync-len = <20>;
64 vsync-len = <10>;
65 hsync-active = <0>;
66 vsync-active = <0>;
67 de-active = <1>;
68 pixelclk-active = <0>;
69 };
70 };
71 };
72
73 gpio-keys {
74 compatible = "gpio-keys";
75
76 power {
77 label = "Power Button";
78 gpios = <&gpio2 21 0>;
79 linux,code = <116>; /* KEY_POWER */
80 gpio-key,wakeup;
81 };
82 };
83
84 imx-drm {
85 compatible = "fsl,imx-drm";
86 crtcs = <&ipu 0>, <&ipu 1>;
87 connectors = <&display0>, <&display1>;
88 };
89
90 sound {
91 compatible = "fsl,imx51-babbage-sgtl5000",
92 "fsl,imx-audio-sgtl5000";
93 model = "imx51-babbage-sgtl5000";
94 ssi-controller = <&ssi2>;
95 audio-codec = <&sgtl5000>;
96 audio-routing =
97 "MIC_IN", "Mic Jack",
98 "Mic Jack", "Mic Bias",
99 "Headphone Jack", "HP_OUT";
100 mux-int-port = <2>;
101 mux-ext-port = <3>;
102 };
103
104 clocks {
105 ckih1 {
106 clock-frequency = <22579200>;
107 };
108
109 clk_26M: codec_clock {
110 compatible = "fixed-clock";
111 reg=<0>;
112 #clock-cells = <0>;
113 clock-frequency = <26000000>;
114 gpios = <&gpio4 26 1>;
115 };
116 };
117 };
118
119 &esdhc1 {
120 pinctrl-names = "default";
121 pinctrl-0 = <&pinctrl_esdhc1_1>;
122 fsl,cd-controller;
123 fsl,wp-controller;
124 status = "okay";
125 };
126
127 &esdhc2 {
128 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_esdhc2_1>;
130 cd-gpios = <&gpio1 6 0>;
131 wp-gpios = <&gpio1 5 0>;
132 status = "okay";
133 };
134
135 &uart3 {
136 pinctrl-names = "default";
137 pinctrl-0 = <&pinctrl_uart3_1 &pinctrl_uart3_rtscts_1>;
138 fsl,uart-has-rtscts;
139 status = "okay";
140 };
141
142 &ecspi1 {
143 pinctrl-names = "default";
144 pinctrl-0 = <&pinctrl_ecspi1_1>;
145 fsl,spi-num-chipselects = <2>;
146 cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;
147 status = "okay";
148
149 pmic: mc13892@0 {
150 #address-cells = <1>;
151 #size-cells = <0>;
152 compatible = "fsl,mc13892";
153 spi-max-frequency = <6000000>;
154 spi-cs-high;
155 reg = <0>;
156 interrupt-parent = <&gpio1>;
157 interrupts = <8 0x4>;
158
159 regulators {
160 sw1_reg: sw1 {
161 regulator-min-microvolt = <600000>;
162 regulator-max-microvolt = <1375000>;
163 regulator-boot-on;
164 regulator-always-on;
165 };
166
167 sw2_reg: sw2 {
168 regulator-min-microvolt = <900000>;
169 regulator-max-microvolt = <1850000>;
170 regulator-boot-on;
171 regulator-always-on;
172 };
173
174 sw3_reg: sw3 {
175 regulator-min-microvolt = <1100000>;
176 regulator-max-microvolt = <1850000>;
177 regulator-boot-on;
178 regulator-always-on;
179 };
180
181 sw4_reg: sw4 {
182 regulator-min-microvolt = <1100000>;
183 regulator-max-microvolt = <1850000>;
184 regulator-boot-on;
185 regulator-always-on;
186 };
187
188 vpll_reg: vpll {
189 regulator-min-microvolt = <1050000>;
190 regulator-max-microvolt = <1800000>;
191 regulator-boot-on;
192 regulator-always-on;
193 };
194
195 vdig_reg: vdig {
196 regulator-min-microvolt = <1650000>;
197 regulator-max-microvolt = <1650000>;
198 regulator-boot-on;
199 };
200
201 vsd_reg: vsd {
202 regulator-min-microvolt = <1800000>;
203 regulator-max-microvolt = <3150000>;
204 };
205
206 vusb2_reg: vusb2 {
207 regulator-min-microvolt = <2400000>;
208 regulator-max-microvolt = <2775000>;
209 regulator-boot-on;
210 regulator-always-on;
211 };
212
213 vvideo_reg: vvideo {
214 regulator-min-microvolt = <2775000>;
215 regulator-max-microvolt = <2775000>;
216 };
217
218 vaudio_reg: vaudio {
219 regulator-min-microvolt = <2300000>;
220 regulator-max-microvolt = <3000000>;
221 };
222
223 vcam_reg: vcam {
224 regulator-min-microvolt = <2500000>;
225 regulator-max-microvolt = <3000000>;
226 };
227
228 vgen1_reg: vgen1 {
229 regulator-min-microvolt = <1200000>;
230 regulator-max-microvolt = <1200000>;
231 };
232
233 vgen2_reg: vgen2 {
234 regulator-min-microvolt = <1200000>;
235 regulator-max-microvolt = <3150000>;
236 regulator-always-on;
237 };
238
239 vgen3_reg: vgen3 {
240 regulator-min-microvolt = <1800000>;
241 regulator-max-microvolt = <2900000>;
242 regulator-always-on;
243 };
244 };
245 };
246
247 flash: at45db321d@1 {
248 #address-cells = <1>;
249 #size-cells = <1>;
250 compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
251 spi-max-frequency = <25000000>;
252 reg = <1>;
253
254 partition@0 {
255 label = "U-Boot";
256 reg = <0x0 0x40000>;
257 read-only;
258 };
259
260 partition@40000 {
261 label = "Kernel";
262 reg = <0x40000 0x3c0000>;
263 };
264 };
265 };
266
267 &ssi2 {
268 fsl,mode = "i2s-slave";
269 status = "okay";
270 };
271
272 &iomuxc {
273 pinctrl-names = "default";
274 pinctrl-0 = <&pinctrl_hog>;
275
276 hog {
277 pinctrl_hog: hoggrp {
278 fsl,pins = <
279 MX51_PAD_GPIO1_0__SD1_CD 0x20d5
280 MX51_PAD_GPIO1_1__SD1_WP 0x20d5
281 MX51_PAD_GPIO1_5__GPIO1_5 0x100
282 MX51_PAD_GPIO1_6__GPIO1_6 0x100
283 MX51_PAD_EIM_A27__GPIO2_21 0x5
284 MX51_PAD_CSPI1_SS0__GPIO4_24 0x85
285 MX51_PAD_CSPI1_SS1__GPIO4_25 0x85
286 MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000
287 >;
288 };
289 };
290 };
291
292 &uart1 {
293 pinctrl-names = "default";
294 pinctrl-0 = <&pinctrl_uart1_1 &pinctrl_uart1_rtscts_1>;
295 fsl,uart-has-rtscts;
296 status = "okay";
297 };
298
299 &uart2 {
300 pinctrl-names = "default";
301 pinctrl-0 = <&pinctrl_uart2_1>;
302 status = "okay";
303 };
304
305 &i2c2 {
306 pinctrl-names = "default";
307 pinctrl-0 = <&pinctrl_i2c2_1>;
308 status = "okay";
309
310 sgtl5000: codec@0a {
311 compatible = "fsl,sgtl5000";
312 reg = <0x0a>;
313 clocks = <&clk_26M>;
314 VDDA-supply = <&vdig_reg>;
315 VDDIO-supply = <&vvideo_reg>;
316 };
317 };
318
319 &audmux {
320 pinctrl-names = "default";
321 pinctrl-0 = <&pinctrl_audmux_1>;
322 status = "okay";
323 };
324
325 &fec {
326 pinctrl-names = "default";
327 pinctrl-0 = <&pinctrl_fec_1>;
328 phy-mode = "mii";
329 status = "okay";
330 };
331
332 &kpp {
333 pinctrl-names = "default";
334 pinctrl-0 = <&pinctrl_kpp_1>;
335 linux,keymap = <0x00000067 /* KEY_UP */
336 0x0001006c /* KEY_DOWN */
337 0x00020072 /* KEY_VOLUMEDOWN */
338 0x00030066 /* KEY_HOME */
339 0x0100006a /* KEY_RIGHT */
340 0x01010069 /* KEY_LEFT */
341 0x0102001c /* KEY_ENTER */
342 0x01030073 /* KEY_VOLUMEUP */
343 0x02000040 /* KEY_F6 */
344 0x02010042 /* KEY_F8 */
345 0x02020043 /* KEY_F9 */
346 0x02030044 /* KEY_F10 */
347 0x0300003b /* KEY_F1 */
348 0x0301003c /* KEY_F2 */
349 0x0302003d /* KEY_F3 */
350 0x03030074>; /* KEY_POWER */
351 status = "okay";
352 };
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