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ARM: dts: STi: STih407: Switch LPC mode from RTC to Clocksource
[deliverable/linux.git] / arch / arm / boot / dts / imx51.dtsi
1 /*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13 #include "skeleton.dtsi"
14 #include "imx51-pinfunc.h"
15 #include <dt-bindings/clock/imx5-clock.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/input/input.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
19
20 / {
21 aliases {
22 ethernet0 = &fec;
23 gpio0 = &gpio1;
24 gpio1 = &gpio2;
25 gpio2 = &gpio3;
26 gpio3 = &gpio4;
27 i2c0 = &i2c1;
28 i2c1 = &i2c2;
29 mmc0 = &esdhc1;
30 mmc1 = &esdhc2;
31 mmc2 = &esdhc3;
32 mmc3 = &esdhc4;
33 serial0 = &uart1;
34 serial1 = &uart2;
35 serial2 = &uart3;
36 spi0 = &ecspi1;
37 spi1 = &ecspi2;
38 spi2 = &cspi;
39 };
40
41 tzic: tz-interrupt-controller@e0000000 {
42 compatible = "fsl,imx51-tzic", "fsl,tzic";
43 interrupt-controller;
44 #interrupt-cells = <1>;
45 reg = <0xe0000000 0x4000>;
46 };
47
48 clocks {
49 #address-cells = <1>;
50 #size-cells = <0>;
51
52 ckil {
53 compatible = "fsl,imx-ckil", "fixed-clock";
54 #clock-cells = <0>;
55 clock-frequency = <32768>;
56 };
57
58 ckih1 {
59 compatible = "fsl,imx-ckih1", "fixed-clock";
60 #clock-cells = <0>;
61 clock-frequency = <0>;
62 };
63
64 ckih2 {
65 compatible = "fsl,imx-ckih2", "fixed-clock";
66 #clock-cells = <0>;
67 clock-frequency = <0>;
68 };
69
70 osc {
71 compatible = "fsl,imx-osc", "fixed-clock";
72 #clock-cells = <0>;
73 clock-frequency = <24000000>;
74 };
75 };
76
77 cpus {
78 #address-cells = <1>;
79 #size-cells = <0>;
80 cpu: cpu@0 {
81 device_type = "cpu";
82 compatible = "arm,cortex-a8";
83 reg = <0>;
84 clock-latency = <62500>;
85 clocks = <&clks IMX5_CLK_CPU_PODF>;
86 clock-names = "cpu";
87 operating-points = <
88 166000 1000000
89 600000 1050000
90 800000 1100000
91 >;
92 voltage-tolerance = <5>;
93 };
94 };
95
96 usbphy {
97 #address-cells = <1>;
98 #size-cells = <0>;
99 compatible = "simple-bus";
100
101 usbphy0: usbphy@0 {
102 compatible = "usb-nop-xceiv";
103 reg = <0>;
104 clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
105 clock-names = "main_clk";
106 };
107 };
108
109 display-subsystem {
110 compatible = "fsl,imx-display-subsystem";
111 ports = <&ipu_di0>, <&ipu_di1>;
112 };
113
114 soc {
115 #address-cells = <1>;
116 #size-cells = <1>;
117 compatible = "simple-bus";
118 interrupt-parent = <&tzic>;
119 ranges;
120
121 iram: iram@1ffe0000 {
122 compatible = "mmio-sram";
123 reg = <0x1ffe0000 0x20000>;
124 };
125
126 ipu: ipu@40000000 {
127 #address-cells = <1>;
128 #size-cells = <0>;
129 compatible = "fsl,imx51-ipu";
130 reg = <0x40000000 0x20000000>;
131 interrupts = <11 10>;
132 clocks = <&clks IMX5_CLK_IPU_GATE>,
133 <&clks IMX5_CLK_IPU_DI0_GATE>,
134 <&clks IMX5_CLK_IPU_DI1_GATE>;
135 clock-names = "bus", "di0", "di1";
136 resets = <&src 2>;
137
138 ipu_di0: port@2 {
139 reg = <2>;
140
141 ipu_di0_disp0: endpoint {
142 };
143 };
144
145 ipu_di1: port@3 {
146 reg = <3>;
147
148 ipu_di1_disp1: endpoint {
149 };
150 };
151 };
152
153 aips@70000000 { /* AIPS1 */
154 compatible = "fsl,aips-bus", "simple-bus";
155 #address-cells = <1>;
156 #size-cells = <1>;
157 reg = <0x70000000 0x10000000>;
158 ranges;
159
160 spba@70000000 {
161 compatible = "fsl,spba-bus", "simple-bus";
162 #address-cells = <1>;
163 #size-cells = <1>;
164 reg = <0x70000000 0x40000>;
165 ranges;
166
167 esdhc1: esdhc@70004000 {
168 compatible = "fsl,imx51-esdhc";
169 reg = <0x70004000 0x4000>;
170 interrupts = <1>;
171 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
172 <&clks IMX5_CLK_DUMMY>,
173 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
174 clock-names = "ipg", "ahb", "per";
175 status = "disabled";
176 };
177
178 esdhc2: esdhc@70008000 {
179 compatible = "fsl,imx51-esdhc";
180 reg = <0x70008000 0x4000>;
181 interrupts = <2>;
182 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
183 <&clks IMX5_CLK_DUMMY>,
184 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
185 clock-names = "ipg", "ahb", "per";
186 bus-width = <4>;
187 status = "disabled";
188 };
189
190 uart3: serial@7000c000 {
191 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
192 reg = <0x7000c000 0x4000>;
193 interrupts = <33>;
194 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
195 <&clks IMX5_CLK_UART3_PER_GATE>;
196 clock-names = "ipg", "per";
197 status = "disabled";
198 };
199
200 ecspi1: ecspi@70010000 {
201 #address-cells = <1>;
202 #size-cells = <0>;
203 compatible = "fsl,imx51-ecspi";
204 reg = <0x70010000 0x4000>;
205 interrupts = <36>;
206 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
207 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
208 clock-names = "ipg", "per";
209 status = "disabled";
210 };
211
212 ssi2: ssi@70014000 {
213 #sound-dai-cells = <0>;
214 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
215 reg = <0x70014000 0x4000>;
216 interrupts = <30>;
217 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
218 <&clks IMX5_CLK_SSI2_ROOT_GATE>;
219 clock-names = "ipg", "baud";
220 dmas = <&sdma 24 1 0>,
221 <&sdma 25 1 0>;
222 dma-names = "rx", "tx";
223 fsl,fifo-depth = <15>;
224 status = "disabled";
225 };
226
227 esdhc3: esdhc@70020000 {
228 compatible = "fsl,imx51-esdhc";
229 reg = <0x70020000 0x4000>;
230 interrupts = <3>;
231 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
232 <&clks IMX5_CLK_DUMMY>,
233 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
234 clock-names = "ipg", "ahb", "per";
235 bus-width = <4>;
236 status = "disabled";
237 };
238
239 esdhc4: esdhc@70024000 {
240 compatible = "fsl,imx51-esdhc";
241 reg = <0x70024000 0x4000>;
242 interrupts = <4>;
243 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
244 <&clks IMX5_CLK_DUMMY>,
245 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
246 clock-names = "ipg", "ahb", "per";
247 bus-width = <4>;
248 status = "disabled";
249 };
250 };
251
252 usbotg: usb@73f80000 {
253 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
254 reg = <0x73f80000 0x0200>;
255 interrupts = <18>;
256 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
257 fsl,usbmisc = <&usbmisc 0>;
258 fsl,usbphy = <&usbphy0>;
259 status = "disabled";
260 };
261
262 usbh1: usb@73f80200 {
263 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
264 reg = <0x73f80200 0x0200>;
265 interrupts = <14>;
266 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
267 fsl,usbmisc = <&usbmisc 1>;
268 dr_mode = "host";
269 status = "disabled";
270 };
271
272 usbh2: usb@73f80400 {
273 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
274 reg = <0x73f80400 0x0200>;
275 interrupts = <16>;
276 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
277 fsl,usbmisc = <&usbmisc 2>;
278 dr_mode = "host";
279 status = "disabled";
280 };
281
282 usbh3: usb@73f80600 {
283 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
284 reg = <0x73f80600 0x0200>;
285 interrupts = <17>;
286 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
287 fsl,usbmisc = <&usbmisc 3>;
288 dr_mode = "host";
289 status = "disabled";
290 };
291
292 usbmisc: usbmisc@73f80800 {
293 #index-cells = <1>;
294 compatible = "fsl,imx51-usbmisc";
295 reg = <0x73f80800 0x200>;
296 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
297 };
298
299 gpio1: gpio@73f84000 {
300 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
301 reg = <0x73f84000 0x4000>;
302 interrupts = <50 51>;
303 gpio-controller;
304 #gpio-cells = <2>;
305 interrupt-controller;
306 #interrupt-cells = <2>;
307 };
308
309 gpio2: gpio@73f88000 {
310 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
311 reg = <0x73f88000 0x4000>;
312 interrupts = <52 53>;
313 gpio-controller;
314 #gpio-cells = <2>;
315 interrupt-controller;
316 #interrupt-cells = <2>;
317 };
318
319 gpio3: gpio@73f8c000 {
320 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
321 reg = <0x73f8c000 0x4000>;
322 interrupts = <54 55>;
323 gpio-controller;
324 #gpio-cells = <2>;
325 interrupt-controller;
326 #interrupt-cells = <2>;
327 };
328
329 gpio4: gpio@73f90000 {
330 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
331 reg = <0x73f90000 0x4000>;
332 interrupts = <56 57>;
333 gpio-controller;
334 #gpio-cells = <2>;
335 interrupt-controller;
336 #interrupt-cells = <2>;
337 };
338
339 kpp: kpp@73f94000 {
340 compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
341 reg = <0x73f94000 0x4000>;
342 interrupts = <60>;
343 clocks = <&clks IMX5_CLK_DUMMY>;
344 status = "disabled";
345 };
346
347 wdog1: wdog@73f98000 {
348 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
349 reg = <0x73f98000 0x4000>;
350 interrupts = <58>;
351 clocks = <&clks IMX5_CLK_DUMMY>;
352 };
353
354 wdog2: wdog@73f9c000 {
355 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
356 reg = <0x73f9c000 0x4000>;
357 interrupts = <59>;
358 clocks = <&clks IMX5_CLK_DUMMY>;
359 status = "disabled";
360 };
361
362 gpt: timer@73fa0000 {
363 compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
364 reg = <0x73fa0000 0x4000>;
365 interrupts = <39>;
366 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
367 <&clks IMX5_CLK_GPT_HF_GATE>;
368 clock-names = "ipg", "per";
369 };
370
371 iomuxc: iomuxc@73fa8000 {
372 compatible = "fsl,imx51-iomuxc";
373 reg = <0x73fa8000 0x4000>;
374 };
375
376 pwm1: pwm@73fb4000 {
377 #pwm-cells = <2>;
378 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
379 reg = <0x73fb4000 0x4000>;
380 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
381 <&clks IMX5_CLK_PWM1_HF_GATE>;
382 clock-names = "ipg", "per";
383 interrupts = <61>;
384 };
385
386 pwm2: pwm@73fb8000 {
387 #pwm-cells = <2>;
388 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
389 reg = <0x73fb8000 0x4000>;
390 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
391 <&clks IMX5_CLK_PWM2_HF_GATE>;
392 clock-names = "ipg", "per";
393 interrupts = <94>;
394 };
395
396 uart1: serial@73fbc000 {
397 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
398 reg = <0x73fbc000 0x4000>;
399 interrupts = <31>;
400 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
401 <&clks IMX5_CLK_UART1_PER_GATE>;
402 clock-names = "ipg", "per";
403 status = "disabled";
404 };
405
406 uart2: serial@73fc0000 {
407 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
408 reg = <0x73fc0000 0x4000>;
409 interrupts = <32>;
410 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
411 <&clks IMX5_CLK_UART2_PER_GATE>;
412 clock-names = "ipg", "per";
413 status = "disabled";
414 };
415
416 src: src@73fd0000 {
417 compatible = "fsl,imx51-src";
418 reg = <0x73fd0000 0x4000>;
419 #reset-cells = <1>;
420 };
421
422 clks: ccm@73fd4000{
423 compatible = "fsl,imx51-ccm";
424 reg = <0x73fd4000 0x4000>;
425 interrupts = <0 71 0x04 0 72 0x04>;
426 #clock-cells = <1>;
427 };
428 };
429
430 aips@80000000 { /* AIPS2 */
431 compatible = "fsl,aips-bus", "simple-bus";
432 #address-cells = <1>;
433 #size-cells = <1>;
434 reg = <0x80000000 0x10000000>;
435 ranges;
436
437 iim: iim@83f98000 {
438 compatible = "fsl,imx51-iim", "fsl,imx27-iim";
439 reg = <0x83f98000 0x4000>;
440 interrupts = <69>;
441 clocks = <&clks IMX5_CLK_IIM_GATE>;
442 };
443
444 owire: owire@83fa4000 {
445 compatible = "fsl,imx51-owire", "fsl,imx21-owire";
446 reg = <0x83fa4000 0x4000>;
447 interrupts = <88>;
448 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
449 status = "disabled";
450 };
451
452 ecspi2: ecspi@83fac000 {
453 #address-cells = <1>;
454 #size-cells = <0>;
455 compatible = "fsl,imx51-ecspi";
456 reg = <0x83fac000 0x4000>;
457 interrupts = <37>;
458 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
459 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
460 clock-names = "ipg", "per";
461 status = "disabled";
462 };
463
464 sdma: sdma@83fb0000 {
465 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
466 reg = <0x83fb0000 0x4000>;
467 interrupts = <6>;
468 clocks = <&clks IMX5_CLK_SDMA_GATE>,
469 <&clks IMX5_CLK_SDMA_GATE>;
470 clock-names = "ipg", "ahb";
471 #dma-cells = <3>;
472 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
473 };
474
475 cspi: cspi@83fc0000 {
476 #address-cells = <1>;
477 #size-cells = <0>;
478 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
479 reg = <0x83fc0000 0x4000>;
480 interrupts = <38>;
481 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
482 <&clks IMX5_CLK_CSPI_IPG_GATE>;
483 clock-names = "ipg", "per";
484 status = "disabled";
485 };
486
487 i2c2: i2c@83fc4000 {
488 #address-cells = <1>;
489 #size-cells = <0>;
490 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
491 reg = <0x83fc4000 0x4000>;
492 interrupts = <63>;
493 clocks = <&clks IMX5_CLK_I2C2_GATE>;
494 status = "disabled";
495 };
496
497 i2c1: i2c@83fc8000 {
498 #address-cells = <1>;
499 #size-cells = <0>;
500 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
501 reg = <0x83fc8000 0x4000>;
502 interrupts = <62>;
503 clocks = <&clks IMX5_CLK_I2C1_GATE>;
504 status = "disabled";
505 };
506
507 ssi1: ssi@83fcc000 {
508 #sound-dai-cells = <0>;
509 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
510 reg = <0x83fcc000 0x4000>;
511 interrupts = <29>;
512 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
513 <&clks IMX5_CLK_SSI1_ROOT_GATE>;
514 clock-names = "ipg", "baud";
515 dmas = <&sdma 28 0 0>,
516 <&sdma 29 0 0>;
517 dma-names = "rx", "tx";
518 fsl,fifo-depth = <15>;
519 status = "disabled";
520 };
521
522 audmux: audmux@83fd0000 {
523 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
524 reg = <0x83fd0000 0x4000>;
525 clocks = <&clks IMX5_CLK_DUMMY>;
526 clock-names = "audmux";
527 status = "disabled";
528 };
529
530 weim: weim@83fda000 {
531 #address-cells = <2>;
532 #size-cells = <1>;
533 compatible = "fsl,imx51-weim";
534 reg = <0x83fda000 0x1000>;
535 clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>;
536 ranges = <
537 0 0 0xb0000000 0x08000000
538 1 0 0xb8000000 0x08000000
539 2 0 0xc0000000 0x08000000
540 3 0 0xc8000000 0x04000000
541 4 0 0xcc000000 0x02000000
542 5 0 0xce000000 0x02000000
543 >;
544 status = "disabled";
545 };
546
547 nfc: nand@83fdb000 {
548 #address-cells = <1>;
549 #size-cells = <1>;
550 compatible = "fsl,imx51-nand";
551 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
552 interrupts = <8>;
553 clocks = <&clks IMX5_CLK_NFC_GATE>;
554 status = "disabled";
555 };
556
557 pata: pata@83fe0000 {
558 compatible = "fsl,imx51-pata", "fsl,imx27-pata";
559 reg = <0x83fe0000 0x4000>;
560 interrupts = <70>;
561 clocks = <&clks IMX5_CLK_PATA_GATE>;
562 status = "disabled";
563 };
564
565 ssi3: ssi@83fe8000 {
566 #sound-dai-cells = <0>;
567 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
568 reg = <0x83fe8000 0x4000>;
569 interrupts = <96>;
570 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
571 <&clks IMX5_CLK_SSI3_ROOT_GATE>;
572 clock-names = "ipg", "baud";
573 dmas = <&sdma 46 0 0>,
574 <&sdma 47 0 0>;
575 dma-names = "rx", "tx";
576 fsl,fifo-depth = <15>;
577 status = "disabled";
578 };
579
580 fec: ethernet@83fec000 {
581 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
582 reg = <0x83fec000 0x4000>;
583 interrupts = <87>;
584 clocks = <&clks IMX5_CLK_FEC_GATE>,
585 <&clks IMX5_CLK_FEC_GATE>,
586 <&clks IMX5_CLK_FEC_GATE>;
587 clock-names = "ipg", "ahb", "ptp";
588 status = "disabled";
589 };
590 };
591 };
592 };
Linux kernel - Deliverables
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