arch/arm/boot/dts/imx53-mba53.dts

   1 /*
   2  * Copyright 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
   3  * Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>, Pengutronix
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 /dts-v1/;
  14 #include "imx53-tqma53.dtsi"
  15
  16 / {
  17         model = "TQ MBa53 starter kit";
  18         compatible = "tq,mba53", "tq,tqma53", "fsl,imx53";
  19
  20         reg_backlight: fixed@0 {
  21                 compatible = "regulator-fixed";
  22                 regulator-name = "lcd-supply";
  23                 gpio = <&gpio2 5 0>;
  24                 startup-delay-us = <5000>;
  25                 enable-active-low;
  26         };
  27
  28         backlight {
  29                 compatible = "pwm-backlight";
  30                 pwms = <&pwm2 0 50000>;
  31                 brightness-levels = <0 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100>;
  32                 default-brightness-level = <10>;
  33                 enable-gpios = <&gpio7 7 0>;
  34                 power-supply = <&reg_backlight>;
  35         };
  36
  37         disp1: display@disp1 {
  38                 compatible = "fsl,imx-parallel-display";
  39                 pinctrl-names = "default";
  40                 pinctrl-0 = <&pinctrl_disp1_1>;
  41                 crtcs = <&ipu 1>;
  42                 interface-pix-fmt = "rgb24";
  43                 status = "disabled";
  44         };
  45
  46         imx-drm {
  47                 compatible = "fsl,imx-drm";
  48                 crtcs = <&ipu 1>;
  49                 connectors = <&disp1>, <&tve>;
  50         };
  51
  52         reg_3p2v: 3p2v {
  53                 compatible = "regulator-fixed";
  54                 regulator-name = "3P2V";
  55                 regulator-min-microvolt = <3200000>;
  56                 regulator-max-microvolt = <3200000>;
  57                 regulator-always-on;
  58         };
  59
  60         sound {
  61                 compatible = "tq,imx53-mba53-sgtl5000",
  62                              "fsl,imx-audio-sgtl5000";
  63                 model = "imx53-mba53-sgtl5000";
  64                 ssi-controller = <&ssi2>;
  65                 audio-codec = <&codec>;
  66                 audio-routing =
  67                         "MIC_IN", "Mic Jack",
  68                         "Mic Jack", "Mic Bias",
  69                         "Headphone Jack", "HP_OUT";
  70                 mux-int-port = <2>;
  71                 mux-ext-port = <5>;
  72         };
  73 };
  74
  75 &ldb {
  76         pinctrl-names = "default";
  77         pinctrl-0 = <&pinctrl_lvds1_1>;
  78         status = "disabled";
  79 };
  80
  81 &iomuxc {
  82         lvds1 {
  83                 pinctrl_lvds1_1: lvds1-grp1 {
  84                         fsl,pins = <
  85                                 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
  86                                 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
  87                                 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
  88                                 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
  89                                 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
  90                         >;
  91                 };
  92
  93                 pinctrl_lvds1_2: lvds1-grp2 {
  94                         fsl,pins = <
  95                                 MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000
  96                                 MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000
  97                                 MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000
  98                                 MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000
  99                                 MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000
 100                         >;
 101                 };
 102         };
 103
 104         disp1 {
 105                 pinctrl_disp1_1: disp1-grp1 {
 106                         fsl,pins = <
 107                                 MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x80000000 /* DISP1_CLK */
 108                                 MX53_PAD_EIM_DA10__IPU_DI1_PIN15   0x80000000 /* DISP1_DRDY */
 109                                 MX53_PAD_EIM_D23__IPU_DI1_PIN2     0x80000000 /* DISP1_HSYNC */
 110                                 MX53_PAD_EIM_EB3__IPU_DI1_PIN3     0x80000000 /* DISP1_VSYNC */
 111                                 MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x80000000
 112                                 MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x80000000
 113                                 MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x80000000
 114                                 MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x80000000
 115                                 MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x80000000
 116                                 MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x80000000
 117                                 MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x80000000
 118                                 MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x80000000
 119                                 MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x80000000
 120                                 MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x80000000
 121                                 MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x80000000
 122                                 MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x80000000
 123                                 MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x80000000
 124                                 MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x80000000
 125                                 MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9  0x80000000
 126                                 MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8  0x80000000
 127                                 MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7  0x80000000
 128                                 MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6  0x80000000
 129                                 MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5  0x80000000
 130                                 MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4  0x80000000
 131                                 MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3  0x80000000
 132                                 MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2  0x80000000
 133                                 MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1  0x80000000
 134                                 MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0  0x80000000
 135                         >;
 136                 };
 137         };
 138
 139         tve {
 140                 pinctrl_vga_sync_1: vgasync-grp1 {
 141                         fsl,pins = <
 142                                 /* VGA_VSYNC, HSYNC with max drive strength */
 143                                 MX53_PAD_EIM_CS1__IPU_DI1_PIN6     0xe6
 144                                 MX53_PAD_EIM_DA15__IPU_DI1_PIN4    0xe6
 145                         >;
 146                 };
 147         };
 148 };
 149
 150 &cspi {
 151         status = "okay";
 152 };
 153
 154 &audmux {
 155         status = "okay";
 156         pinctrl-names = "default";
 157         pinctrl-0 = <&pinctrl_audmux_1>;
 158 };
 159
 160 &i2c2 {
 161         codec: sgtl5000@a {
 162                 compatible = "fsl,sgtl5000";
 163                 reg = <0x0a>;
 164                 clocks = <&clks 150>;
 165                 VDDA-supply = <&reg_3p2v>;
 166                 VDDIO-supply = <&reg_3p2v>;
 167         };
 168
 169         expander: pca9554@20 {
 170                 compatible = "pca9554";
 171                 reg = <0x20>;
 172                 interrupts = <109>;
 173                 #gpio-cells = <2>;
 174                 gpio-controller;
 175         };
 176
 177         sensor2: lm75@49 {
 178                 compatible = "lm75";
 179                 reg = <0x49>;
 180         };
 181 };
 182
 183 &fec {
 184         phy-reset-gpios = <&gpio7 6 0>;
 185         status = "okay";
 186 };
 187
 188 &esdhc2 {
 189         status = "okay";
 190 };
 191
 192 &uart3 {
 193         status = "okay";
 194 };
 195
 196 &ecspi1 {
 197         status = "okay";
 198 };
 199
 200 &usbotg {
 201         dr_mode = "host";
 202         status = "okay";
 203 };
 204
 205 &usbh1 {
 206         status = "okay";
 207 };
 208
 209 &uart1 {
 210         status = "okay";
 211 };
 212
 213 &ssi2 {
 214         fsl,mode = "i2s-slave";
 215         status = "okay";
 216 };
 217
 218 &uart2 {
 219         status = "okay";
 220 };
 221
 222 &can1 {
 223         status = "okay";
 224 };
 225
 226 &can2 {
 227         status = "okay";
 228 };
 229
 230 &i2c3 {
 231         status = "okay";
 232 };
 233
 234 &tve {
 235         pinctrl-names = "default";
 236         pinctrl-0 = <&pinctrl_vga_sync_1>;
 237         ddc = <&i2c3>;
 238         fsl,tve-mode = "vga";
 239         fsl,hsync-pin = <4>;
 240         fsl,vsync-pin = <6>;
 241         status = "okay";
 242 };