2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include "skeleton.dtsi"
14 #include "imx53-pinfunc.h"
15 #include <dt-bindings/clock/imx5-clock.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/input/input.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
52 compatible = "arm,cortex-a8";
54 clocks = <&clks IMX5_CLK_ARM>;
55 clock-latency = <61036>;
56 voltage-tolerance = <5>;
69 compatible = "fsl,imx-display-subsystem";
70 ports = <&ipu_di0>, <&ipu_di1>;
73 tzic: tz-interrupt-controller@0fffc000 {
74 compatible = "fsl,imx53-tzic", "fsl,tzic";
76 #interrupt-cells = <1>;
77 reg = <0x0fffc000 0x4000>;
85 compatible = "fsl,imx-ckil", "fixed-clock";
87 clock-frequency = <32768>;
91 compatible = "fsl,imx-ckih1", "fixed-clock";
93 clock-frequency = <22579200>;
97 compatible = "fsl,imx-ckih2", "fixed-clock";
99 clock-frequency = <0>;
103 compatible = "fsl,imx-osc", "fixed-clock";
105 clock-frequency = <24000000>;
110 #address-cells = <1>;
112 compatible = "simple-bus";
113 interrupt-parent = <&tzic>;
116 sata: sata@10000000 {
117 compatible = "fsl,imx53-ahci";
118 reg = <0x10000000 0x1000>;
120 clocks = <&clks IMX5_CLK_SATA_GATE>,
121 <&clks IMX5_CLK_SATA_REF>,
122 <&clks IMX5_CLK_AHB>;
123 clock-names = "sata", "sata_ref", "ahb";
128 #address-cells = <1>;
130 compatible = "fsl,imx53-ipu";
131 reg = <0x18000000 0x08000000>;
132 interrupts = <11 10>;
133 clocks = <&clks IMX5_CLK_IPU_GATE>,
134 <&clks IMX5_CLK_IPU_DI0_GATE>,
135 <&clks IMX5_CLK_IPU_DI1_GATE>;
136 clock-names = "bus", "di0", "di1";
148 #address-cells = <1>;
152 ipu_di0_disp0: endpoint@0 {
156 ipu_di0_lvds0: endpoint@1 {
158 remote-endpoint = <&lvds0_in>;
163 #address-cells = <1>;
167 ipu_di1_disp1: endpoint@0 {
171 ipu_di1_lvds1: endpoint@1 {
173 remote-endpoint = <&lvds1_in>;
176 ipu_di1_tve: endpoint@2 {
178 remote-endpoint = <&tve_in>;
183 aips@50000000 { /* AIPS1 */
184 compatible = "fsl,aips-bus", "simple-bus";
185 #address-cells = <1>;
187 reg = <0x50000000 0x10000000>;
191 compatible = "fsl,spba-bus", "simple-bus";
192 #address-cells = <1>;
194 reg = <0x50000000 0x40000>;
197 esdhc1: esdhc@50004000 {
198 compatible = "fsl,imx53-esdhc";
199 reg = <0x50004000 0x4000>;
201 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
202 <&clks IMX5_CLK_DUMMY>,
203 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
204 clock-names = "ipg", "ahb", "per";
209 esdhc2: esdhc@50008000 {
210 compatible = "fsl,imx53-esdhc";
211 reg = <0x50008000 0x4000>;
213 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
214 <&clks IMX5_CLK_DUMMY>,
215 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
216 clock-names = "ipg", "ahb", "per";
221 uart3: serial@5000c000 {
222 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
223 reg = <0x5000c000 0x4000>;
225 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
226 <&clks IMX5_CLK_UART3_PER_GATE>;
227 clock-names = "ipg", "per";
228 dmas = <&sdma 42 4 0>, <&sdma 43 4 0>;
229 dma-names = "rx", "tx";
233 ecspi1: ecspi@50010000 {
234 #address-cells = <1>;
236 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
237 reg = <0x50010000 0x4000>;
239 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
240 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
241 clock-names = "ipg", "per";
246 #sound-dai-cells = <0>;
247 compatible = "fsl,imx53-ssi",
250 reg = <0x50014000 0x4000>;
252 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
253 <&clks IMX5_CLK_SSI2_ROOT_GATE>;
254 clock-names = "ipg", "baud";
255 dmas = <&sdma 24 1 0>,
257 dma-names = "rx", "tx";
258 fsl,fifo-depth = <15>;
262 esdhc3: esdhc@50020000 {
263 compatible = "fsl,imx53-esdhc";
264 reg = <0x50020000 0x4000>;
266 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
267 <&clks IMX5_CLK_DUMMY>,
268 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
269 clock-names = "ipg", "ahb", "per";
274 esdhc4: esdhc@50024000 {
275 compatible = "fsl,imx53-esdhc";
276 reg = <0x50024000 0x4000>;
278 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
279 <&clks IMX5_CLK_DUMMY>,
280 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
281 clock-names = "ipg", "ahb", "per";
287 aipstz1: bridge@53f00000 {
288 compatible = "fsl,imx53-aipstz";
289 reg = <0x53f00000 0x60>;
293 compatible = "usb-nop-xceiv";
294 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
295 clock-names = "main_clk";
300 compatible = "usb-nop-xceiv";
301 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
302 clock-names = "main_clk";
306 usbotg: usb@53f80000 {
307 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
308 reg = <0x53f80000 0x0200>;
310 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
311 fsl,usbmisc = <&usbmisc 0>;
312 fsl,usbphy = <&usbphy0>;
316 usbh1: usb@53f80200 {
317 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
318 reg = <0x53f80200 0x0200>;
320 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
321 fsl,usbmisc = <&usbmisc 1>;
322 fsl,usbphy = <&usbphy1>;
327 usbh2: usb@53f80400 {
328 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
329 reg = <0x53f80400 0x0200>;
331 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
332 fsl,usbmisc = <&usbmisc 2>;
337 usbh3: usb@53f80600 {
338 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
339 reg = <0x53f80600 0x0200>;
341 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
342 fsl,usbmisc = <&usbmisc 3>;
347 usbmisc: usbmisc@53f80800 {
349 compatible = "fsl,imx53-usbmisc";
350 reg = <0x53f80800 0x200>;
351 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
354 gpio1: gpio@53f84000 {
355 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
356 reg = <0x53f84000 0x4000>;
357 interrupts = <50 51>;
360 interrupt-controller;
361 #interrupt-cells = <2>;
364 gpio2: gpio@53f88000 {
365 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
366 reg = <0x53f88000 0x4000>;
367 interrupts = <52 53>;
370 interrupt-controller;
371 #interrupt-cells = <2>;
374 gpio3: gpio@53f8c000 {
375 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
376 reg = <0x53f8c000 0x4000>;
377 interrupts = <54 55>;
380 interrupt-controller;
381 #interrupt-cells = <2>;
384 gpio4: gpio@53f90000 {
385 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
386 reg = <0x53f90000 0x4000>;
387 interrupts = <56 57>;
390 interrupt-controller;
391 #interrupt-cells = <2>;
395 compatible = "fsl,imx53-kpp", "fsl,imx21-kpp";
396 reg = <0x53f94000 0x4000>;
398 clocks = <&clks IMX5_CLK_DUMMY>;
402 wdog1: wdog@53f98000 {
403 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
404 reg = <0x53f98000 0x4000>;
406 clocks = <&clks IMX5_CLK_DUMMY>;
409 wdog2: wdog@53f9c000 {
410 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
411 reg = <0x53f9c000 0x4000>;
413 clocks = <&clks IMX5_CLK_DUMMY>;
417 gpt: timer@53fa0000 {
418 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
419 reg = <0x53fa0000 0x4000>;
421 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
422 <&clks IMX5_CLK_GPT_HF_GATE>;
423 clock-names = "ipg", "per";
426 iomuxc: iomuxc@53fa8000 {
427 compatible = "fsl,imx53-iomuxc";
428 reg = <0x53fa8000 0x4000>;
431 gpr: iomuxc-gpr@53fa8000 {
432 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
433 reg = <0x53fa8000 0xc>;
437 #address-cells = <1>;
439 compatible = "fsl,imx53-ldb";
440 reg = <0x53fa8008 0x4>;
442 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
443 <&clks IMX5_CLK_LDB_DI1_SEL>,
444 <&clks IMX5_CLK_IPU_DI0_SEL>,
445 <&clks IMX5_CLK_IPU_DI1_SEL>,
446 <&clks IMX5_CLK_LDB_DI0_GATE>,
447 <&clks IMX5_CLK_LDB_DI1_GATE>;
448 clock-names = "di0_pll", "di1_pll",
449 "di0_sel", "di1_sel",
454 #address-cells = <1>;
463 remote-endpoint = <&ipu_di0_lvds0>;
469 #address-cells = <1>;
478 remote-endpoint = <&ipu_di1_lvds1>;
486 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
487 reg = <0x53fb4000 0x4000>;
488 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
489 <&clks IMX5_CLK_PWM1_HF_GATE>;
490 clock-names = "ipg", "per";
496 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
497 reg = <0x53fb8000 0x4000>;
498 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
499 <&clks IMX5_CLK_PWM2_HF_GATE>;
500 clock-names = "ipg", "per";
504 uart1: serial@53fbc000 {
505 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
506 reg = <0x53fbc000 0x4000>;
508 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
509 <&clks IMX5_CLK_UART1_PER_GATE>;
510 clock-names = "ipg", "per";
511 dmas = <&sdma 18 4 0>, <&sdma 19 4 0>;
512 dma-names = "rx", "tx";
516 uart2: serial@53fc0000 {
517 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
518 reg = <0x53fc0000 0x4000>;
520 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
521 <&clks IMX5_CLK_UART2_PER_GATE>;
522 clock-names = "ipg", "per";
523 dmas = <&sdma 12 4 0>, <&sdma 13 4 0>;
524 dma-names = "rx", "tx";
529 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
530 reg = <0x53fc8000 0x4000>;
532 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
533 <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
534 clock-names = "ipg", "per";
539 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
540 reg = <0x53fcc000 0x4000>;
542 clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
543 <&clks IMX5_CLK_CAN2_SERIAL_GATE>;
544 clock-names = "ipg", "per";
549 compatible = "fsl,imx53-src", "fsl,imx51-src";
550 reg = <0x53fd0000 0x4000>;
555 compatible = "fsl,imx53-ccm";
556 reg = <0x53fd4000 0x4000>;
557 interrupts = <0 71 0x04 0 72 0x04>;
561 gpio5: gpio@53fdc000 {
562 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
563 reg = <0x53fdc000 0x4000>;
564 interrupts = <103 104>;
567 interrupt-controller;
568 #interrupt-cells = <2>;
571 gpio6: gpio@53fe0000 {
572 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
573 reg = <0x53fe0000 0x4000>;
574 interrupts = <105 106>;
577 interrupt-controller;
578 #interrupt-cells = <2>;
581 gpio7: gpio@53fe4000 {
582 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
583 reg = <0x53fe4000 0x4000>;
584 interrupts = <107 108>;
587 interrupt-controller;
588 #interrupt-cells = <2>;
592 #address-cells = <1>;
594 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
595 reg = <0x53fec000 0x4000>;
597 clocks = <&clks IMX5_CLK_I2C3_GATE>;
601 uart4: serial@53ff0000 {
602 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
603 reg = <0x53ff0000 0x4000>;
605 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
606 <&clks IMX5_CLK_UART4_PER_GATE>;
607 clock-names = "ipg", "per";
608 dmas = <&sdma 2 4 0>, <&sdma 3 4 0>;
609 dma-names = "rx", "tx";
614 aips@60000000 { /* AIPS2 */
615 compatible = "fsl,aips-bus", "simple-bus";
616 #address-cells = <1>;
618 reg = <0x60000000 0x10000000>;
621 aipstz2: bridge@63f00000 {
622 compatible = "fsl,imx53-aipstz";
623 reg = <0x63f00000 0x60>;
627 compatible = "fsl,imx53-iim", "fsl,imx27-iim";
628 reg = <0x63f98000 0x4000>;
630 clocks = <&clks IMX5_CLK_IIM_GATE>;
633 uart5: serial@63f90000 {
634 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
635 reg = <0x63f90000 0x4000>;
637 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
638 <&clks IMX5_CLK_UART5_PER_GATE>;
639 clock-names = "ipg", "per";
640 dmas = <&sdma 16 4 0>, <&sdma 17 4 0>;
641 dma-names = "rx", "tx";
645 owire: owire@63fa4000 {
646 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
647 reg = <0x63fa4000 0x4000>;
648 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
652 ecspi2: ecspi@63fac000 {
653 #address-cells = <1>;
655 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
656 reg = <0x63fac000 0x4000>;
658 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
659 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
660 clock-names = "ipg", "per";
664 sdma: sdma@63fb0000 {
665 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
666 reg = <0x63fb0000 0x4000>;
668 clocks = <&clks IMX5_CLK_SDMA_GATE>,
669 <&clks IMX5_CLK_SDMA_GATE>;
670 clock-names = "ipg", "ahb";
672 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
675 cspi: cspi@63fc0000 {
676 #address-cells = <1>;
678 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
679 reg = <0x63fc0000 0x4000>;
681 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
682 <&clks IMX5_CLK_CSPI_IPG_GATE>;
683 clock-names = "ipg", "per";
688 #address-cells = <1>;
690 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
691 reg = <0x63fc4000 0x4000>;
693 clocks = <&clks IMX5_CLK_I2C2_GATE>;
698 #address-cells = <1>;
700 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
701 reg = <0x63fc8000 0x4000>;
703 clocks = <&clks IMX5_CLK_I2C1_GATE>;
708 #sound-dai-cells = <0>;
709 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
711 reg = <0x63fcc000 0x4000>;
713 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
714 <&clks IMX5_CLK_SSI1_ROOT_GATE>;
715 clock-names = "ipg", "baud";
716 dmas = <&sdma 28 0 0>,
718 dma-names = "rx", "tx";
719 fsl,fifo-depth = <15>;
723 audmux: audmux@63fd0000 {
724 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
725 reg = <0x63fd0000 0x4000>;
730 compatible = "fsl,imx53-nand";
731 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
733 clocks = <&clks IMX5_CLK_NFC_GATE>;
738 #sound-dai-cells = <0>;
739 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
741 reg = <0x63fe8000 0x4000>;
743 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
744 <&clks IMX5_CLK_SSI3_ROOT_GATE>;
745 clock-names = "ipg", "baud";
746 dmas = <&sdma 46 0 0>,
748 dma-names = "rx", "tx";
749 fsl,fifo-depth = <15>;
753 fec: ethernet@63fec000 {
754 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
755 reg = <0x63fec000 0x4000>;
757 clocks = <&clks IMX5_CLK_FEC_GATE>,
758 <&clks IMX5_CLK_FEC_GATE>,
759 <&clks IMX5_CLK_FEC_GATE>;
760 clock-names = "ipg", "ahb", "ptp";
765 compatible = "fsl,imx53-tve";
766 reg = <0x63ff0000 0x1000>;
768 clocks = <&clks IMX5_CLK_TVE_GATE>,
769 <&clks IMX5_CLK_IPU_DI1_SEL>;
770 clock-names = "tve", "di_sel";
775 remote-endpoint = <&ipu_di1_tve>;
781 compatible = "fsl,imx53-vpu", "cnm,coda7541";
782 reg = <0x63ff4000 0x1000>;
784 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
785 <&clks IMX5_CLK_VPU_GATE>;
786 clock-names = "per", "ahb";
791 sahara: crypto@63ff8000 {
792 compatible = "fsl,imx53-sahara";
793 reg = <0x63ff8000 0x4000>;
794 interrupts = <19 20>;
795 clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
796 <&clks IMX5_CLK_SAHARA_IPG_GATE>;
797 clock-names = "ipg", "ahb";
801 ocram: sram@f8000000 {
802 compatible = "mmio-sram";
803 reg = <0xf8000000 0x20000>;
804 clocks = <&clks IMX5_CLK_OCRAM>;
808 compatible = "arm,cortex-a8-pmu";