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ARM i.MX5: Move IPU clock lookups into device tree
[deliverable/linux.git] / arch / arm / boot / dts / imx53.dtsi
1 /*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13 #include "skeleton.dtsi"
14 #include "imx53-pinfunc.h"
15
16 / {
17 aliases {
18 serial0 = &uart1;
19 serial1 = &uart2;
20 serial2 = &uart3;
21 serial3 = &uart4;
22 serial4 = &uart5;
23 gpio0 = &gpio1;
24 gpio1 = &gpio2;
25 gpio2 = &gpio3;
26 gpio3 = &gpio4;
27 gpio4 = &gpio5;
28 gpio5 = &gpio6;
29 gpio6 = &gpio7;
30 };
31
32 tzic: tz-interrupt-controller@0fffc000 {
33 compatible = "fsl,imx53-tzic", "fsl,tzic";
34 interrupt-controller;
35 #interrupt-cells = <1>;
36 reg = <0x0fffc000 0x4000>;
37 };
38
39 clocks {
40 #address-cells = <1>;
41 #size-cells = <0>;
42
43 ckil {
44 compatible = "fsl,imx-ckil", "fixed-clock";
45 clock-frequency = <32768>;
46 };
47
48 ckih1 {
49 compatible = "fsl,imx-ckih1", "fixed-clock";
50 clock-frequency = <22579200>;
51 };
52
53 ckih2 {
54 compatible = "fsl,imx-ckih2", "fixed-clock";
55 clock-frequency = <0>;
56 };
57
58 osc {
59 compatible = "fsl,imx-osc", "fixed-clock";
60 clock-frequency = <24000000>;
61 };
62 };
63
64 soc {
65 #address-cells = <1>;
66 #size-cells = <1>;
67 compatible = "simple-bus";
68 interrupt-parent = <&tzic>;
69 ranges;
70
71 ipu: ipu@18000000 {
72 #crtc-cells = <1>;
73 compatible = "fsl,imx53-ipu";
74 reg = <0x18000000 0x080000000>;
75 interrupts = <11 10>;
76 clocks = <&clks 59>, <&clks 110>, <&clks 61>;
77 clock-names = "bus", "di0", "di1";
78 };
79
80 aips@50000000 { /* AIPS1 */
81 compatible = "fsl,aips-bus", "simple-bus";
82 #address-cells = <1>;
83 #size-cells = <1>;
84 reg = <0x50000000 0x10000000>;
85 ranges;
86
87 spba@50000000 {
88 compatible = "fsl,spba-bus", "simple-bus";
89 #address-cells = <1>;
90 #size-cells = <1>;
91 reg = <0x50000000 0x40000>;
92 ranges;
93
94 esdhc1: esdhc@50004000 {
95 compatible = "fsl,imx53-esdhc";
96 reg = <0x50004000 0x4000>;
97 interrupts = <1>;
98 clocks = <&clks 44>, <&clks 0>, <&clks 71>;
99 clock-names = "ipg", "ahb", "per";
100 bus-width = <4>;
101 status = "disabled";
102 };
103
104 esdhc2: esdhc@50008000 {
105 compatible = "fsl,imx53-esdhc";
106 reg = <0x50008000 0x4000>;
107 interrupts = <2>;
108 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
109 clock-names = "ipg", "ahb", "per";
110 bus-width = <4>;
111 status = "disabled";
112 };
113
114 uart3: serial@5000c000 {
115 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
116 reg = <0x5000c000 0x4000>;
117 interrupts = <33>;
118 clocks = <&clks 32>, <&clks 33>;
119 clock-names = "ipg", "per";
120 status = "disabled";
121 };
122
123 ecspi1: ecspi@50010000 {
124 #address-cells = <1>;
125 #size-cells = <0>;
126 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
127 reg = <0x50010000 0x4000>;
128 interrupts = <36>;
129 clocks = <&clks 51>, <&clks 52>;
130 clock-names = "ipg", "per";
131 status = "disabled";
132 };
133
134 ssi2: ssi@50014000 {
135 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
136 reg = <0x50014000 0x4000>;
137 interrupts = <30>;
138 clocks = <&clks 49>;
139 fsl,fifo-depth = <15>;
140 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
141 status = "disabled";
142 };
143
144 esdhc3: esdhc@50020000 {
145 compatible = "fsl,imx53-esdhc";
146 reg = <0x50020000 0x4000>;
147 interrupts = <3>;
148 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
149 clock-names = "ipg", "ahb", "per";
150 bus-width = <4>;
151 status = "disabled";
152 };
153
154 esdhc4: esdhc@50024000 {
155 compatible = "fsl,imx53-esdhc";
156 reg = <0x50024000 0x4000>;
157 interrupts = <4>;
158 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
159 clock-names = "ipg", "ahb", "per";
160 bus-width = <4>;
161 status = "disabled";
162 };
163 };
164
165 usbotg: usb@53f80000 {
166 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
167 reg = <0x53f80000 0x0200>;
168 interrupts = <18>;
169 status = "disabled";
170 };
171
172 usbh1: usb@53f80200 {
173 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
174 reg = <0x53f80200 0x0200>;
175 interrupts = <14>;
176 status = "disabled";
177 };
178
179 usbh2: usb@53f80400 {
180 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
181 reg = <0x53f80400 0x0200>;
182 interrupts = <16>;
183 status = "disabled";
184 };
185
186 usbh3: usb@53f80600 {
187 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
188 reg = <0x53f80600 0x0200>;
189 interrupts = <17>;
190 status = "disabled";
191 };
192
193 gpio1: gpio@53f84000 {
194 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
195 reg = <0x53f84000 0x4000>;
196 interrupts = <50 51>;
197 gpio-controller;
198 #gpio-cells = <2>;
199 interrupt-controller;
200 #interrupt-cells = <2>;
201 };
202
203 gpio2: gpio@53f88000 {
204 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
205 reg = <0x53f88000 0x4000>;
206 interrupts = <52 53>;
207 gpio-controller;
208 #gpio-cells = <2>;
209 interrupt-controller;
210 #interrupt-cells = <2>;
211 };
212
213 gpio3: gpio@53f8c000 {
214 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
215 reg = <0x53f8c000 0x4000>;
216 interrupts = <54 55>;
217 gpio-controller;
218 #gpio-cells = <2>;
219 interrupt-controller;
220 #interrupt-cells = <2>;
221 };
222
223 gpio4: gpio@53f90000 {
224 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
225 reg = <0x53f90000 0x4000>;
226 interrupts = <56 57>;
227 gpio-controller;
228 #gpio-cells = <2>;
229 interrupt-controller;
230 #interrupt-cells = <2>;
231 };
232
233 wdog1: wdog@53f98000 {
234 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
235 reg = <0x53f98000 0x4000>;
236 interrupts = <58>;
237 clocks = <&clks 0>;
238 };
239
240 wdog2: wdog@53f9c000 {
241 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
242 reg = <0x53f9c000 0x4000>;
243 interrupts = <59>;
244 clocks = <&clks 0>;
245 status = "disabled";
246 };
247
248 gpt: timer@53fa0000 {
249 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
250 reg = <0x53fa0000 0x4000>;
251 interrupts = <39>;
252 clocks = <&clks 36>, <&clks 41>;
253 clock-names = "ipg", "per";
254 };
255
256 iomuxc: iomuxc@53fa8000 {
257 compatible = "fsl,imx53-iomuxc";
258 reg = <0x53fa8000 0x4000>;
259
260 audmux {
261 pinctrl_audmux_1: audmuxgrp-1 {
262 fsl,pins = <
263 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
264 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
265 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
266 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
267 >;
268 };
269 };
270
271 fec {
272 pinctrl_fec_1: fecgrp-1 {
273 fsl,pins = <
274 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
275 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
276 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
277 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
278 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
279 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
280 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
281 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
282 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
283 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
284 >;
285 };
286 };
287
288 csi {
289 pinctrl_csi_1: csigrp-1 {
290 fsl,pins = <
291 MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1d5
292 MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5
293 MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5
294 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
295 MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5
296 MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5
297 MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5
298 MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5
299 MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5
300 MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5
301 MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5
302 MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5
303 MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 0x1d5
304 MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 0x1d5
305 MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 0x1d5
306 MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 0x1d5
307 MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 0x1d5
308 MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 0x1d5
309 MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 0x1d5
310 MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 0x1d5
311 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
312 >;
313 };
314 };
315
316 cspi {
317 pinctrl_cspi_1: cspigrp-1 {
318 fsl,pins = <
319 MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5
320 MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5
321 MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5
322 >;
323 };
324 };
325
326 ecspi1 {
327 pinctrl_ecspi1_1: ecspi1grp-1 {
328 fsl,pins = <
329 MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
330 MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
331 MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
332 >;
333 };
334 };
335
336 esdhc1 {
337 pinctrl_esdhc1_1: esdhc1grp-1 {
338 fsl,pins = <
339 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
340 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
341 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
342 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
343 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
344 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
345 >;
346 };
347
348 pinctrl_esdhc1_2: esdhc1grp-2 {
349 fsl,pins = <
350 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
351 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
352 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
353 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
354 MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5
355 MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5
356 MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5
357 MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5
358 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
359 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
360 >;
361 };
362 };
363
364 esdhc2 {
365 pinctrl_esdhc2_1: esdhc2grp-1 {
366 fsl,pins = <
367 MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
368 MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
369 MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
370 MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
371 MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
372 MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
373 >;
374 };
375 };
376
377 esdhc3 {
378 pinctrl_esdhc3_1: esdhc3grp-1 {
379 fsl,pins = <
380 MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
381 MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
382 MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
383 MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
384 MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
385 MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
386 MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
387 MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
388 MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
389 MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
390 >;
391 };
392 };
393
394 can1 {
395 pinctrl_can1_1: can1grp-1 {
396 fsl,pins = <
397 MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x80000000
398 MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x80000000
399 >;
400 };
401
402 pinctrl_can1_2: can1grp-2 {
403 fsl,pins = <
404 MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000
405 MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
406 >;
407 };
408 };
409
410 can2 {
411 pinctrl_can2_1: can2grp-1 {
412 fsl,pins = <
413 MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
414 MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
415 >;
416 };
417 };
418
419 i2c1 {
420 pinctrl_i2c1_1: i2c1grp-1 {
421 fsl,pins = <
422 MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000
423 MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
424 >;
425 };
426 };
427
428 i2c2 {
429 pinctrl_i2c2_1: i2c2grp-1 {
430 fsl,pins = <
431 MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
432 MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
433 >;
434 };
435 };
436
437 i2c3 {
438 pinctrl_i2c3_1: i2c3grp-1 {
439 fsl,pins = <
440 MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
441 MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
442 >;
443 };
444 };
445
446 owire {
447 pinctrl_owire_1: owiregrp-1 {
448 fsl,pins = <
449 MX53_PAD_GPIO_18__OWIRE_LINE 0x80000000
450 >;
451 };
452 };
453
454 uart1 {
455 pinctrl_uart1_1: uart1grp-1 {
456 fsl,pins = <
457 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1c5
458 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1c5
459 >;
460 };
461
462 pinctrl_uart1_2: uart1grp-2 {
463 fsl,pins = <
464 MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1c5
465 MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1c5
466 >;
467 };
468 };
469
470 uart2 {
471 pinctrl_uart2_1: uart2grp-1 {
472 fsl,pins = <
473 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5
474 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5
475 >;
476 };
477 };
478
479 uart3 {
480 pinctrl_uart3_1: uart3grp-1 {
481 fsl,pins = <
482 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5
483 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5
484 MX53_PAD_PATA_DA_1__UART3_CTS 0x1c5
485 MX53_PAD_PATA_DA_2__UART3_RTS 0x1c5
486 >;
487 };
488
489 pinctrl_uart3_2: uart3grp-2 {
490 fsl,pins = <
491 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5
492 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5
493 >;
494 };
495
496 };
497
498 uart4 {
499 pinctrl_uart4_1: uart4grp-1 {
500 fsl,pins = <
501 MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1c5
502 MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1c5
503 >;
504 };
505 };
506
507 uart5 {
508 pinctrl_uart5_1: uart5grp-1 {
509 fsl,pins = <
510 MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1c5
511 MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1c5
512 >;
513 };
514 };
515
516 };
517
518 pwm1: pwm@53fb4000 {
519 #pwm-cells = <2>;
520 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
521 reg = <0x53fb4000 0x4000>;
522 clocks = <&clks 37>, <&clks 38>;
523 clock-names = "ipg", "per";
524 interrupts = <61>;
525 };
526
527 pwm2: pwm@53fb8000 {
528 #pwm-cells = <2>;
529 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
530 reg = <0x53fb8000 0x4000>;
531 clocks = <&clks 39>, <&clks 40>;
532 clock-names = "ipg", "per";
533 interrupts = <94>;
534 };
535
536 uart1: serial@53fbc000 {
537 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
538 reg = <0x53fbc000 0x4000>;
539 interrupts = <31>;
540 clocks = <&clks 28>, <&clks 29>;
541 clock-names = "ipg", "per";
542 status = "disabled";
543 };
544
545 uart2: serial@53fc0000 {
546 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
547 reg = <0x53fc0000 0x4000>;
548 interrupts = <32>;
549 clocks = <&clks 30>, <&clks 31>;
550 clock-names = "ipg", "per";
551 status = "disabled";
552 };
553
554 can1: can@53fc8000 {
555 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
556 reg = <0x53fc8000 0x4000>;
557 interrupts = <82>;
558 clocks = <&clks 158>, <&clks 157>;
559 clock-names = "ipg", "per";
560 status = "disabled";
561 };
562
563 can2: can@53fcc000 {
564 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
565 reg = <0x53fcc000 0x4000>;
566 interrupts = <83>;
567 clocks = <&clks 87>, <&clks 86>;
568 clock-names = "ipg", "per";
569 status = "disabled";
570 };
571
572 clks: ccm@53fd4000{
573 compatible = "fsl,imx53-ccm";
574 reg = <0x53fd4000 0x4000>;
575 interrupts = <0 71 0x04 0 72 0x04>;
576 #clock-cells = <1>;
577 };
578
579 gpio5: gpio@53fdc000 {
580 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
581 reg = <0x53fdc000 0x4000>;
582 interrupts = <103 104>;
583 gpio-controller;
584 #gpio-cells = <2>;
585 interrupt-controller;
586 #interrupt-cells = <2>;
587 };
588
589 gpio6: gpio@53fe0000 {
590 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
591 reg = <0x53fe0000 0x4000>;
592 interrupts = <105 106>;
593 gpio-controller;
594 #gpio-cells = <2>;
595 interrupt-controller;
596 #interrupt-cells = <2>;
597 };
598
599 gpio7: gpio@53fe4000 {
600 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
601 reg = <0x53fe4000 0x4000>;
602 interrupts = <107 108>;
603 gpio-controller;
604 #gpio-cells = <2>;
605 interrupt-controller;
606 #interrupt-cells = <2>;
607 };
608
609 i2c3: i2c@53fec000 {
610 #address-cells = <1>;
611 #size-cells = <0>;
612 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
613 reg = <0x53fec000 0x4000>;
614 interrupts = <64>;
615 clocks = <&clks 88>;
616 status = "disabled";
617 };
618
619 uart4: serial@53ff0000 {
620 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
621 reg = <0x53ff0000 0x4000>;
622 interrupts = <13>;
623 clocks = <&clks 65>, <&clks 66>;
624 clock-names = "ipg", "per";
625 status = "disabled";
626 };
627 };
628
629 aips@60000000 { /* AIPS2 */
630 compatible = "fsl,aips-bus", "simple-bus";
631 #address-cells = <1>;
632 #size-cells = <1>;
633 reg = <0x60000000 0x10000000>;
634 ranges;
635
636 uart5: serial@63f90000 {
637 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
638 reg = <0x63f90000 0x4000>;
639 interrupts = <86>;
640 clocks = <&clks 67>, <&clks 68>;
641 clock-names = "ipg", "per";
642 status = "disabled";
643 };
644
645 owire: owire@63fa4000 {
646 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
647 reg = <0x63fa4000 0x4000>;
648 clocks = <&clks 159>;
649 status = "disabled";
650 };
651
652 ecspi2: ecspi@63fac000 {
653 #address-cells = <1>;
654 #size-cells = <0>;
655 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
656 reg = <0x63fac000 0x4000>;
657 interrupts = <37>;
658 clocks = <&clks 53>, <&clks 54>;
659 clock-names = "ipg", "per";
660 status = "disabled";
661 };
662
663 sdma: sdma@63fb0000 {
664 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
665 reg = <0x63fb0000 0x4000>;
666 interrupts = <6>;
667 clocks = <&clks 56>, <&clks 56>;
668 clock-names = "ipg", "ahb";
669 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
670 };
671
672 cspi: cspi@63fc0000 {
673 #address-cells = <1>;
674 #size-cells = <0>;
675 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
676 reg = <0x63fc0000 0x4000>;
677 interrupts = <38>;
678 clocks = <&clks 55>, <&clks 0>;
679 clock-names = "ipg", "per";
680 status = "disabled";
681 };
682
683 i2c2: i2c@63fc4000 {
684 #address-cells = <1>;
685 #size-cells = <0>;
686 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
687 reg = <0x63fc4000 0x4000>;
688 interrupts = <63>;
689 clocks = <&clks 35>;
690 status = "disabled";
691 };
692
693 i2c1: i2c@63fc8000 {
694 #address-cells = <1>;
695 #size-cells = <0>;
696 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
697 reg = <0x63fc8000 0x4000>;
698 interrupts = <62>;
699 clocks = <&clks 34>;
700 status = "disabled";
701 };
702
703 ssi1: ssi@63fcc000 {
704 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
705 reg = <0x63fcc000 0x4000>;
706 interrupts = <29>;
707 clocks = <&clks 48>;
708 fsl,fifo-depth = <15>;
709 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
710 status = "disabled";
711 };
712
713 audmux: audmux@63fd0000 {
714 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
715 reg = <0x63fd0000 0x4000>;
716 status = "disabled";
717 };
718
719 nfc: nand@63fdb000 {
720 compatible = "fsl,imx53-nand";
721 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
722 interrupts = <8>;
723 clocks = <&clks 60>;
724 status = "disabled";
725 };
726
727 ssi3: ssi@63fe8000 {
728 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
729 reg = <0x63fe8000 0x4000>;
730 interrupts = <96>;
731 clocks = <&clks 50>;
732 fsl,fifo-depth = <15>;
733 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
734 status = "disabled";
735 };
736
737 fec: ethernet@63fec000 {
738 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
739 reg = <0x63fec000 0x4000>;
740 interrupts = <87>;
741 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
742 clock-names = "ipg", "ahb", "ptp";
743 status = "disabled";
744 };
745 };
746 };
747 };
Linux kernel - Deliverables
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