projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
ARM: imx53: use clock defines in DTS files
[deliverable/linux.git] / arch / arm / boot / dts / imx53.dtsi
1 /*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13 #include "skeleton.dtsi"
14 #include "imx53-pinfunc.h"
15 #include <dt-bindings/clock/imx5-clock.h>
16
17 / {
18 aliases {
19 gpio0 = &gpio1;
20 gpio1 = &gpio2;
21 gpio2 = &gpio3;
22 gpio3 = &gpio4;
23 gpio4 = &gpio5;
24 gpio5 = &gpio6;
25 gpio6 = &gpio7;
26 i2c0 = &i2c1;
27 i2c1 = &i2c2;
28 i2c2 = &i2c3;
29 serial0 = &uart1;
30 serial1 = &uart2;
31 serial2 = &uart3;
32 serial3 = &uart4;
33 serial4 = &uart5;
34 spi0 = &ecspi1;
35 spi1 = &ecspi2;
36 spi2 = &cspi;
37 };
38
39 cpus {
40 #address-cells = <1>;
41 #size-cells = <0>;
42 cpu@0 {
43 device_type = "cpu";
44 compatible = "arm,cortex-a8";
45 reg = <0x0>;
46 };
47 };
48
49 tzic: tz-interrupt-controller@0fffc000 {
50 compatible = "fsl,imx53-tzic", "fsl,tzic";
51 interrupt-controller;
52 #interrupt-cells = <1>;
53 reg = <0x0fffc000 0x4000>;
54 };
55
56 clocks {
57 #address-cells = <1>;
58 #size-cells = <0>;
59
60 ckil {
61 compatible = "fsl,imx-ckil", "fixed-clock";
62 clock-frequency = <32768>;
63 };
64
65 ckih1 {
66 compatible = "fsl,imx-ckih1", "fixed-clock";
67 clock-frequency = <22579200>;
68 };
69
70 ckih2 {
71 compatible = "fsl,imx-ckih2", "fixed-clock";
72 clock-frequency = <0>;
73 };
74
75 osc {
76 compatible = "fsl,imx-osc", "fixed-clock";
77 clock-frequency = <24000000>;
78 };
79 };
80
81 soc {
82 #address-cells = <1>;
83 #size-cells = <1>;
84 compatible = "simple-bus";
85 interrupt-parent = <&tzic>;
86 ranges;
87
88 ipu: ipu@18000000 {
89 #crtc-cells = <1>;
90 compatible = "fsl,imx53-ipu";
91 reg = <0x18000000 0x080000000>;
92 interrupts = <11 10>;
93 clocks = <&clks IMX5_CLK_IPU_GATE>,
94 <&clks IMX5_CLK_IPU_DI0_GATE>,
95 <&clks IMX5_CLK_IPU_DI1_GATE>;
96 clock-names = "bus", "di0", "di1";
97 resets = <&src 2>;
98 };
99
100 aips@50000000 { /* AIPS1 */
101 compatible = "fsl,aips-bus", "simple-bus";
102 #address-cells = <1>;
103 #size-cells = <1>;
104 reg = <0x50000000 0x10000000>;
105 ranges;
106
107 spba@50000000 {
108 compatible = "fsl,spba-bus", "simple-bus";
109 #address-cells = <1>;
110 #size-cells = <1>;
111 reg = <0x50000000 0x40000>;
112 ranges;
113
114 esdhc1: esdhc@50004000 {
115 compatible = "fsl,imx53-esdhc";
116 reg = <0x50004000 0x4000>;
117 interrupts = <1>;
118 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
119 <&clks IMX5_CLK_DUMMY>,
120 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
121 clock-names = "ipg", "ahb", "per";
122 bus-width = <4>;
123 status = "disabled";
124 };
125
126 esdhc2: esdhc@50008000 {
127 compatible = "fsl,imx53-esdhc";
128 reg = <0x50008000 0x4000>;
129 interrupts = <2>;
130 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
131 <&clks IMX5_CLK_DUMMY>,
132 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
133 clock-names = "ipg", "ahb", "per";
134 bus-width = <4>;
135 status = "disabled";
136 };
137
138 uart3: serial@5000c000 {
139 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
140 reg = <0x5000c000 0x4000>;
141 interrupts = <33>;
142 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
143 <&clks IMX5_CLK_UART3_PER_GATE>;
144 clock-names = "ipg", "per";
145 status = "disabled";
146 };
147
148 ecspi1: ecspi@50010000 {
149 #address-cells = <1>;
150 #size-cells = <0>;
151 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
152 reg = <0x50010000 0x4000>;
153 interrupts = <36>;
154 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
155 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
156 clock-names = "ipg", "per";
157 status = "disabled";
158 };
159
160 ssi2: ssi@50014000 {
161 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
162 reg = <0x50014000 0x4000>;
163 interrupts = <30>;
164 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
165 dmas = <&sdma 24 1 0>,
166 <&sdma 25 1 0>;
167 dma-names = "rx", "tx";
168 fsl,fifo-depth = <15>;
169 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
170 status = "disabled";
171 };
172
173 esdhc3: esdhc@50020000 {
174 compatible = "fsl,imx53-esdhc";
175 reg = <0x50020000 0x4000>;
176 interrupts = <3>;
177 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
178 <&clks IMX5_CLK_DUMMY>,
179 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
180 clock-names = "ipg", "ahb", "per";
181 bus-width = <4>;
182 status = "disabled";
183 };
184
185 esdhc4: esdhc@50024000 {
186 compatible = "fsl,imx53-esdhc";
187 reg = <0x50024000 0x4000>;
188 interrupts = <4>;
189 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
190 <&clks IMX5_CLK_DUMMY>,
191 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
192 clock-names = "ipg", "ahb", "per";
193 bus-width = <4>;
194 status = "disabled";
195 };
196 };
197
198 usbphy0: usbphy@0 {
199 compatible = "usb-nop-xceiv";
200 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
201 clock-names = "main_clk";
202 status = "okay";
203 };
204
205 usbphy1: usbphy@1 {
206 compatible = "usb-nop-xceiv";
207 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
208 clock-names = "main_clk";
209 status = "okay";
210 };
211
212 usbotg: usb@53f80000 {
213 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
214 reg = <0x53f80000 0x0200>;
215 interrupts = <18>;
216 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
217 fsl,usbmisc = <&usbmisc 0>;
218 fsl,usbphy = <&usbphy0>;
219 status = "disabled";
220 };
221
222 usbh1: usb@53f80200 {
223 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
224 reg = <0x53f80200 0x0200>;
225 interrupts = <14>;
226 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
227 fsl,usbmisc = <&usbmisc 1>;
228 fsl,usbphy = <&usbphy1>;
229 status = "disabled";
230 };
231
232 usbh2: usb@53f80400 {
233 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
234 reg = <0x53f80400 0x0200>;
235 interrupts = <16>;
236 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
237 fsl,usbmisc = <&usbmisc 2>;
238 status = "disabled";
239 };
240
241 usbh3: usb@53f80600 {
242 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
243 reg = <0x53f80600 0x0200>;
244 interrupts = <17>;
245 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
246 fsl,usbmisc = <&usbmisc 3>;
247 status = "disabled";
248 };
249
250 usbmisc: usbmisc@53f80800 {
251 #index-cells = <1>;
252 compatible = "fsl,imx53-usbmisc";
253 reg = <0x53f80800 0x200>;
254 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
255 };
256
257 gpio1: gpio@53f84000 {
258 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
259 reg = <0x53f84000 0x4000>;
260 interrupts = <50 51>;
261 gpio-controller;
262 #gpio-cells = <2>;
263 interrupt-controller;
264 #interrupt-cells = <2>;
265 };
266
267 gpio2: gpio@53f88000 {
268 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
269 reg = <0x53f88000 0x4000>;
270 interrupts = <52 53>;
271 gpio-controller;
272 #gpio-cells = <2>;
273 interrupt-controller;
274 #interrupt-cells = <2>;
275 };
276
277 gpio3: gpio@53f8c000 {
278 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
279 reg = <0x53f8c000 0x4000>;
280 interrupts = <54 55>;
281 gpio-controller;
282 #gpio-cells = <2>;
283 interrupt-controller;
284 #interrupt-cells = <2>;
285 };
286
287 gpio4: gpio@53f90000 {
288 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
289 reg = <0x53f90000 0x4000>;
290 interrupts = <56 57>;
291 gpio-controller;
292 #gpio-cells = <2>;
293 interrupt-controller;
294 #interrupt-cells = <2>;
295 };
296
297 kpp: kpp@53f94000 {
298 compatible = "fsl,imx53-kpp", "fsl,imx21-kpp";
299 reg = <0x53f94000 0x4000>;
300 interrupts = <60>;
301 clocks = <&clks IMX5_CLK_DUMMY>;
302 status = "disabled";
303 };
304
305 wdog1: wdog@53f98000 {
306 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
307 reg = <0x53f98000 0x4000>;
308 interrupts = <58>;
309 clocks = <&clks IMX5_CLK_DUMMY>;
310 };
311
312 wdog2: wdog@53f9c000 {
313 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
314 reg = <0x53f9c000 0x4000>;
315 interrupts = <59>;
316 clocks = <&clks IMX5_CLK_DUMMY>;
317 status = "disabled";
318 };
319
320 gpt: timer@53fa0000 {
321 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
322 reg = <0x53fa0000 0x4000>;
323 interrupts = <39>;
324 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
325 <&clks IMX5_CLK_GPT_HF_GATE>;
326 clock-names = "ipg", "per";
327 };
328
329 iomuxc: iomuxc@53fa8000 {
330 compatible = "fsl,imx53-iomuxc";
331 reg = <0x53fa8000 0x4000>;
332 };
333
334 gpr: iomuxc-gpr@53fa8000 {
335 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
336 reg = <0x53fa8000 0xc>;
337 };
338
339 ldb: ldb@53fa8008 {
340 #address-cells = <1>;
341 #size-cells = <0>;
342 compatible = "fsl,imx53-ldb";
343 reg = <0x53fa8008 0x4>;
344 gpr = <&gpr>;
345 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
346 <&clks IMX5_CLK_LDB_DI1_SEL>,
347 <&clks IMX5_CLK_IPU_DI0_SEL>,
348 <&clks IMX5_CLK_IPU_DI1_SEL>,
349 <&clks IMX5_CLK_LDB_DI0_GATE>,
350 <&clks IMX5_CLK_LDB_DI1_GATE>;
351 clock-names = "di0_pll", "di1_pll",
352 "di0_sel", "di1_sel",
353 "di0", "di1";
354 status = "disabled";
355
356 lvds-channel@0 {
357 reg = <0>;
358 crtcs = <&ipu 0>;
359 status = "disabled";
360 };
361
362 lvds-channel@1 {
363 reg = <1>;
364 crtcs = <&ipu 1>;
365 status = "disabled";
366 };
367 };
368
369 pwm1: pwm@53fb4000 {
370 #pwm-cells = <2>;
371 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
372 reg = <0x53fb4000 0x4000>;
373 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
374 <&clks IMX5_CLK_PWM1_HF_GATE>;
375 clock-names = "ipg", "per";
376 interrupts = <61>;
377 };
378
379 pwm2: pwm@53fb8000 {
380 #pwm-cells = <2>;
381 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
382 reg = <0x53fb8000 0x4000>;
383 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
384 <&clks IMX5_CLK_PWM2_HF_GATE>;
385 clock-names = "ipg", "per";
386 interrupts = <94>;
387 };
388
389 uart1: serial@53fbc000 {
390 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
391 reg = <0x53fbc000 0x4000>;
392 interrupts = <31>;
393 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
394 <&clks IMX5_CLK_UART1_PER_GATE>;
395 clock-names = "ipg", "per";
396 status = "disabled";
397 };
398
399 uart2: serial@53fc0000 {
400 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
401 reg = <0x53fc0000 0x4000>;
402 interrupts = <32>;
403 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
404 <&clks IMX5_CLK_UART2_PER_GATE>;
405 clock-names = "ipg", "per";
406 status = "disabled";
407 };
408
409 can1: can@53fc8000 {
410 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
411 reg = <0x53fc8000 0x4000>;
412 interrupts = <82>;
413 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
414 <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
415 clock-names = "ipg", "per";
416 status = "disabled";
417 };
418
419 can2: can@53fcc000 {
420 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
421 reg = <0x53fcc000 0x4000>;
422 interrupts = <83>;
423 clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
424 <&clks IMX5_CLK_CAN2_SERIAL_GATE>;
425 clock-names = "ipg", "per";
426 status = "disabled";
427 };
428
429 src: src@53fd0000 {
430 compatible = "fsl,imx53-src", "fsl,imx51-src";
431 reg = <0x53fd0000 0x4000>;
432 #reset-cells = <1>;
433 };
434
435 clks: ccm@53fd4000{
436 compatible = "fsl,imx53-ccm";
437 reg = <0x53fd4000 0x4000>;
438 interrupts = <0 71 0x04 0 72 0x04>;
439 #clock-cells = <1>;
440 };
441
442 gpio5: gpio@53fdc000 {
443 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
444 reg = <0x53fdc000 0x4000>;
445 interrupts = <103 104>;
446 gpio-controller;
447 #gpio-cells = <2>;
448 interrupt-controller;
449 #interrupt-cells = <2>;
450 };
451
452 gpio6: gpio@53fe0000 {
453 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
454 reg = <0x53fe0000 0x4000>;
455 interrupts = <105 106>;
456 gpio-controller;
457 #gpio-cells = <2>;
458 interrupt-controller;
459 #interrupt-cells = <2>;
460 };
461
462 gpio7: gpio@53fe4000 {
463 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
464 reg = <0x53fe4000 0x4000>;
465 interrupts = <107 108>;
466 gpio-controller;
467 #gpio-cells = <2>;
468 interrupt-controller;
469 #interrupt-cells = <2>;
470 };
471
472 i2c3: i2c@53fec000 {
473 #address-cells = <1>;
474 #size-cells = <0>;
475 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
476 reg = <0x53fec000 0x4000>;
477 interrupts = <64>;
478 clocks = <&clks IMX5_CLK_I2C3_GATE>;
479 status = "disabled";
480 };
481
482 uart4: serial@53ff0000 {
483 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
484 reg = <0x53ff0000 0x4000>;
485 interrupts = <13>;
486 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
487 <&clks IMX5_CLK_UART4_PER_GATE>;
488 clock-names = "ipg", "per";
489 status = "disabled";
490 };
491 };
492
493 aips@60000000 { /* AIPS2 */
494 compatible = "fsl,aips-bus", "simple-bus";
495 #address-cells = <1>;
496 #size-cells = <1>;
497 reg = <0x60000000 0x10000000>;
498 ranges;
499
500 iim: iim@63f98000 {
501 compatible = "fsl,imx53-iim", "fsl,imx27-iim";
502 reg = <0x63f98000 0x4000>;
503 interrupts = <69>;
504 clocks = <&clks IMX5_CLK_IIM_GATE>;
505 };
506
507 uart5: serial@63f90000 {
508 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
509 reg = <0x63f90000 0x4000>;
510 interrupts = <86>;
511 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
512 <&clks IMX5_CLK_UART5_PER_GATE>;
513 clock-names = "ipg", "per";
514 status = "disabled";
515 };
516
517 owire: owire@63fa4000 {
518 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
519 reg = <0x63fa4000 0x4000>;
520 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
521 status = "disabled";
522 };
523
524 ecspi2: ecspi@63fac000 {
525 #address-cells = <1>;
526 #size-cells = <0>;
527 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
528 reg = <0x63fac000 0x4000>;
529 interrupts = <37>;
530 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
531 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
532 clock-names = "ipg", "per";
533 status = "disabled";
534 };
535
536 sdma: sdma@63fb0000 {
537 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
538 reg = <0x63fb0000 0x4000>;
539 interrupts = <6>;
540 clocks = <&clks IMX5_CLK_SDMA_GATE>,
541 <&clks IMX5_CLK_SDMA_GATE>;
542 clock-names = "ipg", "ahb";
543 #dma-cells = <3>;
544 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
545 };
546
547 cspi: cspi@63fc0000 {
548 #address-cells = <1>;
549 #size-cells = <0>;
550 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
551 reg = <0x63fc0000 0x4000>;
552 interrupts = <38>;
553 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
554 <&clks IMX5_CLK_CSPI_IPG_GATE>;
555 clock-names = "ipg", "per";
556 status = "disabled";
557 };
558
559 i2c2: i2c@63fc4000 {
560 #address-cells = <1>;
561 #size-cells = <0>;
562 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
563 reg = <0x63fc4000 0x4000>;
564 interrupts = <63>;
565 clocks = <&clks IMX5_CLK_I2C2_GATE>;
566 status = "disabled";
567 };
568
569 i2c1: i2c@63fc8000 {
570 #address-cells = <1>;
571 #size-cells = <0>;
572 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
573 reg = <0x63fc8000 0x4000>;
574 interrupts = <62>;
575 clocks = <&clks IMX5_CLK_I2C1_GATE>;
576 status = "disabled";
577 };
578
579 ssi1: ssi@63fcc000 {
580 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
581 reg = <0x63fcc000 0x4000>;
582 interrupts = <29>;
583 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
584 dmas = <&sdma 28 0 0>,
585 <&sdma 29 0 0>;
586 dma-names = "rx", "tx";
587 fsl,fifo-depth = <15>;
588 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
589 status = "disabled";
590 };
591
592 audmux: audmux@63fd0000 {
593 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
594 reg = <0x63fd0000 0x4000>;
595 status = "disabled";
596 };
597
598 nfc: nand@63fdb000 {
599 compatible = "fsl,imx53-nand";
600 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
601 interrupts = <8>;
602 clocks = <&clks IMX5_CLK_NFC_GATE>;
603 status = "disabled";
604 };
605
606 ssi3: ssi@63fe8000 {
607 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
608 reg = <0x63fe8000 0x4000>;
609 interrupts = <96>;
610 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>;
611 dmas = <&sdma 46 0 0>,
612 <&sdma 47 0 0>;
613 dma-names = "rx", "tx";
614 fsl,fifo-depth = <15>;
615 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
616 status = "disabled";
617 };
618
619 fec: ethernet@63fec000 {
620 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
621 reg = <0x63fec000 0x4000>;
622 interrupts = <87>;
623 clocks = <&clks IMX5_CLK_FEC_GATE>,
624 <&clks IMX5_CLK_FEC_GATE>,
625 <&clks IMX5_CLK_FEC_GATE>;
626 clock-names = "ipg", "ahb", "ptp";
627 status = "disabled";
628 };
629
630 tve: tve@63ff0000 {
631 compatible = "fsl,imx53-tve";
632 reg = <0x63ff0000 0x1000>;
633 interrupts = <92>;
634 clocks = <&clks IMX5_CLK_TVE_GATE>,
635 <&clks IMX5_CLK_IPU_DI1_SEL>;
636 clock-names = "tve", "di_sel";
637 crtcs = <&ipu 1>;
638 status = "disabled";
639 };
640
641 vpu: vpu@63ff4000 {
642 compatible = "fsl,imx53-vpu";
643 reg = <0x63ff4000 0x1000>;
644 interrupts = <9>;
645 clocks = <&clks IMX5_CLK_VPU_GATE>,
646 <&clks IMX5_CLK_VPU_GATE>;
647 clock-names = "per", "ahb";
648 iram = <&ocram>;
649 status = "disabled";
650 };
651 };
652
653 ocram: sram@f8000000 {
654 compatible = "mmio-sram";
655 reg = <0xf8000000 0x20000>;
656 clocks = <&clks IMX5_CLK_OCRAM>;
657 };
658 };
659 };
Linux kernel - Deliverables
This page took 0.066655 seconds and 6 git commands to generate.