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ARM: dts: imx53: Add mmc aliases
[deliverable/linux.git] / arch / arm / boot / dts / imx53.dtsi
1 /*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13 #include "skeleton.dtsi"
14 #include "imx53-pinfunc.h"
15 #include <dt-bindings/clock/imx5-clock.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/input/input.h>
18
19 / {
20 aliases {
21 gpio0 = &gpio1;
22 gpio1 = &gpio2;
23 gpio2 = &gpio3;
24 gpio3 = &gpio4;
25 gpio4 = &gpio5;
26 gpio5 = &gpio6;
27 gpio6 = &gpio7;
28 i2c0 = &i2c1;
29 i2c1 = &i2c2;
30 i2c2 = &i2c3;
31 mmc0 = &esdhc1;
32 mmc1 = &esdhc2;
33 mmc2 = &esdhc3;
34 mmc3 = &esdhc4;
35 serial0 = &uart1;
36 serial1 = &uart2;
37 serial2 = &uart3;
38 serial3 = &uart4;
39 serial4 = &uart5;
40 spi0 = &ecspi1;
41 spi1 = &ecspi2;
42 spi2 = &cspi;
43 };
44
45 cpus {
46 #address-cells = <1>;
47 #size-cells = <0>;
48 cpu@0 {
49 device_type = "cpu";
50 compatible = "arm,cortex-a8";
51 reg = <0x0>;
52 };
53 };
54
55 tzic: tz-interrupt-controller@0fffc000 {
56 compatible = "fsl,imx53-tzic", "fsl,tzic";
57 interrupt-controller;
58 #interrupt-cells = <1>;
59 reg = <0x0fffc000 0x4000>;
60 };
61
62 clocks {
63 #address-cells = <1>;
64 #size-cells = <0>;
65
66 ckil {
67 compatible = "fsl,imx-ckil", "fixed-clock";
68 clock-frequency = <32768>;
69 };
70
71 ckih1 {
72 compatible = "fsl,imx-ckih1", "fixed-clock";
73 clock-frequency = <22579200>;
74 };
75
76 ckih2 {
77 compatible = "fsl,imx-ckih2", "fixed-clock";
78 clock-frequency = <0>;
79 };
80
81 osc {
82 compatible = "fsl,imx-osc", "fixed-clock";
83 clock-frequency = <24000000>;
84 };
85 };
86
87 soc {
88 #address-cells = <1>;
89 #size-cells = <1>;
90 compatible = "simple-bus";
91 interrupt-parent = <&tzic>;
92 ranges;
93
94 sata: sata@10000000 {
95 compatible = "fsl,imx53-ahci";
96 reg = <0x10000000 0x1000>;
97 interrupts = <28>;
98 clocks = <&clks IMX5_CLK_SATA_GATE>,
99 <&clks IMX5_CLK_SATA_REF>,
100 <&clks IMX5_CLK_AHB>;
101 clock-names = "sata_gate", "sata_ref", "ahb";
102 status = "disabled";
103 };
104
105 ipu: ipu@18000000 {
106 #crtc-cells = <1>;
107 compatible = "fsl,imx53-ipu";
108 reg = <0x18000000 0x080000000>;
109 interrupts = <11 10>;
110 clocks = <&clks IMX5_CLK_IPU_GATE>,
111 <&clks IMX5_CLK_IPU_DI0_GATE>,
112 <&clks IMX5_CLK_IPU_DI1_GATE>;
113 clock-names = "bus", "di0", "di1";
114 resets = <&src 2>;
115 };
116
117 aips@50000000 { /* AIPS1 */
118 compatible = "fsl,aips-bus", "simple-bus";
119 #address-cells = <1>;
120 #size-cells = <1>;
121 reg = <0x50000000 0x10000000>;
122 ranges;
123
124 spba@50000000 {
125 compatible = "fsl,spba-bus", "simple-bus";
126 #address-cells = <1>;
127 #size-cells = <1>;
128 reg = <0x50000000 0x40000>;
129 ranges;
130
131 esdhc1: esdhc@50004000 {
132 compatible = "fsl,imx53-esdhc";
133 reg = <0x50004000 0x4000>;
134 interrupts = <1>;
135 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
136 <&clks IMX5_CLK_DUMMY>,
137 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
138 clock-names = "ipg", "ahb", "per";
139 bus-width = <4>;
140 status = "disabled";
141 };
142
143 esdhc2: esdhc@50008000 {
144 compatible = "fsl,imx53-esdhc";
145 reg = <0x50008000 0x4000>;
146 interrupts = <2>;
147 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
148 <&clks IMX5_CLK_DUMMY>,
149 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
150 clock-names = "ipg", "ahb", "per";
151 bus-width = <4>;
152 status = "disabled";
153 };
154
155 uart3: serial@5000c000 {
156 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
157 reg = <0x5000c000 0x4000>;
158 interrupts = <33>;
159 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
160 <&clks IMX5_CLK_UART3_PER_GATE>;
161 clock-names = "ipg", "per";
162 status = "disabled";
163 };
164
165 ecspi1: ecspi@50010000 {
166 #address-cells = <1>;
167 #size-cells = <0>;
168 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
169 reg = <0x50010000 0x4000>;
170 interrupts = <36>;
171 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
172 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
173 clock-names = "ipg", "per";
174 status = "disabled";
175 };
176
177 ssi2: ssi@50014000 {
178 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
179 reg = <0x50014000 0x4000>;
180 interrupts = <30>;
181 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
182 dmas = <&sdma 24 1 0>,
183 <&sdma 25 1 0>;
184 dma-names = "rx", "tx";
185 fsl,fifo-depth = <15>;
186 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
187 status = "disabled";
188 };
189
190 esdhc3: esdhc@50020000 {
191 compatible = "fsl,imx53-esdhc";
192 reg = <0x50020000 0x4000>;
193 interrupts = <3>;
194 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
195 <&clks IMX5_CLK_DUMMY>,
196 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
197 clock-names = "ipg", "ahb", "per";
198 bus-width = <4>;
199 status = "disabled";
200 };
201
202 esdhc4: esdhc@50024000 {
203 compatible = "fsl,imx53-esdhc";
204 reg = <0x50024000 0x4000>;
205 interrupts = <4>;
206 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
207 <&clks IMX5_CLK_DUMMY>,
208 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
209 clock-names = "ipg", "ahb", "per";
210 bus-width = <4>;
211 status = "disabled";
212 };
213 };
214
215 usbphy0: usbphy@0 {
216 compatible = "usb-nop-xceiv";
217 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
218 clock-names = "main_clk";
219 status = "okay";
220 };
221
222 usbphy1: usbphy@1 {
223 compatible = "usb-nop-xceiv";
224 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
225 clock-names = "main_clk";
226 status = "okay";
227 };
228
229 usbotg: usb@53f80000 {
230 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
231 reg = <0x53f80000 0x0200>;
232 interrupts = <18>;
233 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
234 fsl,usbmisc = <&usbmisc 0>;
235 fsl,usbphy = <&usbphy0>;
236 status = "disabled";
237 };
238
239 usbh1: usb@53f80200 {
240 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
241 reg = <0x53f80200 0x0200>;
242 interrupts = <14>;
243 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
244 fsl,usbmisc = <&usbmisc 1>;
245 fsl,usbphy = <&usbphy1>;
246 status = "disabled";
247 };
248
249 usbh2: usb@53f80400 {
250 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
251 reg = <0x53f80400 0x0200>;
252 interrupts = <16>;
253 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
254 fsl,usbmisc = <&usbmisc 2>;
255 status = "disabled";
256 };
257
258 usbh3: usb@53f80600 {
259 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
260 reg = <0x53f80600 0x0200>;
261 interrupts = <17>;
262 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
263 fsl,usbmisc = <&usbmisc 3>;
264 status = "disabled";
265 };
266
267 usbmisc: usbmisc@53f80800 {
268 #index-cells = <1>;
269 compatible = "fsl,imx53-usbmisc";
270 reg = <0x53f80800 0x200>;
271 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
272 };
273
274 gpio1: gpio@53f84000 {
275 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
276 reg = <0x53f84000 0x4000>;
277 interrupts = <50 51>;
278 gpio-controller;
279 #gpio-cells = <2>;
280 interrupt-controller;
281 #interrupt-cells = <2>;
282 };
283
284 gpio2: gpio@53f88000 {
285 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
286 reg = <0x53f88000 0x4000>;
287 interrupts = <52 53>;
288 gpio-controller;
289 #gpio-cells = <2>;
290 interrupt-controller;
291 #interrupt-cells = <2>;
292 };
293
294 gpio3: gpio@53f8c000 {
295 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
296 reg = <0x53f8c000 0x4000>;
297 interrupts = <54 55>;
298 gpio-controller;
299 #gpio-cells = <2>;
300 interrupt-controller;
301 #interrupt-cells = <2>;
302 };
303
304 gpio4: gpio@53f90000 {
305 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
306 reg = <0x53f90000 0x4000>;
307 interrupts = <56 57>;
308 gpio-controller;
309 #gpio-cells = <2>;
310 interrupt-controller;
311 #interrupt-cells = <2>;
312 };
313
314 kpp: kpp@53f94000 {
315 compatible = "fsl,imx53-kpp", "fsl,imx21-kpp";
316 reg = <0x53f94000 0x4000>;
317 interrupts = <60>;
318 clocks = <&clks IMX5_CLK_DUMMY>;
319 status = "disabled";
320 };
321
322 wdog1: wdog@53f98000 {
323 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
324 reg = <0x53f98000 0x4000>;
325 interrupts = <58>;
326 clocks = <&clks IMX5_CLK_DUMMY>;
327 };
328
329 wdog2: wdog@53f9c000 {
330 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
331 reg = <0x53f9c000 0x4000>;
332 interrupts = <59>;
333 clocks = <&clks IMX5_CLK_DUMMY>;
334 status = "disabled";
335 };
336
337 gpt: timer@53fa0000 {
338 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
339 reg = <0x53fa0000 0x4000>;
340 interrupts = <39>;
341 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
342 <&clks IMX5_CLK_GPT_HF_GATE>;
343 clock-names = "ipg", "per";
344 };
345
346 iomuxc: iomuxc@53fa8000 {
347 compatible = "fsl,imx53-iomuxc";
348 reg = <0x53fa8000 0x4000>;
349 };
350
351 gpr: iomuxc-gpr@53fa8000 {
352 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
353 reg = <0x53fa8000 0xc>;
354 };
355
356 ldb: ldb@53fa8008 {
357 #address-cells = <1>;
358 #size-cells = <0>;
359 compatible = "fsl,imx53-ldb";
360 reg = <0x53fa8008 0x4>;
361 gpr = <&gpr>;
362 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
363 <&clks IMX5_CLK_LDB_DI1_SEL>,
364 <&clks IMX5_CLK_IPU_DI0_SEL>,
365 <&clks IMX5_CLK_IPU_DI1_SEL>,
366 <&clks IMX5_CLK_LDB_DI0_GATE>,
367 <&clks IMX5_CLK_LDB_DI1_GATE>;
368 clock-names = "di0_pll", "di1_pll",
369 "di0_sel", "di1_sel",
370 "di0", "di1";
371 status = "disabled";
372
373 lvds-channel@0 {
374 reg = <0>;
375 crtcs = <&ipu 0>;
376 status = "disabled";
377 };
378
379 lvds-channel@1 {
380 reg = <1>;
381 crtcs = <&ipu 1>;
382 status = "disabled";
383 };
384 };
385
386 pwm1: pwm@53fb4000 {
387 #pwm-cells = <2>;
388 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
389 reg = <0x53fb4000 0x4000>;
390 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
391 <&clks IMX5_CLK_PWM1_HF_GATE>;
392 clock-names = "ipg", "per";
393 interrupts = <61>;
394 };
395
396 pwm2: pwm@53fb8000 {
397 #pwm-cells = <2>;
398 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
399 reg = <0x53fb8000 0x4000>;
400 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
401 <&clks IMX5_CLK_PWM2_HF_GATE>;
402 clock-names = "ipg", "per";
403 interrupts = <94>;
404 };
405
406 uart1: serial@53fbc000 {
407 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
408 reg = <0x53fbc000 0x4000>;
409 interrupts = <31>;
410 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
411 <&clks IMX5_CLK_UART1_PER_GATE>;
412 clock-names = "ipg", "per";
413 status = "disabled";
414 };
415
416 uart2: serial@53fc0000 {
417 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
418 reg = <0x53fc0000 0x4000>;
419 interrupts = <32>;
420 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
421 <&clks IMX5_CLK_UART2_PER_GATE>;
422 clock-names = "ipg", "per";
423 status = "disabled";
424 };
425
426 can1: can@53fc8000 {
427 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
428 reg = <0x53fc8000 0x4000>;
429 interrupts = <82>;
430 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
431 <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
432 clock-names = "ipg", "per";
433 status = "disabled";
434 };
435
436 can2: can@53fcc000 {
437 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
438 reg = <0x53fcc000 0x4000>;
439 interrupts = <83>;
440 clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
441 <&clks IMX5_CLK_CAN2_SERIAL_GATE>;
442 clock-names = "ipg", "per";
443 status = "disabled";
444 };
445
446 src: src@53fd0000 {
447 compatible = "fsl,imx53-src", "fsl,imx51-src";
448 reg = <0x53fd0000 0x4000>;
449 #reset-cells = <1>;
450 };
451
452 clks: ccm@53fd4000{
453 compatible = "fsl,imx53-ccm";
454 reg = <0x53fd4000 0x4000>;
455 interrupts = <0 71 0x04 0 72 0x04>;
456 #clock-cells = <1>;
457 };
458
459 gpio5: gpio@53fdc000 {
460 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
461 reg = <0x53fdc000 0x4000>;
462 interrupts = <103 104>;
463 gpio-controller;
464 #gpio-cells = <2>;
465 interrupt-controller;
466 #interrupt-cells = <2>;
467 };
468
469 gpio6: gpio@53fe0000 {
470 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
471 reg = <0x53fe0000 0x4000>;
472 interrupts = <105 106>;
473 gpio-controller;
474 #gpio-cells = <2>;
475 interrupt-controller;
476 #interrupt-cells = <2>;
477 };
478
479 gpio7: gpio@53fe4000 {
480 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
481 reg = <0x53fe4000 0x4000>;
482 interrupts = <107 108>;
483 gpio-controller;
484 #gpio-cells = <2>;
485 interrupt-controller;
486 #interrupt-cells = <2>;
487 };
488
489 i2c3: i2c@53fec000 {
490 #address-cells = <1>;
491 #size-cells = <0>;
492 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
493 reg = <0x53fec000 0x4000>;
494 interrupts = <64>;
495 clocks = <&clks IMX5_CLK_I2C3_GATE>;
496 status = "disabled";
497 };
498
499 uart4: serial@53ff0000 {
500 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
501 reg = <0x53ff0000 0x4000>;
502 interrupts = <13>;
503 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
504 <&clks IMX5_CLK_UART4_PER_GATE>;
505 clock-names = "ipg", "per";
506 status = "disabled";
507 };
508 };
509
510 aips@60000000 { /* AIPS2 */
511 compatible = "fsl,aips-bus", "simple-bus";
512 #address-cells = <1>;
513 #size-cells = <1>;
514 reg = <0x60000000 0x10000000>;
515 ranges;
516
517 iim: iim@63f98000 {
518 compatible = "fsl,imx53-iim", "fsl,imx27-iim";
519 reg = <0x63f98000 0x4000>;
520 interrupts = <69>;
521 clocks = <&clks IMX5_CLK_IIM_GATE>;
522 };
523
524 uart5: serial@63f90000 {
525 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
526 reg = <0x63f90000 0x4000>;
527 interrupts = <86>;
528 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
529 <&clks IMX5_CLK_UART5_PER_GATE>;
530 clock-names = "ipg", "per";
531 status = "disabled";
532 };
533
534 owire: owire@63fa4000 {
535 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
536 reg = <0x63fa4000 0x4000>;
537 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
538 status = "disabled";
539 };
540
541 ecspi2: ecspi@63fac000 {
542 #address-cells = <1>;
543 #size-cells = <0>;
544 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
545 reg = <0x63fac000 0x4000>;
546 interrupts = <37>;
547 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
548 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
549 clock-names = "ipg", "per";
550 status = "disabled";
551 };
552
553 sdma: sdma@63fb0000 {
554 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
555 reg = <0x63fb0000 0x4000>;
556 interrupts = <6>;
557 clocks = <&clks IMX5_CLK_SDMA_GATE>,
558 <&clks IMX5_CLK_SDMA_GATE>;
559 clock-names = "ipg", "ahb";
560 #dma-cells = <3>;
561 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
562 };
563
564 cspi: cspi@63fc0000 {
565 #address-cells = <1>;
566 #size-cells = <0>;
567 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
568 reg = <0x63fc0000 0x4000>;
569 interrupts = <38>;
570 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
571 <&clks IMX5_CLK_CSPI_IPG_GATE>;
572 clock-names = "ipg", "per";
573 status = "disabled";
574 };
575
576 i2c2: i2c@63fc4000 {
577 #address-cells = <1>;
578 #size-cells = <0>;
579 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
580 reg = <0x63fc4000 0x4000>;
581 interrupts = <63>;
582 clocks = <&clks IMX5_CLK_I2C2_GATE>;
583 status = "disabled";
584 };
585
586 i2c1: i2c@63fc8000 {
587 #address-cells = <1>;
588 #size-cells = <0>;
589 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
590 reg = <0x63fc8000 0x4000>;
591 interrupts = <62>;
592 clocks = <&clks IMX5_CLK_I2C1_GATE>;
593 status = "disabled";
594 };
595
596 ssi1: ssi@63fcc000 {
597 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
598 reg = <0x63fcc000 0x4000>;
599 interrupts = <29>;
600 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
601 dmas = <&sdma 28 0 0>,
602 <&sdma 29 0 0>;
603 dma-names = "rx", "tx";
604 fsl,fifo-depth = <15>;
605 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
606 status = "disabled";
607 };
608
609 audmux: audmux@63fd0000 {
610 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
611 reg = <0x63fd0000 0x4000>;
612 status = "disabled";
613 };
614
615 nfc: nand@63fdb000 {
616 compatible = "fsl,imx53-nand";
617 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
618 interrupts = <8>;
619 clocks = <&clks IMX5_CLK_NFC_GATE>;
620 status = "disabled";
621 };
622
623 ssi3: ssi@63fe8000 {
624 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
625 reg = <0x63fe8000 0x4000>;
626 interrupts = <96>;
627 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>;
628 dmas = <&sdma 46 0 0>,
629 <&sdma 47 0 0>;
630 dma-names = "rx", "tx";
631 fsl,fifo-depth = <15>;
632 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
633 status = "disabled";
634 };
635
636 fec: ethernet@63fec000 {
637 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
638 reg = <0x63fec000 0x4000>;
639 interrupts = <87>;
640 clocks = <&clks IMX5_CLK_FEC_GATE>,
641 <&clks IMX5_CLK_FEC_GATE>,
642 <&clks IMX5_CLK_FEC_GATE>;
643 clock-names = "ipg", "ahb", "ptp";
644 status = "disabled";
645 };
646
647 tve: tve@63ff0000 {
648 compatible = "fsl,imx53-tve";
649 reg = <0x63ff0000 0x1000>;
650 interrupts = <92>;
651 clocks = <&clks IMX5_CLK_TVE_GATE>,
652 <&clks IMX5_CLK_IPU_DI1_SEL>;
653 clock-names = "tve", "di_sel";
654 crtcs = <&ipu 1>;
655 status = "disabled";
656 };
657
658 vpu: vpu@63ff4000 {
659 compatible = "fsl,imx53-vpu";
660 reg = <0x63ff4000 0x1000>;
661 interrupts = <9>;
662 clocks = <&clks IMX5_CLK_VPU_GATE>,
663 <&clks IMX5_CLK_VPU_GATE>;
664 clock-names = "per", "ahb";
665 iram = <&ocram>;
666 status = "disabled";
667 };
668 };
669
670 ocram: sram@f8000000 {
671 compatible = "mmio-sram";
672 reg = <0xf8000000 0x20000>;
673 clocks = <&clks IMX5_CLK_OCRAM>;
674 };
675 };
676 };
Linux kernel - Deliverables
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