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ARM: dts: imx53: Add DMA configuration for UART
[deliverable/linux.git] / arch / arm / boot / dts / imx53.dtsi
1 /*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13 #include "skeleton.dtsi"
14 #include "imx53-pinfunc.h"
15 #include <dt-bindings/clock/imx5-clock.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/input/input.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
19
20 / {
21 aliases {
22 ethernet0 = &fec;
23 gpio0 = &gpio1;
24 gpio1 = &gpio2;
25 gpio2 = &gpio3;
26 gpio3 = &gpio4;
27 gpio4 = &gpio5;
28 gpio5 = &gpio6;
29 gpio6 = &gpio7;
30 i2c0 = &i2c1;
31 i2c1 = &i2c2;
32 i2c2 = &i2c3;
33 mmc0 = &esdhc1;
34 mmc1 = &esdhc2;
35 mmc2 = &esdhc3;
36 mmc3 = &esdhc4;
37 serial0 = &uart1;
38 serial1 = &uart2;
39 serial2 = &uart3;
40 serial3 = &uart4;
41 serial4 = &uart5;
42 spi0 = &ecspi1;
43 spi1 = &ecspi2;
44 spi2 = &cspi;
45 };
46
47 cpus {
48 #address-cells = <1>;
49 #size-cells = <0>;
50 cpu0: cpu@0 {
51 device_type = "cpu";
52 compatible = "arm,cortex-a8";
53 reg = <0x0>;
54 clocks = <&clks IMX5_CLK_ARM>;
55 clock-latency = <61036>;
56 voltage-tolerance = <5>;
57 operating-points = <
58 /* kHz */
59 166666 850000
60 400000 900000
61 800000 1050000
62 1000000 1200000
63 1200000 1300000
64 >;
65 };
66 };
67
68 display-subsystem {
69 compatible = "fsl,imx-display-subsystem";
70 ports = <&ipu_di0>, <&ipu_di1>;
71 };
72
73 tzic: tz-interrupt-controller@0fffc000 {
74 compatible = "fsl,imx53-tzic", "fsl,tzic";
75 interrupt-controller;
76 #interrupt-cells = <1>;
77 reg = <0x0fffc000 0x4000>;
78 };
79
80 clocks {
81 #address-cells = <1>;
82 #size-cells = <0>;
83
84 ckil {
85 compatible = "fsl,imx-ckil", "fixed-clock";
86 #clock-cells = <0>;
87 clock-frequency = <32768>;
88 };
89
90 ckih1 {
91 compatible = "fsl,imx-ckih1", "fixed-clock";
92 #clock-cells = <0>;
93 clock-frequency = <22579200>;
94 };
95
96 ckih2 {
97 compatible = "fsl,imx-ckih2", "fixed-clock";
98 #clock-cells = <0>;
99 clock-frequency = <0>;
100 };
101
102 osc {
103 compatible = "fsl,imx-osc", "fixed-clock";
104 #clock-cells = <0>;
105 clock-frequency = <24000000>;
106 };
107 };
108
109 soc {
110 #address-cells = <1>;
111 #size-cells = <1>;
112 compatible = "simple-bus";
113 interrupt-parent = <&tzic>;
114 ranges;
115
116 sata: sata@10000000 {
117 compatible = "fsl,imx53-ahci";
118 reg = <0x10000000 0x1000>;
119 interrupts = <28>;
120 clocks = <&clks IMX5_CLK_SATA_GATE>,
121 <&clks IMX5_CLK_SATA_REF>,
122 <&clks IMX5_CLK_AHB>;
123 clock-names = "sata", "sata_ref", "ahb";
124 status = "disabled";
125 };
126
127 ipu: ipu@18000000 {
128 #address-cells = <1>;
129 #size-cells = <0>;
130 compatible = "fsl,imx53-ipu";
131 reg = <0x18000000 0x08000000>;
132 interrupts = <11 10>;
133 clocks = <&clks IMX5_CLK_IPU_GATE>,
134 <&clks IMX5_CLK_IPU_DI0_GATE>,
135 <&clks IMX5_CLK_IPU_DI1_GATE>;
136 clock-names = "bus", "di0", "di1";
137 resets = <&src 2>;
138
139 ipu_di0: port@2 {
140 #address-cells = <1>;
141 #size-cells = <0>;
142 reg = <2>;
143
144 ipu_di0_disp0: endpoint@0 {
145 reg = <0>;
146 };
147
148 ipu_di0_lvds0: endpoint@1 {
149 reg = <1>;
150 remote-endpoint = <&lvds0_in>;
151 };
152 };
153
154 ipu_di1: port@3 {
155 #address-cells = <1>;
156 #size-cells = <0>;
157 reg = <3>;
158
159 ipu_di1_disp1: endpoint@0 {
160 reg = <0>;
161 };
162
163 ipu_di1_lvds1: endpoint@1 {
164 reg = <1>;
165 remote-endpoint = <&lvds1_in>;
166 };
167
168 ipu_di1_tve: endpoint@2 {
169 reg = <2>;
170 remote-endpoint = <&tve_in>;
171 };
172 };
173 };
174
175 aips@50000000 { /* AIPS1 */
176 compatible = "fsl,aips-bus", "simple-bus";
177 #address-cells = <1>;
178 #size-cells = <1>;
179 reg = <0x50000000 0x10000000>;
180 ranges;
181
182 spba@50000000 {
183 compatible = "fsl,spba-bus", "simple-bus";
184 #address-cells = <1>;
185 #size-cells = <1>;
186 reg = <0x50000000 0x40000>;
187 ranges;
188
189 esdhc1: esdhc@50004000 {
190 compatible = "fsl,imx53-esdhc";
191 reg = <0x50004000 0x4000>;
192 interrupts = <1>;
193 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
194 <&clks IMX5_CLK_DUMMY>,
195 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
196 clock-names = "ipg", "ahb", "per";
197 bus-width = <4>;
198 status = "disabled";
199 };
200
201 esdhc2: esdhc@50008000 {
202 compatible = "fsl,imx53-esdhc";
203 reg = <0x50008000 0x4000>;
204 interrupts = <2>;
205 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
206 <&clks IMX5_CLK_DUMMY>,
207 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
208 clock-names = "ipg", "ahb", "per";
209 bus-width = <4>;
210 status = "disabled";
211 };
212
213 uart3: serial@5000c000 {
214 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
215 reg = <0x5000c000 0x4000>;
216 interrupts = <33>;
217 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
218 <&clks IMX5_CLK_UART3_PER_GATE>;
219 clock-names = "ipg", "per";
220 dmas = <&sdma 42 4 0>, <&sdma 43 4 0>;
221 dma-names = "rx", "tx";
222 status = "disabled";
223 };
224
225 ecspi1: ecspi@50010000 {
226 #address-cells = <1>;
227 #size-cells = <0>;
228 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
229 reg = <0x50010000 0x4000>;
230 interrupts = <36>;
231 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
232 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
233 clock-names = "ipg", "per";
234 status = "disabled";
235 };
236
237 ssi2: ssi@50014000 {
238 #sound-dai-cells = <0>;
239 compatible = "fsl,imx53-ssi",
240 "fsl,imx51-ssi",
241 "fsl,imx21-ssi";
242 reg = <0x50014000 0x4000>;
243 interrupts = <30>;
244 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
245 <&clks IMX5_CLK_SSI2_ROOT_GATE>;
246 clock-names = "ipg", "baud";
247 dmas = <&sdma 24 1 0>,
248 <&sdma 25 1 0>;
249 dma-names = "rx", "tx";
250 fsl,fifo-depth = <15>;
251 status = "disabled";
252 };
253
254 esdhc3: esdhc@50020000 {
255 compatible = "fsl,imx53-esdhc";
256 reg = <0x50020000 0x4000>;
257 interrupts = <3>;
258 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
259 <&clks IMX5_CLK_DUMMY>,
260 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
261 clock-names = "ipg", "ahb", "per";
262 bus-width = <4>;
263 status = "disabled";
264 };
265
266 esdhc4: esdhc@50024000 {
267 compatible = "fsl,imx53-esdhc";
268 reg = <0x50024000 0x4000>;
269 interrupts = <4>;
270 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
271 <&clks IMX5_CLK_DUMMY>,
272 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
273 clock-names = "ipg", "ahb", "per";
274 bus-width = <4>;
275 status = "disabled";
276 };
277 };
278
279 aipstz1: bridge@53f00000 {
280 compatible = "fsl,imx53-aipstz";
281 reg = <0x53f00000 0x60>;
282 };
283
284 usbphy0: usbphy@0 {
285 compatible = "usb-nop-xceiv";
286 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
287 clock-names = "main_clk";
288 status = "okay";
289 };
290
291 usbphy1: usbphy@1 {
292 compatible = "usb-nop-xceiv";
293 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
294 clock-names = "main_clk";
295 status = "okay";
296 };
297
298 usbotg: usb@53f80000 {
299 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
300 reg = <0x53f80000 0x0200>;
301 interrupts = <18>;
302 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
303 fsl,usbmisc = <&usbmisc 0>;
304 fsl,usbphy = <&usbphy0>;
305 status = "disabled";
306 };
307
308 usbh1: usb@53f80200 {
309 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
310 reg = <0x53f80200 0x0200>;
311 interrupts = <14>;
312 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
313 fsl,usbmisc = <&usbmisc 1>;
314 fsl,usbphy = <&usbphy1>;
315 dr_mode = "host";
316 status = "disabled";
317 };
318
319 usbh2: usb@53f80400 {
320 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
321 reg = <0x53f80400 0x0200>;
322 interrupts = <16>;
323 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
324 fsl,usbmisc = <&usbmisc 2>;
325 dr_mode = "host";
326 status = "disabled";
327 };
328
329 usbh3: usb@53f80600 {
330 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
331 reg = <0x53f80600 0x0200>;
332 interrupts = <17>;
333 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
334 fsl,usbmisc = <&usbmisc 3>;
335 dr_mode = "host";
336 status = "disabled";
337 };
338
339 usbmisc: usbmisc@53f80800 {
340 #index-cells = <1>;
341 compatible = "fsl,imx53-usbmisc";
342 reg = <0x53f80800 0x200>;
343 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
344 };
345
346 gpio1: gpio@53f84000 {
347 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
348 reg = <0x53f84000 0x4000>;
349 interrupts = <50 51>;
350 gpio-controller;
351 #gpio-cells = <2>;
352 interrupt-controller;
353 #interrupt-cells = <2>;
354 };
355
356 gpio2: gpio@53f88000 {
357 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
358 reg = <0x53f88000 0x4000>;
359 interrupts = <52 53>;
360 gpio-controller;
361 #gpio-cells = <2>;
362 interrupt-controller;
363 #interrupt-cells = <2>;
364 };
365
366 gpio3: gpio@53f8c000 {
367 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
368 reg = <0x53f8c000 0x4000>;
369 interrupts = <54 55>;
370 gpio-controller;
371 #gpio-cells = <2>;
372 interrupt-controller;
373 #interrupt-cells = <2>;
374 };
375
376 gpio4: gpio@53f90000 {
377 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
378 reg = <0x53f90000 0x4000>;
379 interrupts = <56 57>;
380 gpio-controller;
381 #gpio-cells = <2>;
382 interrupt-controller;
383 #interrupt-cells = <2>;
384 };
385
386 kpp: kpp@53f94000 {
387 compatible = "fsl,imx53-kpp", "fsl,imx21-kpp";
388 reg = <0x53f94000 0x4000>;
389 interrupts = <60>;
390 clocks = <&clks IMX5_CLK_DUMMY>;
391 status = "disabled";
392 };
393
394 wdog1: wdog@53f98000 {
395 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
396 reg = <0x53f98000 0x4000>;
397 interrupts = <58>;
398 clocks = <&clks IMX5_CLK_DUMMY>;
399 };
400
401 wdog2: wdog@53f9c000 {
402 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
403 reg = <0x53f9c000 0x4000>;
404 interrupts = <59>;
405 clocks = <&clks IMX5_CLK_DUMMY>;
406 status = "disabled";
407 };
408
409 gpt: timer@53fa0000 {
410 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
411 reg = <0x53fa0000 0x4000>;
412 interrupts = <39>;
413 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
414 <&clks IMX5_CLK_GPT_HF_GATE>;
415 clock-names = "ipg", "per";
416 };
417
418 iomuxc: iomuxc@53fa8000 {
419 compatible = "fsl,imx53-iomuxc";
420 reg = <0x53fa8000 0x4000>;
421 };
422
423 gpr: iomuxc-gpr@53fa8000 {
424 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
425 reg = <0x53fa8000 0xc>;
426 };
427
428 ldb: ldb@53fa8008 {
429 #address-cells = <1>;
430 #size-cells = <0>;
431 compatible = "fsl,imx53-ldb";
432 reg = <0x53fa8008 0x4>;
433 gpr = <&gpr>;
434 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
435 <&clks IMX5_CLK_LDB_DI1_SEL>,
436 <&clks IMX5_CLK_IPU_DI0_SEL>,
437 <&clks IMX5_CLK_IPU_DI1_SEL>,
438 <&clks IMX5_CLK_LDB_DI0_GATE>,
439 <&clks IMX5_CLK_LDB_DI1_GATE>;
440 clock-names = "di0_pll", "di1_pll",
441 "di0_sel", "di1_sel",
442 "di0", "di1";
443 status = "disabled";
444
445 lvds-channel@0 {
446 #address-cells = <1>;
447 #size-cells = <0>;
448 reg = <0>;
449 status = "disabled";
450
451 port@0 {
452 reg = <0>;
453
454 lvds0_in: endpoint {
455 remote-endpoint = <&ipu_di0_lvds0>;
456 };
457 };
458 };
459
460 lvds-channel@1 {
461 #address-cells = <1>;
462 #size-cells = <0>;
463 reg = <1>;
464 status = "disabled";
465
466 port@1 {
467 reg = <1>;
468
469 lvds1_in: endpoint {
470 remote-endpoint = <&ipu_di1_lvds1>;
471 };
472 };
473 };
474 };
475
476 pwm1: pwm@53fb4000 {
477 #pwm-cells = <2>;
478 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
479 reg = <0x53fb4000 0x4000>;
480 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
481 <&clks IMX5_CLK_PWM1_HF_GATE>;
482 clock-names = "ipg", "per";
483 interrupts = <61>;
484 };
485
486 pwm2: pwm@53fb8000 {
487 #pwm-cells = <2>;
488 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
489 reg = <0x53fb8000 0x4000>;
490 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
491 <&clks IMX5_CLK_PWM2_HF_GATE>;
492 clock-names = "ipg", "per";
493 interrupts = <94>;
494 };
495
496 uart1: serial@53fbc000 {
497 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
498 reg = <0x53fbc000 0x4000>;
499 interrupts = <31>;
500 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
501 <&clks IMX5_CLK_UART1_PER_GATE>;
502 clock-names = "ipg", "per";
503 dmas = <&sdma 18 4 0>, <&sdma 19 4 0>;
504 dma-names = "rx", "tx";
505 status = "disabled";
506 };
507
508 uart2: serial@53fc0000 {
509 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
510 reg = <0x53fc0000 0x4000>;
511 interrupts = <32>;
512 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
513 <&clks IMX5_CLK_UART2_PER_GATE>;
514 clock-names = "ipg", "per";
515 dmas = <&sdma 12 4 0>, <&sdma 13 4 0>;
516 dma-names = "rx", "tx";
517 status = "disabled";
518 };
519
520 can1: can@53fc8000 {
521 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
522 reg = <0x53fc8000 0x4000>;
523 interrupts = <82>;
524 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
525 <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
526 clock-names = "ipg", "per";
527 status = "disabled";
528 };
529
530 can2: can@53fcc000 {
531 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
532 reg = <0x53fcc000 0x4000>;
533 interrupts = <83>;
534 clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
535 <&clks IMX5_CLK_CAN2_SERIAL_GATE>;
536 clock-names = "ipg", "per";
537 status = "disabled";
538 };
539
540 src: src@53fd0000 {
541 compatible = "fsl,imx53-src", "fsl,imx51-src";
542 reg = <0x53fd0000 0x4000>;
543 #reset-cells = <1>;
544 };
545
546 clks: ccm@53fd4000{
547 compatible = "fsl,imx53-ccm";
548 reg = <0x53fd4000 0x4000>;
549 interrupts = <0 71 0x04 0 72 0x04>;
550 #clock-cells = <1>;
551 };
552
553 gpio5: gpio@53fdc000 {
554 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
555 reg = <0x53fdc000 0x4000>;
556 interrupts = <103 104>;
557 gpio-controller;
558 #gpio-cells = <2>;
559 interrupt-controller;
560 #interrupt-cells = <2>;
561 };
562
563 gpio6: gpio@53fe0000 {
564 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
565 reg = <0x53fe0000 0x4000>;
566 interrupts = <105 106>;
567 gpio-controller;
568 #gpio-cells = <2>;
569 interrupt-controller;
570 #interrupt-cells = <2>;
571 };
572
573 gpio7: gpio@53fe4000 {
574 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
575 reg = <0x53fe4000 0x4000>;
576 interrupts = <107 108>;
577 gpio-controller;
578 #gpio-cells = <2>;
579 interrupt-controller;
580 #interrupt-cells = <2>;
581 };
582
583 i2c3: i2c@53fec000 {
584 #address-cells = <1>;
585 #size-cells = <0>;
586 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
587 reg = <0x53fec000 0x4000>;
588 interrupts = <64>;
589 clocks = <&clks IMX5_CLK_I2C3_GATE>;
590 status = "disabled";
591 };
592
593 uart4: serial@53ff0000 {
594 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
595 reg = <0x53ff0000 0x4000>;
596 interrupts = <13>;
597 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
598 <&clks IMX5_CLK_UART4_PER_GATE>;
599 clock-names = "ipg", "per";
600 dmas = <&sdma 2 4 0>, <&sdma 3 4 0>;
601 dma-names = "rx", "tx";
602 status = "disabled";
603 };
604 };
605
606 aips@60000000 { /* AIPS2 */
607 compatible = "fsl,aips-bus", "simple-bus";
608 #address-cells = <1>;
609 #size-cells = <1>;
610 reg = <0x60000000 0x10000000>;
611 ranges;
612
613 aipstz2: bridge@63f00000 {
614 compatible = "fsl,imx53-aipstz";
615 reg = <0x63f00000 0x60>;
616 };
617
618 iim: iim@63f98000 {
619 compatible = "fsl,imx53-iim", "fsl,imx27-iim";
620 reg = <0x63f98000 0x4000>;
621 interrupts = <69>;
622 clocks = <&clks IMX5_CLK_IIM_GATE>;
623 };
624
625 uart5: serial@63f90000 {
626 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
627 reg = <0x63f90000 0x4000>;
628 interrupts = <86>;
629 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
630 <&clks IMX5_CLK_UART5_PER_GATE>;
631 clock-names = "ipg", "per";
632 dmas = <&sdma 16 4 0>, <&sdma 17 4 0>;
633 dma-names = "rx", "tx";
634 status = "disabled";
635 };
636
637 owire: owire@63fa4000 {
638 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
639 reg = <0x63fa4000 0x4000>;
640 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
641 status = "disabled";
642 };
643
644 ecspi2: ecspi@63fac000 {
645 #address-cells = <1>;
646 #size-cells = <0>;
647 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
648 reg = <0x63fac000 0x4000>;
649 interrupts = <37>;
650 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
651 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
652 clock-names = "ipg", "per";
653 status = "disabled";
654 };
655
656 sdma: sdma@63fb0000 {
657 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
658 reg = <0x63fb0000 0x4000>;
659 interrupts = <6>;
660 clocks = <&clks IMX5_CLK_SDMA_GATE>,
661 <&clks IMX5_CLK_SDMA_GATE>;
662 clock-names = "ipg", "ahb";
663 #dma-cells = <3>;
664 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
665 };
666
667 cspi: cspi@63fc0000 {
668 #address-cells = <1>;
669 #size-cells = <0>;
670 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
671 reg = <0x63fc0000 0x4000>;
672 interrupts = <38>;
673 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
674 <&clks IMX5_CLK_CSPI_IPG_GATE>;
675 clock-names = "ipg", "per";
676 status = "disabled";
677 };
678
679 i2c2: i2c@63fc4000 {
680 #address-cells = <1>;
681 #size-cells = <0>;
682 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
683 reg = <0x63fc4000 0x4000>;
684 interrupts = <63>;
685 clocks = <&clks IMX5_CLK_I2C2_GATE>;
686 status = "disabled";
687 };
688
689 i2c1: i2c@63fc8000 {
690 #address-cells = <1>;
691 #size-cells = <0>;
692 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
693 reg = <0x63fc8000 0x4000>;
694 interrupts = <62>;
695 clocks = <&clks IMX5_CLK_I2C1_GATE>;
696 status = "disabled";
697 };
698
699 ssi1: ssi@63fcc000 {
700 #sound-dai-cells = <0>;
701 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
702 "fsl,imx21-ssi";
703 reg = <0x63fcc000 0x4000>;
704 interrupts = <29>;
705 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
706 <&clks IMX5_CLK_SSI1_ROOT_GATE>;
707 clock-names = "ipg", "baud";
708 dmas = <&sdma 28 0 0>,
709 <&sdma 29 0 0>;
710 dma-names = "rx", "tx";
711 fsl,fifo-depth = <15>;
712 status = "disabled";
713 };
714
715 audmux: audmux@63fd0000 {
716 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
717 reg = <0x63fd0000 0x4000>;
718 status = "disabled";
719 };
720
721 nfc: nand@63fdb000 {
722 compatible = "fsl,imx53-nand";
723 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
724 interrupts = <8>;
725 clocks = <&clks IMX5_CLK_NFC_GATE>;
726 status = "disabled";
727 };
728
729 ssi3: ssi@63fe8000 {
730 #sound-dai-cells = <0>;
731 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
732 "fsl,imx21-ssi";
733 reg = <0x63fe8000 0x4000>;
734 interrupts = <96>;
735 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
736 <&clks IMX5_CLK_SSI3_ROOT_GATE>;
737 clock-names = "ipg", "baud";
738 dmas = <&sdma 46 0 0>,
739 <&sdma 47 0 0>;
740 dma-names = "rx", "tx";
741 fsl,fifo-depth = <15>;
742 status = "disabled";
743 };
744
745 fec: ethernet@63fec000 {
746 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
747 reg = <0x63fec000 0x4000>;
748 interrupts = <87>;
749 clocks = <&clks IMX5_CLK_FEC_GATE>,
750 <&clks IMX5_CLK_FEC_GATE>,
751 <&clks IMX5_CLK_FEC_GATE>;
752 clock-names = "ipg", "ahb", "ptp";
753 status = "disabled";
754 };
755
756 tve: tve@63ff0000 {
757 compatible = "fsl,imx53-tve";
758 reg = <0x63ff0000 0x1000>;
759 interrupts = <92>;
760 clocks = <&clks IMX5_CLK_TVE_GATE>,
761 <&clks IMX5_CLK_IPU_DI1_SEL>;
762 clock-names = "tve", "di_sel";
763 status = "disabled";
764
765 port {
766 tve_in: endpoint {
767 remote-endpoint = <&ipu_di1_tve>;
768 };
769 };
770 };
771
772 vpu: vpu@63ff4000 {
773 compatible = "fsl,imx53-vpu", "cnm,coda7541";
774 reg = <0x63ff4000 0x1000>;
775 interrupts = <9>;
776 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
777 <&clks IMX5_CLK_VPU_GATE>;
778 clock-names = "per", "ahb";
779 resets = <&src 1>;
780 iram = <&ocram>;
781 };
782
783 sahara: crypto@63ff8000 {
784 compatible = "fsl,imx53-sahara";
785 reg = <0x63ff8000 0x4000>;
786 interrupts = <19 20>;
787 clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
788 <&clks IMX5_CLK_SAHARA_IPG_GATE>;
789 clock-names = "ipg", "ahb";
790 };
791 };
792
793 ocram: sram@f8000000 {
794 compatible = "mmio-sram";
795 reg = <0xf8000000 0x20000>;
796 clocks = <&clks IMX5_CLK_OCRAM>;
797 };
798
799 pmu {
800 compatible = "arm,cortex-a8-pmu";
801 interrupts = <77>;
802 };
803 };
804 };
Linux kernel - Deliverables
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