arch/arm/boot/dts/imx6dl.dtsi

   1
   2 /*
   3  * Copyright 2013 Freescale Semiconductor, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  */
  10
  11 #include "imx6qdl.dtsi"
  12 #include "imx6dl-pinfunc.h"
  13
  14 / {
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu@0 {
  20                         compatible = "arm,cortex-a9";
  21                         device_type = "cpu";
  22                         reg = <0>;
  23                         next-level-cache = <&L2>;
  24                 };
  25
  26                 cpu@1 {
  27                         compatible = "arm,cortex-a9";
  28                         device_type = "cpu";
  29                         reg = <1>;
  30                         next-level-cache = <&L2>;
  31                 };
  32         };
  33
  34         soc {
  35                 aips1: aips-bus@02000000 {
  36                         iomuxc: iomuxc@020e0000 {
  37                                 compatible = "fsl,imx6dl-iomuxc";
  38                                 reg = <0x020e0000 0x4000>;
  39
  40                                 audmux {
  41                                         pinctrl_audmux_2: audmux-2 {
  42                                                 fsl,pins = <
  43                                                         MX6DL_PAD_CSI0_DAT7__AUD3_RXD  0x80000000
  44                                                         MX6DL_PAD_CSI0_DAT4__AUD3_TXC  0x80000000
  45                                                         MX6DL_PAD_CSI0_DAT5__AUD3_TXD  0x80000000
  46                                                         MX6DL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
  47                                                 >;
  48                                         };
  49                                 };
  50
  51                                 ecspi1 {
  52                                         pinctrl_ecspi1_1: ecspi1grp-1 {
  53                                                 fsl,pins = <
  54                                                         MX6DL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
  55                                                         MX6DL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
  56                                                         MX6DL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
  57                                                 >;
  58                                         };
  59                                 };
  60
  61                                 enet {
  62                                         pinctrl_enet_1: enetgrp-1 {
  63                                                 fsl,pins = <
  64                                                         MX6DL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
  65                                                         MX6DL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
  66                                                         MX6DL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
  67                                                         MX6DL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
  68                                                         MX6DL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
  69                                                         MX6DL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
  70                                                         MX6DL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
  71                                                         MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
  72                                                         MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
  73                                                         MX6DL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
  74                                                         MX6DL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
  75                                                         MX6DL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
  76                                                         MX6DL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
  77                                                         MX6DL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
  78                                                         MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
  79                                                         MX6DL_PAD_GPIO_16__ENET_REF_CLK      0x4001b0a8
  80                                                 >;
  81                                         };
  82
  83                                         pinctrl_enet_2: enetgrp-2 {
  84                                                 fsl,pins = <
  85                                                         MX6DL_PAD_KEY_COL1__ENET_MDIO        0x1b0b0
  86                                                         MX6DL_PAD_KEY_COL2__ENET_MDC         0x1b0b0
  87                                                         MX6DL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
  88                                                         MX6DL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
  89                                                         MX6DL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
  90                                                         MX6DL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
  91                                                         MX6DL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
  92                                                         MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
  93                                                         MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
  94                                                         MX6DL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
  95                                                         MX6DL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
  96                                                         MX6DL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
  97                                                         MX6DL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
  98                                                         MX6DL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
  99                                                         MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
 100                                                 >;
 101                                         };
 102                                 };
 103
 104                                 gpmi-nand {
 105                                         pinctrl_gpmi_nand_1: gpmi-nand-1 {
 106                                                 fsl,pins = <
 107                                                         MX6DL_PAD_NANDF_CLE__NAND_CLE     0xb0b1
 108                                                         MX6DL_PAD_NANDF_ALE__NAND_ALE     0xb0b1
 109                                                         MX6DL_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
 110                                                         MX6DL_PAD_NANDF_RB0__NAND_READY_B 0xb000
 111                                                         MX6DL_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
 112                                                         MX6DL_PAD_NANDF_CS1__NAND_CE1_B   0xb0b1
 113                                                         MX6DL_PAD_SD4_CMD__NAND_RE_B      0xb0b1
 114                                                         MX6DL_PAD_SD4_CLK__NAND_WE_B      0xb0b1
 115                                                         MX6DL_PAD_NANDF_D0__NAND_DATA00   0xb0b1
 116                                                         MX6DL_PAD_NANDF_D1__NAND_DATA01   0xb0b1
 117                                                         MX6DL_PAD_NANDF_D2__NAND_DATA02   0xb0b1
 118                                                         MX6DL_PAD_NANDF_D3__NAND_DATA03   0xb0b1
 119                                                         MX6DL_PAD_NANDF_D4__NAND_DATA04   0xb0b1
 120                                                         MX6DL_PAD_NANDF_D5__NAND_DATA05   0xb0b1
 121                                                         MX6DL_PAD_NANDF_D6__NAND_DATA06   0xb0b1
 122                                                         MX6DL_PAD_NANDF_D7__NAND_DATA07   0xb0b1
 123                                                         MX6DL_PAD_SD4_DAT0__NAND_DQS      0x00b1
 124                                                 >;
 125                                         };
 126                                 };
 127
 128                                 i2c1 {
 129                                         pinctrl_i2c1_2: i2c1grp-2 {
 130                                                 fsl,pins = <
 131                                                         MX6DL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
 132                                                         MX6DL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
 133                                                 >;
 134                                         };
 135                                 };
 136
 137                                 uart1 {
 138                                         pinctrl_uart1_1: uart1grp-1 {
 139                                                 fsl,pins = <
 140                                                         MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
 141                                                         MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
 142                                                 >;
 143                                         };
 144                                 };
 145
 146                                 uart4 {
 147                                         pinctrl_uart4_1: uart4grp-1 {
 148                                                 fsl,pins = <
 149                                                         MX6DL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
 150                                                         MX6DL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
 151                                                 >;
 152                                         };
 153                                 };
 154
 155                                 usbotg {
 156                                         pinctrl_usbotg_2: usbotggrp-2 {
 157                                                 fsl,pins = <
 158                                                         MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
 159                                                 >;
 160                                         };
 161                                 };
 162
 163                                 usdhc2 {
 164                                         pinctrl_usdhc2_1: usdhc2grp-1 {
 165                                                 fsl,pins = <
 166                                                         MX6DL_PAD_SD2_CMD__SD2_CMD    0x17059
 167                                                         MX6DL_PAD_SD2_CLK__SD2_CLK    0x10059
 168                                                         MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x17059
 169                                                         MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x17059
 170                                                         MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x17059
 171                                                         MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x17059
 172                                                         MX6DL_PAD_NANDF_D4__SD2_DATA4 0x17059
 173                                                         MX6DL_PAD_NANDF_D5__SD2_DATA5 0x17059
 174                                                         MX6DL_PAD_NANDF_D6__SD2_DATA6 0x17059
 175                                                         MX6DL_PAD_NANDF_D7__SD2_DATA7 0x17059
 176                                                 >;
 177                                         };
 178                                 };
 179
 180                                 usdhc3 {
 181                                         pinctrl_usdhc3_1: usdhc3grp-1 {
 182                                                 fsl,pins = <
 183                                                         MX6DL_PAD_SD3_CMD__SD3_CMD    0x17059
 184                                                         MX6DL_PAD_SD3_CLK__SD3_CLK    0x10059
 185                                                         MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
 186                                                         MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
 187                                                         MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
 188                                                         MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
 189                                                         MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x17059
 190                                                         MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x17059
 191                                                         MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x17059
 192                                                         MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x17059
 193                                                 >;
 194                                         };
 195
 196                                         pinctrl_usdhc3_2: usdhc3grp_2 {
 197                                                 fsl,pins = <
 198                                                         MX6DL_PAD_SD3_CMD__SD3_CMD    0x17059
 199                                                         MX6DL_PAD_SD3_CLK__SD3_CLK    0x10059
 200                                                         MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
 201                                                         MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
 202                                                         MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
 203                                                         MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
 204                                                 >;
 205                                         };
 206                                 };
 207
 208                                 weim {
 209                                         pinctrl_weim_cs0_1: weim_cs0grp-1 {
 210                                                 fsl,pins = <
 211                                                         MX6DL_PAD_EIM_CS0__EIM_CS0_B   0xb0b1
 212                                                 >;
 213                                         };
 214
 215                                         pinctrl_weim_nor_1: weim_norgrp-1 {
 216                                                 fsl,pins = <
 217                                                         MX6DL_PAD_EIM_OE__EIM_OE_B     0xb0b1
 218                                                         MX6DL_PAD_EIM_RW__EIM_RW       0xb0b1
 219                                                         MX6DL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
 220                                                         /* data */
 221                                                         MX6DL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
 222                                                         MX6DL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
 223                                                         MX6DL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
 224                                                         MX6DL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
 225                                                         MX6DL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
 226                                                         MX6DL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
 227                                                         MX6DL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
 228                                                         MX6DL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
 229                                                         MX6DL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
 230                                                         MX6DL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
 231                                                         MX6DL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
 232                                                         MX6DL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
 233                                                         MX6DL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
 234                                                         MX6DL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
 235                                                         MX6DL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
 236                                                         MX6DL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
 237                                                         /* address */
 238                                                         MX6DL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
 239                                                         MX6DL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
 240                                                         MX6DL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
 241                                                         MX6DL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
 242                                                         MX6DL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
 243                                                         MX6DL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
 244                                                         MX6DL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
 245                                                         MX6DL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
 246                                                         MX6DL_PAD_EIM_DA15__EIM_AD15  0xb0b1
 247                                                         MX6DL_PAD_EIM_DA14__EIM_AD14  0xb0b1
 248                                                         MX6DL_PAD_EIM_DA13__EIM_AD13  0xb0b1
 249                                                         MX6DL_PAD_EIM_DA12__EIM_AD12  0xb0b1
 250                                                         MX6DL_PAD_EIM_DA11__EIM_AD11  0xb0b1
 251                                                         MX6DL_PAD_EIM_DA10__EIM_AD10  0xb0b1
 252                                                         MX6DL_PAD_EIM_DA9__EIM_AD09   0xb0b1
 253                                                         MX6DL_PAD_EIM_DA8__EIM_AD08   0xb0b1
 254                                                         MX6DL_PAD_EIM_DA7__EIM_AD07   0xb0b1
 255                                                         MX6DL_PAD_EIM_DA6__EIM_AD06   0xb0b1
 256                                                         MX6DL_PAD_EIM_DA5__EIM_AD05   0xb0b1
 257                                                         MX6DL_PAD_EIM_DA4__EIM_AD04   0xb0b1
 258                                                         MX6DL_PAD_EIM_DA3__EIM_AD03   0xb0b1
 259                                                         MX6DL_PAD_EIM_DA2__EIM_AD02   0xb0b1
 260                                                         MX6DL_PAD_EIM_DA1__EIM_AD01   0xb0b1
 261                                                         MX6DL_PAD_EIM_DA0__EIM_AD00   0xb0b1
 262                                                 >;
 263                                         };
 264
 265                                 };
 266
 267                         };
 268
 269                         pxp: pxp@020f0000 {
 270                                 reg = <0x020f0000 0x4000>;
 271                                 interrupts = <0 98 0x04>;
 272                         };
 273
 274                         epdc: epdc@020f4000 {
 275                                 reg = <0x020f4000 0x4000>;
 276                                 interrupts = <0 97 0x04>;
 277                         };
 278
 279                         lcdif: lcdif@020f8000 {
 280                                 reg = <0x020f8000 0x4000>;
 281                                 interrupts = <0 39 0x04>;
 282                         };
 283                 };
 284
 285                 aips2: aips-bus@02100000 {
 286                         i2c4: i2c@021f8000 {
 287                                 #address-cells = <1>;
 288                                 #size-cells = <0>;
 289                                 compatible = "fsl,imx1-i2c";
 290                                 reg = <0x021f8000 0x4000>;
 291                                 interrupts = <0 35 0x04>;
 292                                 status = "disabled";
 293                         };
 294                 };
 295         };
 296 };