Merge branch 'master' into queue
[deliverable/linux.git] / arch / arm / boot / dts / imx6q-sabresd.dts
1 /*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13 /dts-v1/;
14 /include/ "imx6q.dtsi"
15
16 / {
17 model = "Freescale i.MX6Q SABRE Smart Device Board";
18 compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
19
20 memory {
21 reg = <0x10000000 0x40000000>;
22 };
23
24 gpio-keys {
25 compatible = "gpio-keys";
26
27 volume-up {
28 label = "Volume Up";
29 gpios = <&gpio1 4 0>;
30 linux,code = <115>; /* KEY_VOLUMEUP */
31 };
32
33 volume-down {
34 label = "Volume Down";
35 gpios = <&gpio1 5 0>;
36 linux,code = <114>; /* KEY_VOLUMEDOWN */
37 };
38 };
39 };
40
41 &uart1 {
42 pinctrl-names = "default";
43 pinctrl-0 = <&pinctrl_uart1_1>;
44 status = "okay";
45 };
46
47 &iomuxc {
48 pinctrl-names = "default";
49 pinctrl-0 = <&pinctrl_hog>;
50
51 hog {
52 pinctrl_hog: hoggrp {
53 fsl,pins = <
54 1004 0x80000000 /* MX6Q_PAD_GPIO_4__GPIO_1_4 */
55 1012 0x80000000 /* MX6Q_PAD_GPIO_5__GPIO_1_5 */
56 1402 0x80000000 /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */
57 1410 0x80000000 /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */
58 1418 0x80000000 /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */
59 1426 0x80000000 /* MX6Q_PAD_NANDF_D3__GPIO_2_3 */
60 >;
61 };
62 };
63 };
64
65 &fec {
66 pinctrl-names = "default";
67 pinctrl-0 = <&pinctrl_enet_1>;
68 phy-mode = "rgmii";
69 status = "okay";
70 };
71
72 &usdhc2 {
73 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_usdhc2_1>;
75 cd-gpios = <&gpio2 2 0>;
76 wp-gpios = <&gpio2 3 0>;
77 status = "okay";
78 };
79
80 &usdhc3 {
81 pinctrl-names = "default";
82 pinctrl-0 = <&pinctrl_usdhc3_1>;
83 cd-gpios = <&gpio2 0 0>;
84 wp-gpios = <&gpio2 1 0>;
85 status = "okay";
86 };
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