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ARM: meson: dts: add basic Meson/Meson6/Meson6-atv1200 DTSI/DTS
[deliverable/linux.git] / arch / arm / boot / dts / imx6sl.dtsi
1 /*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include "skeleton.dtsi"
12 #include "imx6sl-pinfunc.h"
13 #include <dt-bindings/clock/imx6sl-clock.h>
14
15 / {
16 aliases {
17 ethernet0 = &fec;
18 gpio0 = &gpio1;
19 gpio1 = &gpio2;
20 gpio2 = &gpio3;
21 gpio3 = &gpio4;
22 gpio4 = &gpio5;
23 serial0 = &uart1;
24 serial1 = &uart2;
25 serial2 = &uart3;
26 serial3 = &uart4;
27 serial4 = &uart5;
28 spi0 = &ecspi1;
29 spi1 = &ecspi2;
30 spi2 = &ecspi3;
31 spi3 = &ecspi4;
32 usbphy0 = &usbphy1;
33 usbphy1 = &usbphy2;
34 };
35
36 cpus {
37 #address-cells = <1>;
38 #size-cells = <0>;
39
40 cpu@0 {
41 compatible = "arm,cortex-a9";
42 device_type = "cpu";
43 reg = <0x0>;
44 next-level-cache = <&L2>;
45 operating-points = <
46 /* kHz uV */
47 996000 1275000
48 792000 1175000
49 396000 975000
50 >;
51 fsl,soc-operating-points = <
52 /* ARM kHz SOC-PU uV */
53 996000 1225000
54 792000 1175000
55 396000 1175000
56 >;
57 clock-latency = <61036>; /* two CLK32 periods */
58 clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
59 <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
60 <&clks IMX6SL_CLK_PLL1_SYS>;
61 clock-names = "arm", "pll2_pfd2_396m", "step",
62 "pll1_sw", "pll1_sys";
63 arm-supply = <&reg_arm>;
64 pu-supply = <&reg_pu>;
65 soc-supply = <&reg_soc>;
66 };
67 };
68
69 intc: interrupt-controller@00a01000 {
70 compatible = "arm,cortex-a9-gic";
71 #interrupt-cells = <3>;
72 interrupt-controller;
73 reg = <0x00a01000 0x1000>,
74 <0x00a00100 0x100>;
75 };
76
77 clocks {
78 #address-cells = <1>;
79 #size-cells = <0>;
80
81 ckil {
82 compatible = "fixed-clock";
83 #clock-cells = <0>;
84 clock-frequency = <32768>;
85 };
86
87 osc {
88 compatible = "fixed-clock";
89 #clock-cells = <0>;
90 clock-frequency = <24000000>;
91 };
92 };
93
94 soc {
95 #address-cells = <1>;
96 #size-cells = <1>;
97 compatible = "simple-bus";
98 interrupt-parent = <&intc>;
99 ranges;
100
101 ocram: sram@00900000 {
102 compatible = "mmio-sram";
103 reg = <0x00900000 0x20000>;
104 clocks = <&clks IMX6SL_CLK_OCRAM>;
105 };
106
107 L2: l2-cache@00a02000 {
108 compatible = "arm,pl310-cache";
109 reg = <0x00a02000 0x1000>;
110 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
111 cache-unified;
112 cache-level = <2>;
113 arm,tag-latency = <4 2 3>;
114 arm,data-latency = <4 2 3>;
115 };
116
117 pmu {
118 compatible = "arm,cortex-a9-pmu";
119 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
120 };
121
122 aips1: aips-bus@02000000 {
123 compatible = "fsl,aips-bus", "simple-bus";
124 #address-cells = <1>;
125 #size-cells = <1>;
126 reg = <0x02000000 0x100000>;
127 ranges;
128
129 spba: spba-bus@02000000 {
130 compatible = "fsl,spba-bus", "simple-bus";
131 #address-cells = <1>;
132 #size-cells = <1>;
133 reg = <0x02000000 0x40000>;
134 ranges;
135
136 spdif: spdif@02004000 {
137 reg = <0x02004000 0x4000>;
138 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
139 };
140
141 ecspi1: ecspi@02008000 {
142 #address-cells = <1>;
143 #size-cells = <0>;
144 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
145 reg = <0x02008000 0x4000>;
146 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
147 clocks = <&clks IMX6SL_CLK_ECSPI1>,
148 <&clks IMX6SL_CLK_ECSPI1>;
149 clock-names = "ipg", "per";
150 status = "disabled";
151 };
152
153 ecspi2: ecspi@0200c000 {
154 #address-cells = <1>;
155 #size-cells = <0>;
156 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
157 reg = <0x0200c000 0x4000>;
158 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
159 clocks = <&clks IMX6SL_CLK_ECSPI2>,
160 <&clks IMX6SL_CLK_ECSPI2>;
161 clock-names = "ipg", "per";
162 status = "disabled";
163 };
164
165 ecspi3: ecspi@02010000 {
166 #address-cells = <1>;
167 #size-cells = <0>;
168 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
169 reg = <0x02010000 0x4000>;
170 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
171 clocks = <&clks IMX6SL_CLK_ECSPI3>,
172 <&clks IMX6SL_CLK_ECSPI3>;
173 clock-names = "ipg", "per";
174 status = "disabled";
175 };
176
177 ecspi4: ecspi@02014000 {
178 #address-cells = <1>;
179 #size-cells = <0>;
180 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
181 reg = <0x02014000 0x4000>;
182 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
183 clocks = <&clks IMX6SL_CLK_ECSPI4>,
184 <&clks IMX6SL_CLK_ECSPI4>;
185 clock-names = "ipg", "per";
186 status = "disabled";
187 };
188
189 uart5: serial@02018000 {
190 compatible = "fsl,imx6sl-uart",
191 "fsl,imx6q-uart", "fsl,imx21-uart";
192 reg = <0x02018000 0x4000>;
193 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&clks IMX6SL_CLK_UART>,
195 <&clks IMX6SL_CLK_UART_SERIAL>;
196 clock-names = "ipg", "per";
197 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
198 dma-names = "rx", "tx";
199 status = "disabled";
200 };
201
202 uart1: serial@02020000 {
203 compatible = "fsl,imx6sl-uart",
204 "fsl,imx6q-uart", "fsl,imx21-uart";
205 reg = <0x02020000 0x4000>;
206 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
207 clocks = <&clks IMX6SL_CLK_UART>,
208 <&clks IMX6SL_CLK_UART_SERIAL>;
209 clock-names = "ipg", "per";
210 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
211 dma-names = "rx", "tx";
212 status = "disabled";
213 };
214
215 uart2: serial@02024000 {
216 compatible = "fsl,imx6sl-uart",
217 "fsl,imx6q-uart", "fsl,imx21-uart";
218 reg = <0x02024000 0x4000>;
219 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
220 clocks = <&clks IMX6SL_CLK_UART>,
221 <&clks IMX6SL_CLK_UART_SERIAL>;
222 clock-names = "ipg", "per";
223 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
224 dma-names = "rx", "tx";
225 status = "disabled";
226 };
227
228 ssi1: ssi@02028000 {
229 #sound-dai-cells = <0>;
230 compatible = "fsl,imx6sl-ssi",
231 "fsl,imx51-ssi";
232 reg = <0x02028000 0x4000>;
233 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&clks IMX6SL_CLK_SSI1_IPG>,
235 <&clks IMX6SL_CLK_SSI1>;
236 clock-names = "ipg", "baud";
237 dmas = <&sdma 37 1 0>,
238 <&sdma 38 1 0>;
239 dma-names = "rx", "tx";
240 fsl,fifo-depth = <15>;
241 status = "disabled";
242 };
243
244 ssi2: ssi@0202c000 {
245 #sound-dai-cells = <0>;
246 compatible = "fsl,imx6sl-ssi",
247 "fsl,imx51-ssi";
248 reg = <0x0202c000 0x4000>;
249 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
250 clocks = <&clks IMX6SL_CLK_SSI2_IPG>,
251 <&clks IMX6SL_CLK_SSI2>;
252 clock-names = "ipg", "baud";
253 dmas = <&sdma 41 1 0>,
254 <&sdma 42 1 0>;
255 dma-names = "rx", "tx";
256 fsl,fifo-depth = <15>;
257 status = "disabled";
258 };
259
260 ssi3: ssi@02030000 {
261 #sound-dai-cells = <0>;
262 compatible = "fsl,imx6sl-ssi",
263 "fsl,imx51-ssi";
264 reg = <0x02030000 0x4000>;
265 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
266 clocks = <&clks IMX6SL_CLK_SSI3_IPG>,
267 <&clks IMX6SL_CLK_SSI3>;
268 clock-names = "ipg", "baud";
269 dmas = <&sdma 45 1 0>,
270 <&sdma 46 1 0>;
271 dma-names = "rx", "tx";
272 fsl,fifo-depth = <15>;
273 status = "disabled";
274 };
275
276 uart3: serial@02034000 {
277 compatible = "fsl,imx6sl-uart",
278 "fsl,imx6q-uart", "fsl,imx21-uart";
279 reg = <0x02034000 0x4000>;
280 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
281 clocks = <&clks IMX6SL_CLK_UART>,
282 <&clks IMX6SL_CLK_UART_SERIAL>;
283 clock-names = "ipg", "per";
284 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
285 dma-names = "rx", "tx";
286 status = "disabled";
287 };
288
289 uart4: serial@02038000 {
290 compatible = "fsl,imx6sl-uart",
291 "fsl,imx6q-uart", "fsl,imx21-uart";
292 reg = <0x02038000 0x4000>;
293 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
294 clocks = <&clks IMX6SL_CLK_UART>,
295 <&clks IMX6SL_CLK_UART_SERIAL>;
296 clock-names = "ipg", "per";
297 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
298 dma-names = "rx", "tx";
299 status = "disabled";
300 };
301 };
302
303 pwm1: pwm@02080000 {
304 #pwm-cells = <2>;
305 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
306 reg = <0x02080000 0x4000>;
307 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
308 clocks = <&clks IMX6SL_CLK_PWM1>,
309 <&clks IMX6SL_CLK_PWM1>;
310 clock-names = "ipg", "per";
311 };
312
313 pwm2: pwm@02084000 {
314 #pwm-cells = <2>;
315 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
316 reg = <0x02084000 0x4000>;
317 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&clks IMX6SL_CLK_PWM2>,
319 <&clks IMX6SL_CLK_PWM2>;
320 clock-names = "ipg", "per";
321 };
322
323 pwm3: pwm@02088000 {
324 #pwm-cells = <2>;
325 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
326 reg = <0x02088000 0x4000>;
327 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
328 clocks = <&clks IMX6SL_CLK_PWM3>,
329 <&clks IMX6SL_CLK_PWM3>;
330 clock-names = "ipg", "per";
331 };
332
333 pwm4: pwm@0208c000 {
334 #pwm-cells = <2>;
335 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
336 reg = <0x0208c000 0x4000>;
337 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
338 clocks = <&clks IMX6SL_CLK_PWM4>,
339 <&clks IMX6SL_CLK_PWM4>;
340 clock-names = "ipg", "per";
341 };
342
343 gpt: gpt@02098000 {
344 compatible = "fsl,imx6sl-gpt";
345 reg = <0x02098000 0x4000>;
346 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
347 clocks = <&clks IMX6SL_CLK_GPT>,
348 <&clks IMX6SL_CLK_GPT_SERIAL>;
349 clock-names = "ipg", "per";
350 };
351
352 gpio1: gpio@0209c000 {
353 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
354 reg = <0x0209c000 0x4000>;
355 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
356 <0 67 IRQ_TYPE_LEVEL_HIGH>;
357 gpio-controller;
358 #gpio-cells = <2>;
359 interrupt-controller;
360 #interrupt-cells = <2>;
361 };
362
363 gpio2: gpio@020a0000 {
364 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
365 reg = <0x020a0000 0x4000>;
366 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
367 <0 69 IRQ_TYPE_LEVEL_HIGH>;
368 gpio-controller;
369 #gpio-cells = <2>;
370 interrupt-controller;
371 #interrupt-cells = <2>;
372 };
373
374 gpio3: gpio@020a4000 {
375 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
376 reg = <0x020a4000 0x4000>;
377 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
378 <0 71 IRQ_TYPE_LEVEL_HIGH>;
379 gpio-controller;
380 #gpio-cells = <2>;
381 interrupt-controller;
382 #interrupt-cells = <2>;
383 };
384
385 gpio4: gpio@020a8000 {
386 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
387 reg = <0x020a8000 0x4000>;
388 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
389 <0 73 IRQ_TYPE_LEVEL_HIGH>;
390 gpio-controller;
391 #gpio-cells = <2>;
392 interrupt-controller;
393 #interrupt-cells = <2>;
394 };
395
396 gpio5: gpio@020ac000 {
397 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
398 reg = <0x020ac000 0x4000>;
399 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
400 <0 75 IRQ_TYPE_LEVEL_HIGH>;
401 gpio-controller;
402 #gpio-cells = <2>;
403 interrupt-controller;
404 #interrupt-cells = <2>;
405 };
406
407 kpp: kpp@020b8000 {
408 compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
409 reg = <0x020b8000 0x4000>;
410 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
411 clocks = <&clks IMX6SL_CLK_DUMMY>;
412 status = "disabled";
413 };
414
415 wdog1: wdog@020bc000 {
416 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
417 reg = <0x020bc000 0x4000>;
418 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
419 clocks = <&clks IMX6SL_CLK_DUMMY>;
420 };
421
422 wdog2: wdog@020c0000 {
423 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
424 reg = <0x020c0000 0x4000>;
425 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
426 clocks = <&clks IMX6SL_CLK_DUMMY>;
427 status = "disabled";
428 };
429
430 clks: ccm@020c4000 {
431 compatible = "fsl,imx6sl-ccm";
432 reg = <0x020c4000 0x4000>;
433 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
434 <0 88 IRQ_TYPE_LEVEL_HIGH>;
435 #clock-cells = <1>;
436 };
437
438 anatop: anatop@020c8000 {
439 compatible = "fsl,imx6sl-anatop",
440 "fsl,imx6q-anatop",
441 "syscon", "simple-bus";
442 reg = <0x020c8000 0x1000>;
443 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
444 <0 54 IRQ_TYPE_LEVEL_HIGH>,
445 <0 127 IRQ_TYPE_LEVEL_HIGH>;
446
447 regulator-1p1@110 {
448 compatible = "fsl,anatop-regulator";
449 regulator-name = "vdd1p1";
450 regulator-min-microvolt = <800000>;
451 regulator-max-microvolt = <1375000>;
452 regulator-always-on;
453 anatop-reg-offset = <0x110>;
454 anatop-vol-bit-shift = <8>;
455 anatop-vol-bit-width = <5>;
456 anatop-min-bit-val = <4>;
457 anatop-min-voltage = <800000>;
458 anatop-max-voltage = <1375000>;
459 };
460
461 regulator-3p0@120 {
462 compatible = "fsl,anatop-regulator";
463 regulator-name = "vdd3p0";
464 regulator-min-microvolt = <2800000>;
465 regulator-max-microvolt = <3150000>;
466 regulator-always-on;
467 anatop-reg-offset = <0x120>;
468 anatop-vol-bit-shift = <8>;
469 anatop-vol-bit-width = <5>;
470 anatop-min-bit-val = <0>;
471 anatop-min-voltage = <2625000>;
472 anatop-max-voltage = <3400000>;
473 };
474
475 regulator-2p5@130 {
476 compatible = "fsl,anatop-regulator";
477 regulator-name = "vdd2p5";
478 regulator-min-microvolt = <2100000>;
479 regulator-max-microvolt = <2850000>;
480 regulator-always-on;
481 anatop-reg-offset = <0x130>;
482 anatop-vol-bit-shift = <8>;
483 anatop-vol-bit-width = <5>;
484 anatop-min-bit-val = <0>;
485 anatop-min-voltage = <2100000>;
486 anatop-max-voltage = <2850000>;
487 };
488
489 reg_arm: regulator-vddcore@140 {
490 compatible = "fsl,anatop-regulator";
491 regulator-name = "vddarm";
492 regulator-min-microvolt = <725000>;
493 regulator-max-microvolt = <1450000>;
494 regulator-always-on;
495 anatop-reg-offset = <0x140>;
496 anatop-vol-bit-shift = <0>;
497 anatop-vol-bit-width = <5>;
498 anatop-delay-reg-offset = <0x170>;
499 anatop-delay-bit-shift = <24>;
500 anatop-delay-bit-width = <2>;
501 anatop-min-bit-val = <1>;
502 anatop-min-voltage = <725000>;
503 anatop-max-voltage = <1450000>;
504 };
505
506 reg_pu: regulator-vddpu@140 {
507 compatible = "fsl,anatop-regulator";
508 regulator-name = "vddpu";
509 regulator-min-microvolt = <725000>;
510 regulator-max-microvolt = <1450000>;
511 regulator-always-on;
512 anatop-reg-offset = <0x140>;
513 anatop-vol-bit-shift = <9>;
514 anatop-vol-bit-width = <5>;
515 anatop-delay-reg-offset = <0x170>;
516 anatop-delay-bit-shift = <26>;
517 anatop-delay-bit-width = <2>;
518 anatop-min-bit-val = <1>;
519 anatop-min-voltage = <725000>;
520 anatop-max-voltage = <1450000>;
521 };
522
523 reg_soc: regulator-vddsoc@140 {
524 compatible = "fsl,anatop-regulator";
525 regulator-name = "vddsoc";
526 regulator-min-microvolt = <725000>;
527 regulator-max-microvolt = <1450000>;
528 regulator-always-on;
529 anatop-reg-offset = <0x140>;
530 anatop-vol-bit-shift = <18>;
531 anatop-vol-bit-width = <5>;
532 anatop-delay-reg-offset = <0x170>;
533 anatop-delay-bit-shift = <28>;
534 anatop-delay-bit-width = <2>;
535 anatop-min-bit-val = <1>;
536 anatop-min-voltage = <725000>;
537 anatop-max-voltage = <1450000>;
538 };
539 };
540
541 tempmon: tempmon {
542 compatible = "fsl,imx6q-tempmon";
543 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
544 fsl,tempmon = <&anatop>;
545 fsl,tempmon-data = <&ocotp>;
546 clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
547 };
548
549 usbphy1: usbphy@020c9000 {
550 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
551 reg = <0x020c9000 0x1000>;
552 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
553 clocks = <&clks IMX6SL_CLK_USBPHY1>;
554 fsl,anatop = <&anatop>;
555 };
556
557 usbphy2: usbphy@020ca000 {
558 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
559 reg = <0x020ca000 0x1000>;
560 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
561 clocks = <&clks IMX6SL_CLK_USBPHY2>;
562 fsl,anatop = <&anatop>;
563 };
564
565 snvs@020cc000 {
566 compatible = "fsl,sec-v4.0-mon", "simple-bus";
567 #address-cells = <1>;
568 #size-cells = <1>;
569 ranges = <0 0x020cc000 0x4000>;
570
571 snvs-rtc-lp@34 {
572 compatible = "fsl,sec-v4.0-mon-rtc-lp";
573 reg = <0x34 0x58>;
574 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
575 <0 20 IRQ_TYPE_LEVEL_HIGH>;
576 };
577 };
578
579 epit1: epit@020d0000 {
580 reg = <0x020d0000 0x4000>;
581 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
582 };
583
584 epit2: epit@020d4000 {
585 reg = <0x020d4000 0x4000>;
586 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
587 };
588
589 src: src@020d8000 {
590 compatible = "fsl,imx6sl-src", "fsl,imx51-src";
591 reg = <0x020d8000 0x4000>;
592 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
593 <0 96 IRQ_TYPE_LEVEL_HIGH>;
594 #reset-cells = <1>;
595 };
596
597 gpc: gpc@020dc000 {
598 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
599 reg = <0x020dc000 0x4000>;
600 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
601 };
602
603 gpr: iomuxc-gpr@020e0000 {
604 compatible = "fsl,imx6sl-iomuxc-gpr",
605 "fsl,imx6q-iomuxc-gpr", "syscon";
606 reg = <0x020e0000 0x38>;
607 };
608
609 iomuxc: iomuxc@020e0000 {
610 compatible = "fsl,imx6sl-iomuxc";
611 reg = <0x020e0000 0x4000>;
612 };
613
614 csi: csi@020e4000 {
615 reg = <0x020e4000 0x4000>;
616 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
617 };
618
619 spdc: spdc@020e8000 {
620 reg = <0x020e8000 0x4000>;
621 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
622 };
623
624 sdma: sdma@020ec000 {
625 compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma";
626 reg = <0x020ec000 0x4000>;
627 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
628 clocks = <&clks IMX6SL_CLK_SDMA>,
629 <&clks IMX6SL_CLK_SDMA>;
630 clock-names = "ipg", "ahb";
631 #dma-cells = <3>;
632 /* imx6sl reuses imx6q sdma firmware */
633 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
634 };
635
636 pxp: pxp@020f0000 {
637 reg = <0x020f0000 0x4000>;
638 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
639 };
640
641 epdc: epdc@020f4000 {
642 reg = <0x020f4000 0x4000>;
643 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
644 };
645
646 lcdif: lcdif@020f8000 {
647 compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif";
648 reg = <0x020f8000 0x4000>;
649 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
650 clocks = <&clks IMX6SL_CLK_LCDIF_PIX>,
651 <&clks IMX6SL_CLK_LCDIF_AXI>,
652 <&clks IMX6SL_CLK_DUMMY>;
653 clock-names = "pix", "axi", "disp_axi";
654 status = "disabled";
655 };
656
657 dcp: dcp@020fc000 {
658 reg = <0x020fc000 0x4000>;
659 interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
660 };
661 };
662
663 aips2: aips-bus@02100000 {
664 compatible = "fsl,aips-bus", "simple-bus";
665 #address-cells = <1>;
666 #size-cells = <1>;
667 reg = <0x02100000 0x100000>;
668 ranges;
669
670 usbotg1: usb@02184000 {
671 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
672 reg = <0x02184000 0x200>;
673 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
674 clocks = <&clks IMX6SL_CLK_USBOH3>;
675 fsl,usbphy = <&usbphy1>;
676 fsl,usbmisc = <&usbmisc 0>;
677 status = "disabled";
678 };
679
680 usbotg2: usb@02184200 {
681 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
682 reg = <0x02184200 0x200>;
683 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
684 clocks = <&clks IMX6SL_CLK_USBOH3>;
685 fsl,usbphy = <&usbphy2>;
686 fsl,usbmisc = <&usbmisc 1>;
687 status = "disabled";
688 };
689
690 usbh: usb@02184400 {
691 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
692 reg = <0x02184400 0x200>;
693 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
694 clocks = <&clks IMX6SL_CLK_USBOH3>;
695 fsl,usbmisc = <&usbmisc 2>;
696 status = "disabled";
697 };
698
699 usbmisc: usbmisc@02184800 {
700 #index-cells = <1>;
701 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
702 reg = <0x02184800 0x200>;
703 clocks = <&clks IMX6SL_CLK_USBOH3>;
704 };
705
706 fec: ethernet@02188000 {
707 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
708 reg = <0x02188000 0x4000>;
709 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
710 clocks = <&clks IMX6SL_CLK_ENET>,
711 <&clks IMX6SL_CLK_ENET_REF>;
712 clock-names = "ipg", "ahb";
713 status = "disabled";
714 };
715
716 usdhc1: usdhc@02190000 {
717 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
718 reg = <0x02190000 0x4000>;
719 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
720 clocks = <&clks IMX6SL_CLK_USDHC1>,
721 <&clks IMX6SL_CLK_USDHC1>,
722 <&clks IMX6SL_CLK_USDHC1>;
723 clock-names = "ipg", "ahb", "per";
724 bus-width = <4>;
725 status = "disabled";
726 };
727
728 usdhc2: usdhc@02194000 {
729 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
730 reg = <0x02194000 0x4000>;
731 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
732 clocks = <&clks IMX6SL_CLK_USDHC2>,
733 <&clks IMX6SL_CLK_USDHC2>,
734 <&clks IMX6SL_CLK_USDHC2>;
735 clock-names = "ipg", "ahb", "per";
736 bus-width = <4>;
737 status = "disabled";
738 };
739
740 usdhc3: usdhc@02198000 {
741 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
742 reg = <0x02198000 0x4000>;
743 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
744 clocks = <&clks IMX6SL_CLK_USDHC3>,
745 <&clks IMX6SL_CLK_USDHC3>,
746 <&clks IMX6SL_CLK_USDHC3>;
747 clock-names = "ipg", "ahb", "per";
748 bus-width = <4>;
749 status = "disabled";
750 };
751
752 usdhc4: usdhc@0219c000 {
753 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
754 reg = <0x0219c000 0x4000>;
755 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
756 clocks = <&clks IMX6SL_CLK_USDHC4>,
757 <&clks IMX6SL_CLK_USDHC4>,
758 <&clks IMX6SL_CLK_USDHC4>;
759 clock-names = "ipg", "ahb", "per";
760 bus-width = <4>;
761 status = "disabled";
762 };
763
764 i2c1: i2c@021a0000 {
765 #address-cells = <1>;
766 #size-cells = <0>;
767 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
768 reg = <0x021a0000 0x4000>;
769 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
770 clocks = <&clks IMX6SL_CLK_I2C1>;
771 status = "disabled";
772 };
773
774 i2c2: i2c@021a4000 {
775 #address-cells = <1>;
776 #size-cells = <0>;
777 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
778 reg = <0x021a4000 0x4000>;
779 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
780 clocks = <&clks IMX6SL_CLK_I2C2>;
781 status = "disabled";
782 };
783
784 i2c3: i2c@021a8000 {
785 #address-cells = <1>;
786 #size-cells = <0>;
787 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
788 reg = <0x021a8000 0x4000>;
789 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
790 clocks = <&clks IMX6SL_CLK_I2C3>;
791 status = "disabled";
792 };
793
794 mmdc: mmdc@021b0000 {
795 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
796 reg = <0x021b0000 0x4000>;
797 };
798
799 rngb: rngb@021b4000 {
800 reg = <0x021b4000 0x4000>;
801 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
802 };
803
804 weim: weim@021b8000 {
805 reg = <0x021b8000 0x4000>;
806 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
807 };
808
809 ocotp: ocotp@021bc000 {
810 compatible = "fsl,imx6sl-ocotp", "syscon";
811 reg = <0x021bc000 0x4000>;
812 };
813
814 audmux: audmux@021d8000 {
815 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
816 reg = <0x021d8000 0x4000>;
817 status = "disabled";
818 };
819 };
820 };
821 };
Linux kernel - Deliverables
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