4 pinctrl: pinctrl@10000 {
5 compatible = "marvell,88f6282-pinctrl";
9 marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
10 "mpp4", "mpp5", "mpp18", "mpp19";
11 marvell,function = "nand";
14 pmx_sata0: pmx-sata0 {
15 marvell,pins = "mpp5", "mpp21", "mpp23";
16 marvell,function = "sata0";
18 pmx_sata1: pmx-sata1 {
19 marvell,pins = "mpp4", "mpp20", "mpp22";
20 marvell,function = "sata1";
23 marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3";
24 marvell,function = "spi";
26 pmx_twsi0: pmx-twsi0 {
27 marvell,pins = "mpp8", "mpp9";
28 marvell,function = "twsi0";
31 pmx_twsi1: pmx-twsi1 {
32 marvell,pins = "mpp36", "mpp37";
33 marvell,function = "twsi1";
36 pmx_uart0: pmx-uart0 {
37 marvell,pins = "mpp10", "mpp11";
38 marvell,function = "uart0";
41 pmx_uart1: pmx-uart1 {
42 marvell,pins = "mpp13", "mpp14";
43 marvell,function = "uart1";
46 marvell,pins = "mpp12", "mpp13", "mpp14",
47 "mpp15", "mpp16", "mpp17";
48 marvell,function = "sdio";
53 compatible = "marvell,kirkwood-thermal";
59 compatible = "marvell,mv64xxx-i2c";
64 clock-frequency = <100000>;
65 clocks = <&gate_clk 7>;
70 compatible = "marvell,kirkwood-pcie";
77 bus-range = <0x00 0xff>;
79 ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000 /* Port 0.0 registers */
80 0x82000000 0 0x00044000 0x00044000 0 0x00002000 /* Port 1.0 registers */
81 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
82 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
86 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
87 reg = <0x0800 0 0 0 0>;
90 #interrupt-cells = <1>;
92 interrupt-map-mask = <0 0 0 0>;
93 interrupt-map = <0 0 0 0 &intc 9>;
94 marvell,pcie-port = <0>;
95 marvell,pcie-lane = <0>;
96 clocks = <&gate_clk 2>;
102 assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>;
103 reg = <0x1000 0 0 0 0>;
104 #address-cells = <3>;
106 #interrupt-cells = <1>;
108 interrupt-map-mask = <0 0 0 0>;
109 interrupt-map = <0 0 0 0 &intc 10>;
110 marvell,pcie-port = <1>;
111 marvell,pcie-lane = <0>;
112 clocks = <&gate_clk 18>;