2 * Common base for NXP LPC18xx and LPC43xx devices.
4 * Copyright 2015 Joachim Eastwood <manabian@gmail.com>
6 * This code is released using a dual license strategy: BSD/GPL
7 * You can choose the licence that better fits your requirements.
9 * Released under the terms of 3-clause BSD License
10 * Released under the terms of GNU General Public License Version 2.0
14 #include "armv7-m.dtsi"
16 #include "dt-bindings/clock/lpc18xx-cgu.h"
17 #include "dt-bindings/clock/lpc18xx-ccu.h"
19 #define LPC_PIN(port, pin) (0x##port * 32 + pin)
20 #define LPC_GPIO(port, pin) (port * 32 + pin)
28 compatible = "arm,cortex-m3";
31 clocks = <&ccu1 CLK_CPU_CORE>;
37 compatible = "fixed-clock";
39 clock-frequency = <12000000>;
43 compatible = "fixed-clock";
45 clock-frequency = <32768>;
48 enet_rx_clk: enet_rx_clk {
49 compatible = "fixed-clock";
51 clock-frequency = <0>;
52 clock-output-names = "enet_rx_clk";
55 enet_tx_clk: enet_tx_clk {
56 compatible = "fixed-clock";
58 clock-frequency = <0>;
59 clock-output-names = "enet_tx_clk";
63 compatible = "fixed-clock";
65 clock-frequency = <0>;
66 clock-output-names = "gp_clkin";
71 mmcsd: mmcsd@40004000 {
72 compatible = "snps,dw-mshc";
73 reg = <0x40004000 0x1000>;
76 clocks = <&ccu2 CLK_SDIO>, <&ccu1 CLK_CPU_SDIO>;
77 clock-names = "ciu", "biu";
82 compatible = "nxp,lpc1850-ehci", "generic-ehci";
83 reg = <0x40006100 0x100>;
85 clocks = <&ccu1 CLK_CPU_USB0>;
86 phys = <&usb0_otg_phy>;
88 has-transaction-translator;
93 compatible = "nxp,lpc1850-ehci", "generic-ehci";
94 reg = <0x40007100 0x100>;
96 clocks = <&ccu1 CLK_CPU_USB1>;
100 mac: ethernet@40010000 {
101 compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac";
102 reg = <0x40010000 0x2000>;
104 interrupt-names = "macirq";
105 clocks = <&ccu1 CLK_CPU_ETHERNET>;
106 clock-names = "stmmaceth";
110 creg: syscon@40043000 {
111 compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd";
112 reg = <0x40043000 0x1000>;
113 clocks = <&ccu1 CLK_CPU_CREG>;
115 usb0_otg_phy: phy@004 {
116 compatible = "nxp,lpc1850-usb-otg-phy";
117 clocks = <&ccu1 CLK_USB0>;
122 cgu: clock-controller@40050000 {
123 compatible = "nxp,lpc1850-cgu";
124 reg = <0x40050000 0x1000>;
126 clocks = <&xtal>, <&xtal32>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>;
129 ccu1: clock-controller@40051000 {
130 compatible = "nxp,lpc1850-ccu";
131 reg = <0x40051000 0x1000>;
133 clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>,
134 <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>,
135 <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
136 <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>;
137 clock-names = "base_apb3_clk", "base_apb1_clk",
138 "base_spifi_clk", "base_cpu_clk",
139 "base_periph_clk", "base_usb0_clk",
140 "base_usb1_clk", "base_spi_clk";
143 ccu2: clock-controller@40052000 {
144 compatible = "nxp,lpc1850-ccu";
145 reg = <0x40052000 0x1000>;
147 clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
148 <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
149 <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>,
150 <&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>;
151 clock-names = "base_audio_clk", "base_uart3_clk",
152 "base_uart2_clk", "base_uart1_clk",
153 "base_uart0_clk", "base_ssp1_clk",
154 "base_ssp0_clk", "base_sdio_clk";
157 uart0: serial@40081000 {
158 compatible = "nxp,lpc1850-uart", "ns16550a";
159 reg = <0x40081000 0x1000>;
162 clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>;
163 clock-names = "uartclk", "reg";
167 uart1: serial@40082000 {
168 compatible = "nxp,lpc1850-uart", "ns16550a";
169 reg = <0x40082000 0x1000>;
172 clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>;
173 clock-names = "uartclk", "reg";
178 compatible = "arm,pl022", "arm,primecell";
179 reg = <0x40083000 0x1000>;
181 clocks = <&ccu2 CLK_APB0_SSP0>, <&ccu1 CLK_CPU_SSP0>;
182 clock-names = "sspclk", "apb_pclk";
183 #address-cells = <1>;
188 timer0: timer@40084000 {
189 compatible = "nxp,lpc3220-timer";
190 reg = <0x40084000 0x1000>;
192 clocks = <&ccu1 CLK_CPU_TIMER0>;
193 clock-names = "timerclk";
196 timer1: timer@40085000 {
197 compatible = "nxp,lpc3220-timer";
198 reg = <0x40085000 0x1000>;
200 clocks = <&ccu1 CLK_CPU_TIMER1>;
201 clock-names = "timerclk";
204 pinctrl: pinctrl@40086000 {
205 compatible = "nxp,lpc1850-scu";
206 reg = <0x40086000 0x1000>;
207 clocks = <&ccu1 CLK_CPU_SCU>;
211 compatible = "bosch,c_can";
212 reg = <0x400a4000 0x1000>;
214 clocks = <&ccu1 CLK_APB1_CAN1>;
218 uart2: serial@400c1000 {
219 compatible = "nxp,lpc1850-uart", "ns16550a";
220 reg = <0x400c1000 0x1000>;
223 clocks = <&ccu2 CLK_APB2_UART2>, <&ccu1 CLK_CPU_UART2>;
224 clock-names = "uartclk", "reg";
228 uart3: serial@400c2000 {
229 compatible = "nxp,lpc1850-uart", "ns16550a";
230 reg = <0x400c2000 0x1000>;
233 clocks = <&ccu2 CLK_APB2_UART3>, <&ccu1 CLK_CPU_UART3>;
234 clock-names = "uartclk", "reg";
238 timer2: timer@400c3000 {
239 compatible = "nxp,lpc3220-timer";
240 reg = <0x400c3000 0x1000>;
242 clocks = <&ccu1 CLK_CPU_TIMER2>;
243 clock-names = "timerclk";
246 timer3: timer@400c4000 {
247 compatible = "nxp,lpc3220-timer";
248 reg = <0x400c4000 0x1000>;
250 clocks = <&ccu1 CLK_CPU_TIMER3>;
251 clock-names = "timerclk";
255 compatible = "arm,pl022", "arm,primecell";
256 reg = <0x400c5000 0x1000>;
258 clocks = <&ccu2 CLK_APB2_SSP1>, <&ccu1 CLK_CPU_SSP1>;
259 clock-names = "sspclk", "apb_pclk";
260 #address-cells = <1>;
266 compatible = "bosch,c_can";
267 reg = <0x400e2000 0x1000>;
269 clocks = <&ccu1 CLK_APB3_CAN0>;
273 gpio: gpio@400f4000 {
274 compatible = "nxp,lpc1850-gpio";
275 reg = <0x400f4000 0x4000>;
276 clocks = <&ccu1 CLK_CPU_GPIO>;
279 gpio-ranges = <&pinctrl LPC_GPIO(0,0) LPC_PIN(0,0) 2>,
280 <&pinctrl LPC_GPIO(0,4) LPC_PIN(1,0) 1>,
281 <&pinctrl LPC_GPIO(0,8) LPC_PIN(1,1) 4>,
282 <&pinctrl LPC_GPIO(1,8) LPC_PIN(1,5) 2>,
283 <&pinctrl LPC_GPIO(1,0) LPC_PIN(1,7) 8>,
284 <&pinctrl LPC_GPIO(0,2) LPC_PIN(1,15) 2>,
285 <&pinctrl LPC_GPIO(0,12) LPC_PIN(1,17) 2>,
286 <&pinctrl LPC_GPIO(0,15) LPC_PIN(1,20) 1>,
287 <&pinctrl LPC_GPIO(5,0) LPC_PIN(2,0) 7>,
288 <&pinctrl LPC_GPIO(0,7) LPC_PIN(2,7) 1>,
289 <&pinctrl LPC_GPIO(5,7) LPC_PIN(2,8) 1>,
290 <&pinctrl LPC_GPIO(1,10) LPC_PIN(2,9) 1>,
291 <&pinctrl LPC_GPIO(0,14) LPC_PIN(2,10) 1>,
292 <&pinctrl LPC_GPIO(1,11) LPC_PIN(2,11) 3>,
293 <&pinctrl LPC_GPIO(5,8) LPC_PIN(3,1) 2>,
294 <&pinctrl LPC_GPIO(1,14) LPC_PIN(3,4) 2>,
295 <&pinctrl LPC_GPIO(0,6) LPC_PIN(3,6) 1>,
296 <&pinctrl LPC_GPIO(5,10) LPC_PIN(3,7) 2>,
297 <&pinctrl LPC_GPIO(2,0) LPC_PIN(4,0) 7>,
298 <&pinctrl LPC_GPIO(5,12) LPC_PIN(4,8) 3>,
299 <&pinctrl LPC_GPIO(2,9) LPC_PIN(5,0) 7>,
300 <&pinctrl LPC_GPIO(2,7) LPC_PIN(5,7) 1>,
301 <&pinctrl LPC_GPIO(3,0) LPC_PIN(6,1) 5>,
302 <&pinctrl LPC_GPIO(0,5) LPC_PIN(6,6) 1>,
303 <&pinctrl LPC_GPIO(5,15) LPC_PIN(6,7) 2>,
304 <&pinctrl LPC_GPIO(3,5) LPC_PIN(6,9) 3>,
305 <&pinctrl LPC_GPIO(2,8) LPC_PIN(6,12) 1>,
306 <&pinctrl LPC_GPIO(3,8) LPC_PIN(7,0) 8>,
307 <&pinctrl LPC_GPIO(4,0) LPC_PIN(8,0) 8>,
308 <&pinctrl LPC_GPIO(4,12) LPC_PIN(9,0) 4>,
309 <&pinctrl LPC_GPIO(5,17) LPC_PIN(9,4) 2>,
310 <&pinctrl LPC_GPIO(4,11) LPC_PIN(9,6) 1>,
311 <&pinctrl LPC_GPIO(4,8) LPC_PIN(a,1) 3>,
312 <&pinctrl LPC_GPIO(5,19) LPC_PIN(a,4) 1>,
313 <&pinctrl LPC_GPIO(5,20) LPC_PIN(b,0) 7>,
314 <&pinctrl LPC_GPIO(6,0) LPC_PIN(c,1) 14>,
315 <&pinctrl LPC_GPIO(6,14) LPC_PIN(d,0) 17>,
316 <&pinctrl LPC_GPIO(7,0) LPC_PIN(e,0) 16>,
317 <&pinctrl LPC_GPIO(7,16) LPC_PIN(f,1) 3>,
318 <&pinctrl LPC_GPIO(7,19) LPC_PIN(f,5) 7>;