arch/arm/boot/dts/omap3.dtsi

   1 /*
   2  * Device Tree Source for OMAP3 SoC
   3  *
   4  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 #include <dt-bindings/gpio/gpio.h>
  12 #include <dt-bindings/interrupt-controller/irq.h>
  13 #include <dt-bindings/pinctrl/omap.h>
  14
  15 #include "skeleton.dtsi"
  16
  17 / {
  18         compatible = "ti,omap3430", "ti,omap3";
  19         interrupt-parent = <&intc>;
  20
  21         aliases {
  22                 i2c0 = &i2c1;
  23                 i2c1 = &i2c2;
  24                 i2c2 = &i2c3;
  25                 serial0 = &uart1;
  26                 serial1 = &uart2;
  27                 serial2 = &uart3;
  28         };
  29
  30         cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33
  34                 cpu@0 {
  35                         compatible = "arm,cortex-a8";
  36                         device_type = "cpu";
  37                         reg = <0x0>;
  38
  39                         clocks = <&dpll1_ck>;
  40                         clock-names = "cpu";
  41
  42                         clock-latency = <300000>; /* From omap-cpufreq driver */
  43                 };
  44         };
  45
  46         pmu {
  47                 compatible = "arm,cortex-a8-pmu";
  48                 reg = <0x54000000 0x800000>;
  49                 interrupts = <3>;
  50                 ti,hwmods = "debugss";
  51         };
  52
  53         /*
  54          * The soc node represents the soc top level view. It is used for IPs
  55          * that are not memory mapped in the MPU view or for the MPU itself.
  56          */
  57         soc {
  58                 compatible = "ti,omap-infra";
  59                 mpu {
  60                         compatible = "ti,omap3-mpu";
  61                         ti,hwmods = "mpu";
  62                 };
  63
  64                 iva: iva {
  65                         compatible = "ti,iva2.2";
  66                         ti,hwmods = "iva";
  67
  68                         dsp {
  69                                 compatible = "ti,omap3-c64";
  70                         };
  71                 };
  72         };
  73
  74         /*
  75          * XXX: Use a flat representation of the OMAP3 interconnect.
  76          * The real OMAP interconnect network is quite complex.
  77          * Since it will not bring real advantage to represent that in DT for
  78          * the moment, just use a fake OCP bus entry to represent the whole bus
  79          * hierarchy.
  80          */
  81         ocp {
  82                 compatible = "ti,omap3-l3-smx", "simple-bus";
  83                 reg = <0x68000000 0x10000>;
  84                 interrupts = <9 10>;
  85                 #address-cells = <1>;
  86                 #size-cells = <1>;
  87                 ranges;
  88                 ti,hwmods = "l3_main";
  89
  90                 aes: aes@480c5000 {
  91                         compatible = "ti,omap3-aes";
  92                         ti,hwmods = "aes";
  93                         reg = <0x480c5000 0x50>;
  94                         interrupts = <0>;
  95                         dmas = <&sdma 65 &sdma 66>;
  96                         dma-names = "tx", "rx";
  97                 };
  98
  99                 prm: prm@48306000 {
 100                         compatible = "ti,omap3-prm";
 101                         reg = <0x48306000 0x4000>;
 102                         interrupts = <11>;
 103
 104                         prm_clocks: clocks {
 105                                 #address-cells = <1>;
 106                                 #size-cells = <0>;
 107                         };
 108
 109                         prm_clockdomains: clockdomains {
 110                         };
 111                 };
 112
 113                 cm: cm@48004000 {
 114                         compatible = "ti,omap3-cm";
 115                         reg = <0x48004000 0x4000>;
 116
 117                         cm_clocks: clocks {
 118                                 #address-cells = <1>;
 119                                 #size-cells = <0>;
 120                         };
 121
 122                         cm_clockdomains: clockdomains {
 123                         };
 124                 };
 125
 126                 scrm: scrm@48002000 {
 127                         compatible = "ti,omap3-scrm";
 128                         reg = <0x48002000 0x2000>;
 129
 130                         scrm_clocks: clocks {
 131                                 #address-cells = <1>;
 132                                 #size-cells = <0>;
 133                         };
 134
 135                         scrm_clockdomains: clockdomains {
 136                         };
 137                 };
 138
 139                 counter32k: counter@48320000 {
 140                         compatible = "ti,omap-counter32k";
 141                         reg = <0x48320000 0x20>;
 142                         ti,hwmods = "counter_32k";
 143                 };
 144
 145                 intc: interrupt-controller@48200000 {
 146                         compatible = "ti,omap3-intc";
 147                         interrupt-controller;
 148                         #interrupt-cells = <1>;
 149                         reg = <0x48200000 0x1000>;
 150                 };
 151
 152                 sdma: dma-controller@48056000 {
 153                         compatible = "ti,omap3630-sdma", "ti,omap3430-sdma";
 154                         reg = <0x48056000 0x1000>;
 155                         interrupts = <12>,
 156                                      <13>,
 157                                      <14>,
 158                                      <15>;
 159                         #dma-cells = <1>;
 160                         dma-channels = <32>;
 161                         dma-requests = <96>;
 162                 };
 163
 164                 omap3_pmx_core: pinmux@48002030 {
 165                         compatible = "ti,omap3-padconf", "pinctrl-single";
 166                         reg = <0x48002030 0x0238>;
 167                         #address-cells = <1>;
 168                         #size-cells = <0>;
 169                         #interrupt-cells = <1>;
 170                         interrupt-controller;
 171                         pinctrl-single,register-width = <16>;
 172                         pinctrl-single,function-mask = <0xff1f>;
 173                 };
 174
 175                 omap3_pmx_wkup: pinmux@48002a00 {
 176                         compatible = "ti,omap3-padconf", "pinctrl-single";
 177                         reg = <0x48002a00 0x5c>;
 178                         #address-cells = <1>;
 179                         #size-cells = <0>;
 180                         #interrupt-cells = <1>;
 181                         interrupt-controller;
 182                         pinctrl-single,register-width = <16>;
 183                         pinctrl-single,function-mask = <0xff1f>;
 184                 };
 185
 186                 omap3_scm_general: tisyscon@48002270 {
 187                         compatible = "syscon";
 188                         reg = <0x48002270 0x2f0>;
 189                 };
 190
 191                 pbias_regulator: pbias_regulator {
 192                         compatible = "ti,pbias-omap";
 193                         reg = <0x2b0 0x4>;
 194                         syscon = <&omap3_scm_general>;
 195                         pbias_mmc_reg: pbias_mmc_omap2430 {
 196                                 regulator-name = "pbias_mmc_omap2430";
 197                                 regulator-min-microvolt = <1800000>;
 198                                 regulator-max-microvolt = <3000000>;
 199                         };
 200                 };
 201
 202                 gpio1: gpio@48310000 {
 203                         compatible = "ti,omap3-gpio";
 204                         reg = <0x48310000 0x200>;
 205                         interrupts = <29>;
 206                         ti,hwmods = "gpio1";
 207                         ti,gpio-always-on;
 208                         gpio-controller;
 209                         #gpio-cells = <2>;
 210                         interrupt-controller;
 211                         #interrupt-cells = <2>;
 212                 };
 213
 214                 gpio2: gpio@49050000 {
 215                         compatible = "ti,omap3-gpio";
 216                         reg = <0x49050000 0x200>;
 217                         interrupts = <30>;
 218                         ti,hwmods = "gpio2";
 219                         gpio-controller;
 220                         #gpio-cells = <2>;
 221                         interrupt-controller;
 222                         #interrupt-cells = <2>;
 223                 };
 224
 225                 gpio3: gpio@49052000 {
 226                         compatible = "ti,omap3-gpio";
 227                         reg = <0x49052000 0x200>;
 228                         interrupts = <31>;
 229                         ti,hwmods = "gpio3";
 230                         gpio-controller;
 231                         #gpio-cells = <2>;
 232                         interrupt-controller;
 233                         #interrupt-cells = <2>;
 234                 };
 235
 236                 gpio4: gpio@49054000 {
 237                         compatible = "ti,omap3-gpio";
 238                         reg = <0x49054000 0x200>;
 239                         interrupts = <32>;
 240                         ti,hwmods = "gpio4";
 241                         gpio-controller;
 242                         #gpio-cells = <2>;
 243                         interrupt-controller;
 244                         #interrupt-cells = <2>;
 245                 };
 246
 247                 gpio5: gpio@49056000 {
 248                         compatible = "ti,omap3-gpio";
 249                         reg = <0x49056000 0x200>;
 250                         interrupts = <33>;
 251                         ti,hwmods = "gpio5";
 252                         gpio-controller;
 253                         #gpio-cells = <2>;
 254                         interrupt-controller;
 255                         #interrupt-cells = <2>;
 256                 };
 257
 258                 gpio6: gpio@49058000 {
 259                         compatible = "ti,omap3-gpio";
 260                         reg = <0x49058000 0x200>;
 261                         interrupts = <34>;
 262                         ti,hwmods = "gpio6";
 263                         gpio-controller;
 264                         #gpio-cells = <2>;
 265                         interrupt-controller;
 266                         #interrupt-cells = <2>;
 267                 };
 268
 269                 uart1: serial@4806a000 {
 270                         compatible = "ti,omap3-uart";
 271                         reg = <0x4806a000 0x2000>;
 272                         interrupts-extended = <&intc 72>;
 273                         dmas = <&sdma 49 &sdma 50>;
 274                         dma-names = "tx", "rx";
 275                         ti,hwmods = "uart1";
 276                         clock-frequency = <48000000>;
 277                 };
 278
 279                 uart2: serial@4806c000 {
 280                         compatible = "ti,omap3-uart";
 281                         reg = <0x4806c000 0x400>;
 282                         interrupts-extended = <&intc 73>;
 283                         dmas = <&sdma 51 &sdma 52>;
 284                         dma-names = "tx", "rx";
 285                         ti,hwmods = "uart2";
 286                         clock-frequency = <48000000>;
 287                 };
 288
 289                 uart3: serial@49020000 {
 290                         compatible = "ti,omap3-uart";
 291                         reg = <0x49020000 0x400>;
 292                         interrupts-extended = <&intc 74>;
 293                         dmas = <&sdma 53 &sdma 54>;
 294                         dma-names = "tx", "rx";
 295                         ti,hwmods = "uart3";
 296                         clock-frequency = <48000000>;
 297                 };
 298
 299                 i2c1: i2c@48070000 {
 300                         compatible = "ti,omap3-i2c";
 301                         reg = <0x48070000 0x80>;
 302                         interrupts = <56>;
 303                         dmas = <&sdma 27 &sdma 28>;
 304                         dma-names = "tx", "rx";
 305                         #address-cells = <1>;
 306                         #size-cells = <0>;
 307                         ti,hwmods = "i2c1";
 308                 };
 309
 310                 i2c2: i2c@48072000 {
 311                         compatible = "ti,omap3-i2c";
 312                         reg = <0x48072000 0x80>;
 313                         interrupts = <57>;
 314                         dmas = <&sdma 29 &sdma 30>;
 315                         dma-names = "tx", "rx";
 316                         #address-cells = <1>;
 317                         #size-cells = <0>;
 318                         ti,hwmods = "i2c2";
 319                 };
 320
 321                 i2c3: i2c@48060000 {
 322                         compatible = "ti,omap3-i2c";
 323                         reg = <0x48060000 0x80>;
 324                         interrupts = <61>;
 325                         dmas = <&sdma 25 &sdma 26>;
 326                         dma-names = "tx", "rx";
 327                         #address-cells = <1>;
 328                         #size-cells = <0>;
 329                         ti,hwmods = "i2c3";
 330                 };
 331
 332                 mailbox: mailbox@48094000 {
 333                         compatible = "ti,omap3-mailbox";
 334                         ti,hwmods = "mailbox";
 335                         reg = <0x48094000 0x200>;
 336                         interrupts = <26>;
 337                         #mbox-cells = <1>;
 338                         ti,mbox-num-users = <2>;
 339                         ti,mbox-num-fifos = <2>;
 340                         mbox_dsp: dsp {
 341                                 ti,mbox-tx = <0 0 0>;
 342                                 ti,mbox-rx = <1 0 0>;
 343                         };
 344                 };
 345
 346                 mcspi1: spi@48098000 {
 347                         compatible = "ti,omap2-mcspi";
 348                         reg = <0x48098000 0x100>;
 349                         interrupts = <65>;
 350                         #address-cells = <1>;
 351                         #size-cells = <0>;
 352                         ti,hwmods = "mcspi1";
 353                         ti,spi-num-cs = <4>;
 354                         dmas = <&sdma 35>,
 355                                <&sdma 36>,
 356                                <&sdma 37>,
 357                                <&sdma 38>,
 358                                <&sdma 39>,
 359                                <&sdma 40>,
 360                                <&sdma 41>,
 361                                <&sdma 42>;
 362                         dma-names = "tx0", "rx0", "tx1", "rx1",
 363                                     "tx2", "rx2", "tx3", "rx3";
 364                 };
 365
 366                 mcspi2: spi@4809a000 {
 367                         compatible = "ti,omap2-mcspi";
 368                         reg = <0x4809a000 0x100>;
 369                         interrupts = <66>;
 370                         #address-cells = <1>;
 371                         #size-cells = <0>;
 372                         ti,hwmods = "mcspi2";
 373                         ti,spi-num-cs = <2>;
 374                         dmas = <&sdma 43>,
 375                                <&sdma 44>,
 376                                <&sdma 45>,
 377                                <&sdma 46>;
 378                         dma-names = "tx0", "rx0", "tx1", "rx1";
 379                 };
 380
 381                 mcspi3: spi@480b8000 {
 382                         compatible = "ti,omap2-mcspi";
 383                         reg = <0x480b8000 0x100>;
 384                         interrupts = <91>;
 385                         #address-cells = <1>;
 386                         #size-cells = <0>;
 387                         ti,hwmods = "mcspi3";
 388                         ti,spi-num-cs = <2>;
 389                         dmas = <&sdma 15>,
 390                                <&sdma 16>,
 391                                <&sdma 23>,
 392                                <&sdma 24>;
 393                         dma-names = "tx0", "rx0", "tx1", "rx1";
 394                 };
 395
 396                 mcspi4: spi@480ba000 {
 397                         compatible = "ti,omap2-mcspi";
 398                         reg = <0x480ba000 0x100>;
 399                         interrupts = <48>;
 400                         #address-cells = <1>;
 401                         #size-cells = <0>;
 402                         ti,hwmods = "mcspi4";
 403                         ti,spi-num-cs = <1>;
 404                         dmas = <&sdma 70>, <&sdma 71>;
 405                         dma-names = "tx0", "rx0";
 406                 };
 407
 408                 hdqw1w: 1w@480b2000 {
 409                         compatible = "ti,omap3-1w";
 410                         reg = <0x480b2000 0x1000>;
 411                         interrupts = <58>;
 412                         ti,hwmods = "hdq1w";
 413                 };
 414
 415                 mmc1: mmc@4809c000 {
 416                         compatible = "ti,omap3-hsmmc";
 417                         reg = <0x4809c000 0x200>;
 418                         interrupts = <83>;
 419                         ti,hwmods = "mmc1";
 420                         ti,dual-volt;
 421                         dmas = <&sdma 61>, <&sdma 62>;
 422                         dma-names = "tx", "rx";
 423                         pbias-supply = <&pbias_mmc_reg>;
 424                 };
 425
 426                 mmc2: mmc@480b4000 {
 427                         compatible = "ti,omap3-hsmmc";
 428                         reg = <0x480b4000 0x200>;
 429                         interrupts = <86>;
 430                         ti,hwmods = "mmc2";
 431                         dmas = <&sdma 47>, <&sdma 48>;
 432                         dma-names = "tx", "rx";
 433                 };
 434
 435                 mmc3: mmc@480ad000 {
 436                         compatible = "ti,omap3-hsmmc";
 437                         reg = <0x480ad000 0x200>;
 438                         interrupts = <94>;
 439                         ti,hwmods = "mmc3";
 440                         dmas = <&sdma 77>, <&sdma 78>;
 441                         dma-names = "tx", "rx";
 442                 };
 443
 444                 mmu_isp: mmu@480bd400 {
 445                         compatible = "ti,omap2-iommu";
 446                         reg = <0x480bd400 0x80>;
 447                         interrupts = <24>;
 448                         ti,hwmods = "mmu_isp";
 449                         ti,#tlb-entries = <8>;
 450                 };
 451
 452                 mmu_iva: mmu@5d000000 {
 453                         compatible = "ti,omap2-iommu";
 454                         reg = <0x5d000000 0x80>;
 455                         interrupts = <28>;
 456                         ti,hwmods = "mmu_iva";
 457                         status = "disabled";
 458                 };
 459
 460                 wdt2: wdt@48314000 {
 461                         compatible = "ti,omap3-wdt";
 462                         reg = <0x48314000 0x80>;
 463                         ti,hwmods = "wd_timer2";
 464                 };
 465
 466                 mcbsp1: mcbsp@48074000 {
 467                         compatible = "ti,omap3-mcbsp";
 468                         reg = <0x48074000 0xff>;
 469                         reg-names = "mpu";
 470                         interrupts = <16>, /* OCP compliant interrupt */
 471                                      <59>, /* TX interrupt */
 472                                      <60>; /* RX interrupt */
 473                         interrupt-names = "common", "tx", "rx";
 474                         ti,buffer-size = <128>;
 475                         ti,hwmods = "mcbsp1";
 476                         dmas = <&sdma 31>,
 477                                <&sdma 32>;
 478                         dma-names = "tx", "rx";
 479                         status = "disabled";
 480                 };
 481
 482                 mcbsp2: mcbsp@49022000 {
 483                         compatible = "ti,omap3-mcbsp";
 484                         reg = <0x49022000 0xff>,
 485                               <0x49028000 0xff>;
 486                         reg-names = "mpu", "sidetone";
 487                         interrupts = <17>, /* OCP compliant interrupt */
 488                                      <62>, /* TX interrupt */
 489                                      <63>, /* RX interrupt */
 490                                      <4>;  /* Sidetone */
 491                         interrupt-names = "common", "tx", "rx", "sidetone";
 492                         ti,buffer-size = <1280>;
 493                         ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
 494                         dmas = <&sdma 33>,
 495                                <&sdma 34>;
 496                         dma-names = "tx", "rx";
 497                         status = "disabled";
 498                 };
 499
 500                 mcbsp3: mcbsp@49024000 {
 501                         compatible = "ti,omap3-mcbsp";
 502                         reg = <0x49024000 0xff>,
 503                               <0x4902a000 0xff>;
 504                         reg-names = "mpu", "sidetone";
 505                         interrupts = <22>, /* OCP compliant interrupt */
 506                                      <89>, /* TX interrupt */
 507                                      <90>, /* RX interrupt */
 508                                      <5>;  /* Sidetone */
 509                         interrupt-names = "common", "tx", "rx", "sidetone";
 510                         ti,buffer-size = <128>;
 511                         ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
 512                         dmas = <&sdma 17>,
 513                                <&sdma 18>;
 514                         dma-names = "tx", "rx";
 515                         status = "disabled";
 516                 };
 517
 518                 mcbsp4: mcbsp@49026000 {
 519                         compatible = "ti,omap3-mcbsp";
 520                         reg = <0x49026000 0xff>;
 521                         reg-names = "mpu";
 522                         interrupts = <23>, /* OCP compliant interrupt */
 523                                      <54>, /* TX interrupt */
 524                                      <55>; /* RX interrupt */
 525                         interrupt-names = "common", "tx", "rx";
 526                         ti,buffer-size = <128>;
 527                         ti,hwmods = "mcbsp4";
 528                         dmas = <&sdma 19>,
 529                                <&sdma 20>;
 530                         dma-names = "tx", "rx";
 531                         status = "disabled";
 532                 };
 533
 534                 mcbsp5: mcbsp@48096000 {
 535                         compatible = "ti,omap3-mcbsp";
 536                         reg = <0x48096000 0xff>;
 537                         reg-names = "mpu";
 538                         interrupts = <27>, /* OCP compliant interrupt */
 539                                      <81>, /* TX interrupt */
 540                                      <82>; /* RX interrupt */
 541                         interrupt-names = "common", "tx", "rx";
 542                         ti,buffer-size = <128>;
 543                         ti,hwmods = "mcbsp5";
 544                         dmas = <&sdma 21>,
 545                                <&sdma 22>;
 546                         dma-names = "tx", "rx";
 547                         status = "disabled";
 548                 };
 549
 550                 sham: sham@480c3000 {
 551                         compatible = "ti,omap3-sham";
 552                         ti,hwmods = "sham";
 553                         reg = <0x480c3000 0x64>;
 554                         interrupts = <49>;
 555                         dmas = <&sdma 69>;
 556                         dma-names = "rx";
 557                 };
 558
 559                 smartreflex_core: smartreflex@480cb000 {
 560                         compatible = "ti,omap3-smartreflex-core";
 561                         ti,hwmods = "smartreflex_core";
 562                         reg = <0x480cb000 0x400>;
 563                         interrupts = <19>;
 564                 };
 565
 566                 smartreflex_mpu_iva: smartreflex@480c9000 {
 567                         compatible = "ti,omap3-smartreflex-iva";
 568                         ti,hwmods = "smartreflex_mpu_iva";
 569                         reg = <0x480c9000 0x400>;
 570                         interrupts = <18>;
 571                 };
 572
 573                 timer1: timer@48318000 {
 574                         compatible = "ti,omap3430-timer";
 575                         reg = <0x48318000 0x400>;
 576                         interrupts = <37>;
 577                         ti,hwmods = "timer1";
 578                         ti,timer-alwon;
 579                 };
 580
 581                 timer2: timer@49032000 {
 582                         compatible = "ti,omap3430-timer";
 583                         reg = <0x49032000 0x400>;
 584                         interrupts = <38>;
 585                         ti,hwmods = "timer2";
 586                 };
 587
 588                 timer3: timer@49034000 {
 589                         compatible = "ti,omap3430-timer";
 590                         reg = <0x49034000 0x400>;
 591                         interrupts = <39>;
 592                         ti,hwmods = "timer3";
 593                 };
 594
 595                 timer4: timer@49036000 {
 596                         compatible = "ti,omap3430-timer";
 597                         reg = <0x49036000 0x400>;
 598                         interrupts = <40>;
 599                         ti,hwmods = "timer4";
 600                 };
 601
 602                 timer5: timer@49038000 {
 603                         compatible = "ti,omap3430-timer";
 604                         reg = <0x49038000 0x400>;
 605                         interrupts = <41>;
 606                         ti,hwmods = "timer5";
 607                         ti,timer-dsp;
 608                 };
 609
 610                 timer6: timer@4903a000 {
 611                         compatible = "ti,omap3430-timer";
 612                         reg = <0x4903a000 0x400>;
 613                         interrupts = <42>;
 614                         ti,hwmods = "timer6";
 615                         ti,timer-dsp;
 616                 };
 617
 618                 timer7: timer@4903c000 {
 619                         compatible = "ti,omap3430-timer";
 620                         reg = <0x4903c000 0x400>;
 621                         interrupts = <43>;
 622                         ti,hwmods = "timer7";
 623                         ti,timer-dsp;
 624                 };
 625
 626                 timer8: timer@4903e000 {
 627                         compatible = "ti,omap3430-timer";
 628                         reg = <0x4903e000 0x400>;
 629                         interrupts = <44>;
 630                         ti,hwmods = "timer8";
 631                         ti,timer-pwm;
 632                         ti,timer-dsp;
 633                 };
 634
 635                 timer9: timer@49040000 {
 636                         compatible = "ti,omap3430-timer";
 637                         reg = <0x49040000 0x400>;
 638                         interrupts = <45>;
 639                         ti,hwmods = "timer9";
 640                         ti,timer-pwm;
 641                 };
 642
 643                 timer10: timer@48086000 {
 644                         compatible = "ti,omap3430-timer";
 645                         reg = <0x48086000 0x400>;
 646                         interrupts = <46>;
 647                         ti,hwmods = "timer10";
 648                         ti,timer-pwm;
 649                 };
 650
 651                 timer11: timer@48088000 {
 652                         compatible = "ti,omap3430-timer";
 653                         reg = <0x48088000 0x400>;
 654                         interrupts = <47>;
 655                         ti,hwmods = "timer11";
 656                         ti,timer-pwm;
 657                 };
 658
 659                 timer12: timer@48304000 {
 660                         compatible = "ti,omap3430-timer";
 661                         reg = <0x48304000 0x400>;
 662                         interrupts = <95>;
 663                         ti,hwmods = "timer12";
 664                         ti,timer-alwon;
 665                         ti,timer-secure;
 666                 };
 667
 668                 usbhstll: usbhstll@48062000 {
 669                         compatible = "ti,usbhs-tll";
 670                         reg = <0x48062000 0x1000>;
 671                         interrupts = <78>;
 672                         ti,hwmods = "usb_tll_hs";
 673                 };
 674
 675                 usbhshost: usbhshost@48064000 {
 676                         compatible = "ti,usbhs-host";
 677                         reg = <0x48064000 0x400>;
 678                         ti,hwmods = "usb_host_hs";
 679                         #address-cells = <1>;
 680                         #size-cells = <1>;
 681                         ranges;
 682
 683                         usbhsohci: ohci@48064400 {
 684                                 compatible = "ti,ohci-omap3";
 685                                 reg = <0x48064400 0x400>;
 686                                 interrupt-parent = <&intc>;
 687                                 interrupts = <76>;
 688                         };
 689
 690                         usbhsehci: ehci@48064800 {
 691                                 compatible = "ti,ehci-omap";
 692                                 reg = <0x48064800 0x400>;
 693                                 interrupt-parent = <&intc>;
 694                                 interrupts = <77>;
 695                         };
 696                 };
 697
 698                 gpmc: gpmc@6e000000 {
 699                         compatible = "ti,omap3430-gpmc";
 700                         ti,hwmods = "gpmc";
 701                         reg = <0x6e000000 0x02d0>;
 702                         interrupts = <20>;
 703                         gpmc,num-cs = <8>;
 704                         gpmc,num-waitpins = <4>;
 705                         #address-cells = <2>;
 706                         #size-cells = <1>;
 707                 };
 708
 709                 usb_otg_hs: usb_otg_hs@480ab000 {
 710                         compatible = "ti,omap3-musb";
 711                         reg = <0x480ab000 0x1000>;
 712                         interrupts = <92>, <93>;
 713                         interrupt-names = "mc", "dma";
 714                         ti,hwmods = "usb_otg_hs";
 715                         multipoint = <1>;
 716                         num-eps = <16>;
 717                         ram-bits = <12>;
 718                 };
 719
 720                 dss: dss@48050000 {
 721                         compatible = "ti,omap3-dss";
 722                         reg = <0x48050000 0x200>;
 723                         status = "disabled";
 724                         ti,hwmods = "dss_core";
 725                         clocks = <&dss1_alwon_fck>;
 726                         clock-names = "fck";
 727                         #address-cells = <1>;
 728                         #size-cells = <1>;
 729                         ranges;
 730
 731                         dispc@48050400 {
 732                                 compatible = "ti,omap3-dispc";
 733                                 reg = <0x48050400 0x400>;
 734                                 interrupts = <25>;
 735                                 ti,hwmods = "dss_dispc";
 736                                 clocks = <&dss1_alwon_fck>;
 737                                 clock-names = "fck";
 738                         };
 739
 740                         dsi: encoder@4804fc00 {
 741                                 compatible = "ti,omap3-dsi";
 742                                 reg = <0x4804fc00 0x200>,
 743                                       <0x4804fe00 0x40>,
 744                                       <0x4804ff00 0x20>;
 745                                 reg-names = "proto", "phy", "pll";
 746                                 interrupts = <25>;
 747                                 status = "disabled";
 748                                 ti,hwmods = "dss_dsi1";
 749                                 clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>;
 750                                 clock-names = "fck", "sys_clk";
 751                         };
 752
 753                         rfbi: encoder@48050800 {
 754                                 compatible = "ti,omap3-rfbi";
 755                                 reg = <0x48050800 0x100>;
 756                                 status = "disabled";
 757                                 ti,hwmods = "dss_rfbi";
 758                                 clocks = <&dss1_alwon_fck>, <&dss_ick>;
 759                                 clock-names = "fck", "ick";
 760                         };
 761
 762                         venc: encoder@48050c00 {
 763                                 compatible = "ti,omap3-venc";
 764                                 reg = <0x48050c00 0x100>;
 765                                 status = "disabled";
 766                                 ti,hwmods = "dss_venc";
 767                                 clocks = <&dss_tv_fck>;
 768                                 clock-names = "fck";
 769                         };
 770                 };
 771
 772                 ssi: ssi-controller@48058000 {
 773                         compatible = "ti,omap3-ssi";
 774                         ti,hwmods = "ssi";
 775
 776                         status = "disabled";
 777
 778                         reg = <0x48058000 0x1000>,
 779                               <0x48059000 0x1000>;
 780                         reg-names = "sys",
 781                                     "gdd";
 782
 783                         interrupts = <71>;
 784                         interrupt-names = "gdd_mpu";
 785
 786                         #address-cells = <1>;
 787                         #size-cells = <1>;
 788                         ranges;
 789
 790                         ssi_port1: ssi-port@4805a000 {
 791                                 compatible = "ti,omap3-ssi-port";
 792
 793                                 reg = <0x4805a000 0x800>,
 794                                       <0x4805a800 0x800>;
 795                                 reg-names = "tx",
 796                                             "rx";
 797
 798                                 interrupt-parent = <&intc>;
 799                                 interrupts = <67>,
 800                                              <68>;
 801                         };
 802
 803                         ssi_port2: ssi-port@4805b000 {
 804                                 compatible = "ti,omap3-ssi-port";
 805
 806                                 reg = <0x4805b000 0x800>,
 807                                       <0x4805b800 0x800>;
 808                                 reg-names = "tx",
 809                                             "rx";
 810
 811                                 interrupt-parent = <&intc>;
 812                                 interrupts = <69>,
 813                                              <70>;
 814                         };
 815                 };
 816         };
 817 };
 818
 819 /include/ "omap3xxx-clocks.dtsi"