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ARM: dts: OMAP2+: Use pinctrl constants
[deliverable/linux.git] / arch / arm / boot / dts / omap4.dtsi
1 /*
2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/omap.h>
12
13 #include "skeleton.dtsi"
14
15 / {
16 compatible = "ti,omap4430", "ti,omap4";
17 interrupt-parent = <&gic>;
18
19 aliases {
20 serial0 = &uart1;
21 serial1 = &uart2;
22 serial2 = &uart3;
23 serial3 = &uart4;
24 };
25
26 cpus {
27 cpu@0 {
28 compatible = "arm,cortex-a9";
29 next-level-cache = <&L2>;
30 };
31 cpu@1 {
32 compatible = "arm,cortex-a9";
33 next-level-cache = <&L2>;
34 };
35 };
36
37 gic: interrupt-controller@48241000 {
38 compatible = "arm,cortex-a9-gic";
39 interrupt-controller;
40 #interrupt-cells = <3>;
41 reg = <0x48241000 0x1000>,
42 <0x48240100 0x0100>;
43 };
44
45 L2: l2-cache-controller@48242000 {
46 compatible = "arm,pl310-cache";
47 reg = <0x48242000 0x1000>;
48 cache-unified;
49 cache-level = <2>;
50 };
51
52 local-timer@0x48240600 {
53 compatible = "arm,cortex-a9-twd-timer";
54 reg = <0x48240600 0x20>;
55 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
56 };
57
58 /*
59 * The soc node represents the soc top level view. It is uses for IPs
60 * that are not memory mapped in the MPU view or for the MPU itself.
61 */
62 soc {
63 compatible = "ti,omap-infra";
64 mpu {
65 compatible = "ti,omap4-mpu";
66 ti,hwmods = "mpu";
67 };
68
69 dsp {
70 compatible = "ti,omap3-c64";
71 ti,hwmods = "dsp";
72 };
73
74 iva {
75 compatible = "ti,ivahd";
76 ti,hwmods = "iva";
77 };
78 };
79
80 /*
81 * XXX: Use a flat representation of the OMAP4 interconnect.
82 * The real OMAP interconnect network is quite complex.
83 * Since that will not bring real advantage to represent that in DT for
84 * the moment, just use a fake OCP bus entry to represent the whole bus
85 * hierarchy.
86 */
87 ocp {
88 compatible = "ti,omap4-l3-noc", "simple-bus";
89 #address-cells = <1>;
90 #size-cells = <1>;
91 ranges;
92 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
93 reg = <0x44000000 0x1000>,
94 <0x44800000 0x2000>,
95 <0x45000000 0x1000>;
96 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
97 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
98
99 counter32k: counter@4a304000 {
100 compatible = "ti,omap-counter32k";
101 reg = <0x4a304000 0x20>;
102 ti,hwmods = "counter_32k";
103 };
104
105 omap4_pmx_core: pinmux@4a100040 {
106 compatible = "ti,omap4-padconf", "pinctrl-single";
107 reg = <0x4a100040 0x0196>;
108 #address-cells = <1>;
109 #size-cells = <0>;
110 pinctrl-single,register-width = <16>;
111 pinctrl-single,function-mask = <0x7fff>;
112 };
113 omap4_pmx_wkup: pinmux@4a31e040 {
114 compatible = "ti,omap4-padconf", "pinctrl-single";
115 reg = <0x4a31e040 0x0038>;
116 #address-cells = <1>;
117 #size-cells = <0>;
118 pinctrl-single,register-width = <16>;
119 pinctrl-single,function-mask = <0x7fff>;
120 };
121
122 sdma: dma-controller@4a056000 {
123 compatible = "ti,omap4430-sdma";
124 reg = <0x4a056000 0x1000>;
125 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
126 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
127 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
128 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
129 #dma-cells = <1>;
130 #dma-channels = <32>;
131 #dma-requests = <127>;
132 };
133
134 gpio1: gpio@4a310000 {
135 compatible = "ti,omap4-gpio";
136 reg = <0x4a310000 0x200>;
137 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
138 ti,hwmods = "gpio1";
139 ti,gpio-always-on;
140 gpio-controller;
141 #gpio-cells = <2>;
142 interrupt-controller;
143 #interrupt-cells = <2>;
144 };
145
146 gpio2: gpio@48055000 {
147 compatible = "ti,omap4-gpio";
148 reg = <0x48055000 0x200>;
149 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
150 ti,hwmods = "gpio2";
151 gpio-controller;
152 #gpio-cells = <2>;
153 interrupt-controller;
154 #interrupt-cells = <2>;
155 };
156
157 gpio3: gpio@48057000 {
158 compatible = "ti,omap4-gpio";
159 reg = <0x48057000 0x200>;
160 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
161 ti,hwmods = "gpio3";
162 gpio-controller;
163 #gpio-cells = <2>;
164 interrupt-controller;
165 #interrupt-cells = <2>;
166 };
167
168 gpio4: gpio@48059000 {
169 compatible = "ti,omap4-gpio";
170 reg = <0x48059000 0x200>;
171 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
172 ti,hwmods = "gpio4";
173 gpio-controller;
174 #gpio-cells = <2>;
175 interrupt-controller;
176 #interrupt-cells = <2>;
177 };
178
179 gpio5: gpio@4805b000 {
180 compatible = "ti,omap4-gpio";
181 reg = <0x4805b000 0x200>;
182 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
183 ti,hwmods = "gpio5";
184 gpio-controller;
185 #gpio-cells = <2>;
186 interrupt-controller;
187 #interrupt-cells = <2>;
188 };
189
190 gpio6: gpio@4805d000 {
191 compatible = "ti,omap4-gpio";
192 reg = <0x4805d000 0x200>;
193 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
194 ti,hwmods = "gpio6";
195 gpio-controller;
196 #gpio-cells = <2>;
197 interrupt-controller;
198 #interrupt-cells = <2>;
199 };
200
201 gpmc: gpmc@50000000 {
202 compatible = "ti,omap4430-gpmc";
203 reg = <0x50000000 0x1000>;
204 #address-cells = <2>;
205 #size-cells = <1>;
206 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
207 gpmc,num-cs = <8>;
208 gpmc,num-waitpins = <4>;
209 ti,hwmods = "gpmc";
210 };
211
212 uart1: serial@4806a000 {
213 compatible = "ti,omap4-uart";
214 reg = <0x4806a000 0x100>;
215 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
216 ti,hwmods = "uart1";
217 clock-frequency = <48000000>;
218 };
219
220 uart2: serial@4806c000 {
221 compatible = "ti,omap4-uart";
222 reg = <0x4806c000 0x100>;
223 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
224 ti,hwmods = "uart2";
225 clock-frequency = <48000000>;
226 };
227
228 uart3: serial@48020000 {
229 compatible = "ti,omap4-uart";
230 reg = <0x48020000 0x100>;
231 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
232 ti,hwmods = "uart3";
233 clock-frequency = <48000000>;
234 };
235
236 uart4: serial@4806e000 {
237 compatible = "ti,omap4-uart";
238 reg = <0x4806e000 0x100>;
239 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
240 ti,hwmods = "uart4";
241 clock-frequency = <48000000>;
242 };
243
244 i2c1: i2c@48070000 {
245 compatible = "ti,omap4-i2c";
246 reg = <0x48070000 0x100>;
247 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
248 #address-cells = <1>;
249 #size-cells = <0>;
250 ti,hwmods = "i2c1";
251 };
252
253 i2c2: i2c@48072000 {
254 compatible = "ti,omap4-i2c";
255 reg = <0x48072000 0x100>;
256 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
257 #address-cells = <1>;
258 #size-cells = <0>;
259 ti,hwmods = "i2c2";
260 };
261
262 i2c3: i2c@48060000 {
263 compatible = "ti,omap4-i2c";
264 reg = <0x48060000 0x100>;
265 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
266 #address-cells = <1>;
267 #size-cells = <0>;
268 ti,hwmods = "i2c3";
269 };
270
271 i2c4: i2c@48350000 {
272 compatible = "ti,omap4-i2c";
273 reg = <0x48350000 0x100>;
274 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
275 #address-cells = <1>;
276 #size-cells = <0>;
277 ti,hwmods = "i2c4";
278 };
279
280 mcspi1: spi@48098000 {
281 compatible = "ti,omap4-mcspi";
282 reg = <0x48098000 0x200>;
283 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
284 #address-cells = <1>;
285 #size-cells = <0>;
286 ti,hwmods = "mcspi1";
287 ti,spi-num-cs = <4>;
288 dmas = <&sdma 35>,
289 <&sdma 36>,
290 <&sdma 37>,
291 <&sdma 38>,
292 <&sdma 39>,
293 <&sdma 40>,
294 <&sdma 41>,
295 <&sdma 42>;
296 dma-names = "tx0", "rx0", "tx1", "rx1",
297 "tx2", "rx2", "tx3", "rx3";
298 };
299
300 mcspi2: spi@4809a000 {
301 compatible = "ti,omap4-mcspi";
302 reg = <0x4809a000 0x200>;
303 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
304 #address-cells = <1>;
305 #size-cells = <0>;
306 ti,hwmods = "mcspi2";
307 ti,spi-num-cs = <2>;
308 dmas = <&sdma 43>,
309 <&sdma 44>,
310 <&sdma 45>,
311 <&sdma 46>;
312 dma-names = "tx0", "rx0", "tx1", "rx1";
313 };
314
315 mcspi3: spi@480b8000 {
316 compatible = "ti,omap4-mcspi";
317 reg = <0x480b8000 0x200>;
318 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
319 #address-cells = <1>;
320 #size-cells = <0>;
321 ti,hwmods = "mcspi3";
322 ti,spi-num-cs = <2>;
323 dmas = <&sdma 15>, <&sdma 16>;
324 dma-names = "tx0", "rx0";
325 };
326
327 mcspi4: spi@480ba000 {
328 compatible = "ti,omap4-mcspi";
329 reg = <0x480ba000 0x200>;
330 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
331 #address-cells = <1>;
332 #size-cells = <0>;
333 ti,hwmods = "mcspi4";
334 ti,spi-num-cs = <1>;
335 dmas = <&sdma 70>, <&sdma 71>;
336 dma-names = "tx0", "rx0";
337 };
338
339 mmc1: mmc@4809c000 {
340 compatible = "ti,omap4-hsmmc";
341 reg = <0x4809c000 0x400>;
342 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
343 ti,hwmods = "mmc1";
344 ti,dual-volt;
345 ti,needs-special-reset;
346 dmas = <&sdma 61>, <&sdma 62>;
347 dma-names = "tx", "rx";
348 };
349
350 mmc2: mmc@480b4000 {
351 compatible = "ti,omap4-hsmmc";
352 reg = <0x480b4000 0x400>;
353 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
354 ti,hwmods = "mmc2";
355 ti,needs-special-reset;
356 dmas = <&sdma 47>, <&sdma 48>;
357 dma-names = "tx", "rx";
358 };
359
360 mmc3: mmc@480ad000 {
361 compatible = "ti,omap4-hsmmc";
362 reg = <0x480ad000 0x400>;
363 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
364 ti,hwmods = "mmc3";
365 ti,needs-special-reset;
366 dmas = <&sdma 77>, <&sdma 78>;
367 dma-names = "tx", "rx";
368 };
369
370 mmc4: mmc@480d1000 {
371 compatible = "ti,omap4-hsmmc";
372 reg = <0x480d1000 0x400>;
373 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
374 ti,hwmods = "mmc4";
375 ti,needs-special-reset;
376 dmas = <&sdma 57>, <&sdma 58>;
377 dma-names = "tx", "rx";
378 };
379
380 mmc5: mmc@480d5000 {
381 compatible = "ti,omap4-hsmmc";
382 reg = <0x480d5000 0x400>;
383 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
384 ti,hwmods = "mmc5";
385 ti,needs-special-reset;
386 dmas = <&sdma 59>, <&sdma 60>;
387 dma-names = "tx", "rx";
388 };
389
390 wdt2: wdt@4a314000 {
391 compatible = "ti,omap4-wdt", "ti,omap3-wdt";
392 reg = <0x4a314000 0x80>;
393 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
394 ti,hwmods = "wd_timer2";
395 };
396
397 mcpdm: mcpdm@40132000 {
398 compatible = "ti,omap4-mcpdm";
399 reg = <0x40132000 0x7f>, /* MPU private access */
400 <0x49032000 0x7f>; /* L3 Interconnect */
401 reg-names = "mpu", "dma";
402 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
403 ti,hwmods = "mcpdm";
404 dmas = <&sdma 65>,
405 <&sdma 66>;
406 dma-names = "up_link", "dn_link";
407 };
408
409 dmic: dmic@4012e000 {
410 compatible = "ti,omap4-dmic";
411 reg = <0x4012e000 0x7f>, /* MPU private access */
412 <0x4902e000 0x7f>; /* L3 Interconnect */
413 reg-names = "mpu", "dma";
414 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
415 ti,hwmods = "dmic";
416 dmas = <&sdma 67>;
417 dma-names = "up_link";
418 };
419
420 mcbsp1: mcbsp@40122000 {
421 compatible = "ti,omap4-mcbsp";
422 reg = <0x40122000 0xff>, /* MPU private access */
423 <0x49022000 0xff>; /* L3 Interconnect */
424 reg-names = "mpu", "dma";
425 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
426 interrupt-names = "common";
427 ti,buffer-size = <128>;
428 ti,hwmods = "mcbsp1";
429 dmas = <&sdma 33>,
430 <&sdma 34>;
431 dma-names = "tx", "rx";
432 };
433
434 mcbsp2: mcbsp@40124000 {
435 compatible = "ti,omap4-mcbsp";
436 reg = <0x40124000 0xff>, /* MPU private access */
437 <0x49024000 0xff>; /* L3 Interconnect */
438 reg-names = "mpu", "dma";
439 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
440 interrupt-names = "common";
441 ti,buffer-size = <128>;
442 ti,hwmods = "mcbsp2";
443 dmas = <&sdma 17>,
444 <&sdma 18>;
445 dma-names = "tx", "rx";
446 };
447
448 mcbsp3: mcbsp@40126000 {
449 compatible = "ti,omap4-mcbsp";
450 reg = <0x40126000 0xff>, /* MPU private access */
451 <0x49026000 0xff>; /* L3 Interconnect */
452 reg-names = "mpu", "dma";
453 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
454 interrupt-names = "common";
455 ti,buffer-size = <128>;
456 ti,hwmods = "mcbsp3";
457 dmas = <&sdma 19>,
458 <&sdma 20>;
459 dma-names = "tx", "rx";
460 };
461
462 mcbsp4: mcbsp@48096000 {
463 compatible = "ti,omap4-mcbsp";
464 reg = <0x48096000 0xff>; /* L4 Interconnect */
465 reg-names = "mpu";
466 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
467 interrupt-names = "common";
468 ti,buffer-size = <128>;
469 ti,hwmods = "mcbsp4";
470 dmas = <&sdma 31>,
471 <&sdma 32>;
472 dma-names = "tx", "rx";
473 };
474
475 keypad: keypad@4a31c000 {
476 compatible = "ti,omap4-keypad";
477 reg = <0x4a31c000 0x80>;
478 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
479 reg-names = "mpu";
480 ti,hwmods = "kbd";
481 };
482
483 emif1: emif@4c000000 {
484 compatible = "ti,emif-4d";
485 reg = <0x4c000000 0x100>;
486 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
487 ti,hwmods = "emif1";
488 phy-type = <1>;
489 hw-caps-read-idle-ctrl;
490 hw-caps-ll-interface;
491 hw-caps-temp-alert;
492 };
493
494 emif2: emif@4d000000 {
495 compatible = "ti,emif-4d";
496 reg = <0x4d000000 0x100>;
497 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
498 ti,hwmods = "emif2";
499 phy-type = <1>;
500 hw-caps-read-idle-ctrl;
501 hw-caps-ll-interface;
502 hw-caps-temp-alert;
503 };
504
505 ocp2scp@4a0ad000 {
506 compatible = "ti,omap-ocp2scp";
507 reg = <0x4a0ad000 0x1f>;
508 #address-cells = <1>;
509 #size-cells = <1>;
510 ranges;
511 ti,hwmods = "ocp2scp_usb_phy";
512 usb2_phy: usb2phy@4a0ad080 {
513 compatible = "ti,omap-usb2";
514 reg = <0x4a0ad080 0x58>;
515 ctrl-module = <&omap_control_usb>;
516 };
517 };
518
519 timer1: timer@4a318000 {
520 compatible = "ti,omap3430-timer";
521 reg = <0x4a318000 0x80>;
522 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
523 ti,hwmods = "timer1";
524 ti,timer-alwon;
525 };
526
527 timer2: timer@48032000 {
528 compatible = "ti,omap3430-timer";
529 reg = <0x48032000 0x80>;
530 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
531 ti,hwmods = "timer2";
532 };
533
534 timer3: timer@48034000 {
535 compatible = "ti,omap4430-timer";
536 reg = <0x48034000 0x80>;
537 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
538 ti,hwmods = "timer3";
539 };
540
541 timer4: timer@48036000 {
542 compatible = "ti,omap4430-timer";
543 reg = <0x48036000 0x80>;
544 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
545 ti,hwmods = "timer4";
546 };
547
548 timer5: timer@40138000 {
549 compatible = "ti,omap4430-timer";
550 reg = <0x40138000 0x80>,
551 <0x49038000 0x80>;
552 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
553 ti,hwmods = "timer5";
554 ti,timer-dsp;
555 };
556
557 timer6: timer@4013a000 {
558 compatible = "ti,omap4430-timer";
559 reg = <0x4013a000 0x80>,
560 <0x4903a000 0x80>;
561 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
562 ti,hwmods = "timer6";
563 ti,timer-dsp;
564 };
565
566 timer7: timer@4013c000 {
567 compatible = "ti,omap4430-timer";
568 reg = <0x4013c000 0x80>,
569 <0x4903c000 0x80>;
570 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
571 ti,hwmods = "timer7";
572 ti,timer-dsp;
573 };
574
575 timer8: timer@4013e000 {
576 compatible = "ti,omap4430-timer";
577 reg = <0x4013e000 0x80>,
578 <0x4903e000 0x80>;
579 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
580 ti,hwmods = "timer8";
581 ti,timer-pwm;
582 ti,timer-dsp;
583 };
584
585 timer9: timer@4803e000 {
586 compatible = "ti,omap4430-timer";
587 reg = <0x4803e000 0x80>;
588 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
589 ti,hwmods = "timer9";
590 ti,timer-pwm;
591 };
592
593 timer10: timer@48086000 {
594 compatible = "ti,omap3430-timer";
595 reg = <0x48086000 0x80>;
596 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
597 ti,hwmods = "timer10";
598 ti,timer-pwm;
599 };
600
601 timer11: timer@48088000 {
602 compatible = "ti,omap4430-timer";
603 reg = <0x48088000 0x80>;
604 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
605 ti,hwmods = "timer11";
606 ti,timer-pwm;
607 };
608
609 usbhstll: usbhstll@4a062000 {
610 compatible = "ti,usbhs-tll";
611 reg = <0x4a062000 0x1000>;
612 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
613 ti,hwmods = "usb_tll_hs";
614 };
615
616 usbhshost: usbhshost@4a064000 {
617 compatible = "ti,usbhs-host";
618 reg = <0x4a064000 0x800>;
619 ti,hwmods = "usb_host_hs";
620 #address-cells = <1>;
621 #size-cells = <1>;
622 ranges;
623
624 usbhsohci: ohci@4a064800 {
625 compatible = "ti,ohci-omap3", "usb-ohci";
626 reg = <0x4a064800 0x400>;
627 interrupt-parent = <&gic>;
628 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
629 };
630
631 usbhsehci: ehci@4a064c00 {
632 compatible = "ti,ehci-omap", "usb-ehci";
633 reg = <0x4a064c00 0x400>;
634 interrupt-parent = <&gic>;
635 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
636 };
637 };
638
639 omap_control_usb: omap-control-usb@4a002300 {
640 compatible = "ti,omap-control-usb";
641 reg = <0x4a002300 0x4>,
642 <0x4a00233c 0x4>;
643 reg-names = "control_dev_conf", "otghs_control";
644 ti,type = <1>;
645 };
646
647 usb_otg_hs: usb_otg_hs@4a0ab000 {
648 compatible = "ti,omap4-musb";
649 reg = <0x4a0ab000 0x7ff>;
650 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
651 interrupt-names = "mc", "dma";
652 ti,hwmods = "usb_otg_hs";
653 usb-phy = <&usb2_phy>;
654 multipoint = <1>;
655 num-eps = <16>;
656 ram-bits = <12>;
657 ti,has-mailbox;
658 };
659 };
660 };
Linux kernel - Deliverables
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