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Merge branch 'topic/firewire-update' into for-next
[deliverable/linux.git] / arch / arm / boot / dts / omap4.dtsi
1 /*
2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/omap.h>
12
13 #include "skeleton.dtsi"
14
15 / {
16 compatible = "ti,omap4430", "ti,omap4";
17 interrupt-parent = <&wakeupgen>;
18
19 aliases {
20 i2c0 = &i2c1;
21 i2c1 = &i2c2;
22 i2c2 = &i2c3;
23 i2c3 = &i2c4;
24 serial0 = &uart1;
25 serial1 = &uart2;
26 serial2 = &uart3;
27 serial3 = &uart4;
28 };
29
30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33
34 cpu@0 {
35 compatible = "arm,cortex-a9";
36 device_type = "cpu";
37 next-level-cache = <&L2>;
38 reg = <0x0>;
39
40 clocks = <&dpll_mpu_ck>;
41 clock-names = "cpu";
42
43 clock-latency = <300000>; /* From omap-cpufreq driver */
44 };
45 cpu@1 {
46 compatible = "arm,cortex-a9";
47 device_type = "cpu";
48 next-level-cache = <&L2>;
49 reg = <0x1>;
50 };
51 };
52
53 gic: interrupt-controller@48241000 {
54 compatible = "arm,cortex-a9-gic";
55 interrupt-controller;
56 #interrupt-cells = <3>;
57 reg = <0x48241000 0x1000>,
58 <0x48240100 0x0100>;
59 interrupt-parent = <&gic>;
60 };
61
62 L2: l2-cache-controller@48242000 {
63 compatible = "arm,pl310-cache";
64 reg = <0x48242000 0x1000>;
65 cache-unified;
66 cache-level = <2>;
67 };
68
69 local-timer@48240600 {
70 compatible = "arm,cortex-a9-twd-timer";
71 clocks = <&mpu_periphclk>;
72 reg = <0x48240600 0x20>;
73 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
74 interrupt-parent = <&gic>;
75 };
76
77 wakeupgen: interrupt-controller@48281000 {
78 compatible = "ti,omap4-wugen-mpu";
79 interrupt-controller;
80 #interrupt-cells = <3>;
81 reg = <0x48281000 0x1000>;
82 interrupt-parent = <&gic>;
83 };
84
85 /*
86 * The soc node represents the soc top level view. It is used for IPs
87 * that are not memory mapped in the MPU view or for the MPU itself.
88 */
89 soc {
90 compatible = "ti,omap-infra";
91 mpu {
92 compatible = "ti,omap4-mpu";
93 ti,hwmods = "mpu";
94 sram = <&ocmcram>;
95 };
96
97 dsp {
98 compatible = "ti,omap3-c64";
99 ti,hwmods = "dsp";
100 };
101
102 iva {
103 compatible = "ti,ivahd";
104 ti,hwmods = "iva";
105 };
106 };
107
108 /*
109 * XXX: Use a flat representation of the OMAP4 interconnect.
110 * The real OMAP interconnect network is quite complex.
111 * Since it will not bring real advantage to represent that in DT for
112 * the moment, just use a fake OCP bus entry to represent the whole bus
113 * hierarchy.
114 */
115 ocp {
116 compatible = "ti,omap4-l3-noc", "simple-bus";
117 #address-cells = <1>;
118 #size-cells = <1>;
119 ranges;
120 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
121 reg = <0x44000000 0x1000>,
122 <0x44800000 0x2000>,
123 <0x45000000 0x1000>;
124 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
125 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
126
127 l4_cfg: l4@4a000000 {
128 compatible = "ti,omap4-l4-cfg", "simple-bus";
129 #address-cells = <1>;
130 #size-cells = <1>;
131 ranges = <0 0x4a000000 0x1000000>;
132
133 cm1: cm1@4000 {
134 compatible = "ti,omap4-cm1";
135 reg = <0x4000 0x2000>;
136
137 cm1_clocks: clocks {
138 #address-cells = <1>;
139 #size-cells = <0>;
140 };
141
142 cm1_clockdomains: clockdomains {
143 };
144 };
145
146 cm2: cm2@8000 {
147 compatible = "ti,omap4-cm2";
148 reg = <0x8000 0x3000>;
149
150 cm2_clocks: clocks {
151 #address-cells = <1>;
152 #size-cells = <0>;
153 };
154
155 cm2_clockdomains: clockdomains {
156 };
157 };
158
159 omap4_scm_core: scm@2000 {
160 compatible = "ti,omap4-scm-core", "simple-bus";
161 reg = <0x2000 0x1000>;
162 #address-cells = <1>;
163 #size-cells = <1>;
164 ranges = <0 0x2000 0x1000>;
165
166 scm_conf: scm_conf@0 {
167 compatible = "syscon";
168 reg = <0x0 0x800>;
169 #address-cells = <1>;
170 #size-cells = <1>;
171 };
172 };
173
174 omap4_padconf_core: scm@100000 {
175 compatible = "ti,omap4-scm-padconf-core",
176 "simple-bus";
177 #address-cells = <1>;
178 #size-cells = <1>;
179 ranges = <0 0x100000 0x1000>;
180
181 omap4_pmx_core: pinmux@40 {
182 compatible = "ti,omap4-padconf",
183 "pinctrl-single";
184 reg = <0x40 0x0196>;
185 #address-cells = <1>;
186 #size-cells = <0>;
187 #interrupt-cells = <1>;
188 interrupt-controller;
189 pinctrl-single,register-width = <16>;
190 pinctrl-single,function-mask = <0x7fff>;
191 };
192
193 omap4_padconf_global: omap4_padconf_global@5a0 {
194 compatible = "syscon",
195 "simple-bus";
196 reg = <0x5a0 0x170>;
197 #address-cells = <1>;
198 #size-cells = <1>;
199 ranges = <0 0x5a0 0x170>;
200
201 pbias_regulator: pbias_regulator {
202 compatible = "ti,pbias-omap4", "ti,pbias-omap";
203 reg = <0x60 0x4>;
204 syscon = <&omap4_padconf_global>;
205 pbias_mmc_reg: pbias_mmc_omap4 {
206 regulator-name = "pbias_mmc_omap4";
207 regulator-min-microvolt = <1800000>;
208 regulator-max-microvolt = <3000000>;
209 };
210 };
211 };
212 };
213
214 l4_wkup: l4@300000 {
215 compatible = "ti,omap4-l4-wkup", "simple-bus";
216 #address-cells = <1>;
217 #size-cells = <1>;
218 ranges = <0 0x300000 0x40000>;
219
220 counter32k: counter@4000 {
221 compatible = "ti,omap-counter32k";
222 reg = <0x4000 0x20>;
223 ti,hwmods = "counter_32k";
224 };
225
226 prm: prm@6000 {
227 compatible = "ti,omap4-prm";
228 reg = <0x6000 0x3000>;
229 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
230
231 prm_clocks: clocks {
232 #address-cells = <1>;
233 #size-cells = <0>;
234 };
235
236 prm_clockdomains: clockdomains {
237 };
238 };
239
240 scrm: scrm@a000 {
241 compatible = "ti,omap4-scrm";
242 reg = <0xa000 0x2000>;
243
244 scrm_clocks: clocks {
245 #address-cells = <1>;
246 #size-cells = <0>;
247 };
248
249 scrm_clockdomains: clockdomains {
250 };
251 };
252
253 omap4_pmx_wkup: pinmux@1e040 {
254 compatible = "ti,omap4-padconf",
255 "pinctrl-single";
256 reg = <0x1e040 0x0038>;
257 #address-cells = <1>;
258 #size-cells = <0>;
259 #interrupt-cells = <1>;
260 interrupt-controller;
261 pinctrl-single,register-width = <16>;
262 pinctrl-single,function-mask = <0x7fff>;
263 };
264 };
265 };
266
267 ocmcram: ocmcram@40304000 {
268 compatible = "mmio-sram";
269 reg = <0x40304000 0xa000>; /* 40k */
270 };
271
272 sdma: dma-controller@4a056000 {
273 compatible = "ti,omap4430-sdma";
274 reg = <0x4a056000 0x1000>;
275 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
276 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
277 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
278 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
279 #dma-cells = <1>;
280 dma-channels = <32>;
281 dma-requests = <127>;
282 };
283
284 gpio1: gpio@4a310000 {
285 compatible = "ti,omap4-gpio";
286 reg = <0x4a310000 0x200>;
287 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
288 ti,hwmods = "gpio1";
289 ti,gpio-always-on;
290 gpio-controller;
291 #gpio-cells = <2>;
292 interrupt-controller;
293 #interrupt-cells = <2>;
294 };
295
296 gpio2: gpio@48055000 {
297 compatible = "ti,omap4-gpio";
298 reg = <0x48055000 0x200>;
299 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
300 ti,hwmods = "gpio2";
301 gpio-controller;
302 #gpio-cells = <2>;
303 interrupt-controller;
304 #interrupt-cells = <2>;
305 };
306
307 gpio3: gpio@48057000 {
308 compatible = "ti,omap4-gpio";
309 reg = <0x48057000 0x200>;
310 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
311 ti,hwmods = "gpio3";
312 gpio-controller;
313 #gpio-cells = <2>;
314 interrupt-controller;
315 #interrupt-cells = <2>;
316 };
317
318 gpio4: gpio@48059000 {
319 compatible = "ti,omap4-gpio";
320 reg = <0x48059000 0x200>;
321 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
322 ti,hwmods = "gpio4";
323 gpio-controller;
324 #gpio-cells = <2>;
325 interrupt-controller;
326 #interrupt-cells = <2>;
327 };
328
329 gpio5: gpio@4805b000 {
330 compatible = "ti,omap4-gpio";
331 reg = <0x4805b000 0x200>;
332 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
333 ti,hwmods = "gpio5";
334 gpio-controller;
335 #gpio-cells = <2>;
336 interrupt-controller;
337 #interrupt-cells = <2>;
338 };
339
340 gpio6: gpio@4805d000 {
341 compatible = "ti,omap4-gpio";
342 reg = <0x4805d000 0x200>;
343 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
344 ti,hwmods = "gpio6";
345 gpio-controller;
346 #gpio-cells = <2>;
347 interrupt-controller;
348 #interrupt-cells = <2>;
349 };
350
351 gpmc: gpmc@50000000 {
352 compatible = "ti,omap4430-gpmc";
353 reg = <0x50000000 0x1000>;
354 #address-cells = <2>;
355 #size-cells = <1>;
356 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
357 gpmc,num-cs = <8>;
358 gpmc,num-waitpins = <4>;
359 ti,hwmods = "gpmc";
360 ti,no-idle-on-init;
361 clocks = <&l3_div_ck>;
362 clock-names = "fck";
363 };
364
365 uart1: serial@4806a000 {
366 compatible = "ti,omap4-uart";
367 reg = <0x4806a000 0x100>;
368 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
369 ti,hwmods = "uart1";
370 clock-frequency = <48000000>;
371 };
372
373 uart2: serial@4806c000 {
374 compatible = "ti,omap4-uart";
375 reg = <0x4806c000 0x100>;
376 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
377 ti,hwmods = "uart2";
378 clock-frequency = <48000000>;
379 };
380
381 uart3: serial@48020000 {
382 compatible = "ti,omap4-uart";
383 reg = <0x48020000 0x100>;
384 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
385 ti,hwmods = "uart3";
386 clock-frequency = <48000000>;
387 };
388
389 uart4: serial@4806e000 {
390 compatible = "ti,omap4-uart";
391 reg = <0x4806e000 0x100>;
392 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
393 ti,hwmods = "uart4";
394 clock-frequency = <48000000>;
395 };
396
397 hwspinlock: spinlock@4a0f6000 {
398 compatible = "ti,omap4-hwspinlock";
399 reg = <0x4a0f6000 0x1000>;
400 ti,hwmods = "spinlock";
401 #hwlock-cells = <1>;
402 };
403
404 i2c1: i2c@48070000 {
405 compatible = "ti,omap4-i2c";
406 reg = <0x48070000 0x100>;
407 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
408 #address-cells = <1>;
409 #size-cells = <0>;
410 ti,hwmods = "i2c1";
411 };
412
413 i2c2: i2c@48072000 {
414 compatible = "ti,omap4-i2c";
415 reg = <0x48072000 0x100>;
416 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
417 #address-cells = <1>;
418 #size-cells = <0>;
419 ti,hwmods = "i2c2";
420 };
421
422 i2c3: i2c@48060000 {
423 compatible = "ti,omap4-i2c";
424 reg = <0x48060000 0x100>;
425 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
426 #address-cells = <1>;
427 #size-cells = <0>;
428 ti,hwmods = "i2c3";
429 };
430
431 i2c4: i2c@48350000 {
432 compatible = "ti,omap4-i2c";
433 reg = <0x48350000 0x100>;
434 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
435 #address-cells = <1>;
436 #size-cells = <0>;
437 ti,hwmods = "i2c4";
438 };
439
440 mcspi1: spi@48098000 {
441 compatible = "ti,omap4-mcspi";
442 reg = <0x48098000 0x200>;
443 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
444 #address-cells = <1>;
445 #size-cells = <0>;
446 ti,hwmods = "mcspi1";
447 ti,spi-num-cs = <4>;
448 dmas = <&sdma 35>,
449 <&sdma 36>,
450 <&sdma 37>,
451 <&sdma 38>,
452 <&sdma 39>,
453 <&sdma 40>,
454 <&sdma 41>,
455 <&sdma 42>;
456 dma-names = "tx0", "rx0", "tx1", "rx1",
457 "tx2", "rx2", "tx3", "rx3";
458 };
459
460 mcspi2: spi@4809a000 {
461 compatible = "ti,omap4-mcspi";
462 reg = <0x4809a000 0x200>;
463 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
464 #address-cells = <1>;
465 #size-cells = <0>;
466 ti,hwmods = "mcspi2";
467 ti,spi-num-cs = <2>;
468 dmas = <&sdma 43>,
469 <&sdma 44>,
470 <&sdma 45>,
471 <&sdma 46>;
472 dma-names = "tx0", "rx0", "tx1", "rx1";
473 };
474
475 mcspi3: spi@480b8000 {
476 compatible = "ti,omap4-mcspi";
477 reg = <0x480b8000 0x200>;
478 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
479 #address-cells = <1>;
480 #size-cells = <0>;
481 ti,hwmods = "mcspi3";
482 ti,spi-num-cs = <2>;
483 dmas = <&sdma 15>, <&sdma 16>;
484 dma-names = "tx0", "rx0";
485 };
486
487 mcspi4: spi@480ba000 {
488 compatible = "ti,omap4-mcspi";
489 reg = <0x480ba000 0x200>;
490 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
491 #address-cells = <1>;
492 #size-cells = <0>;
493 ti,hwmods = "mcspi4";
494 ti,spi-num-cs = <1>;
495 dmas = <&sdma 70>, <&sdma 71>;
496 dma-names = "tx0", "rx0";
497 };
498
499 mmc1: mmc@4809c000 {
500 compatible = "ti,omap4-hsmmc";
501 reg = <0x4809c000 0x400>;
502 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
503 ti,hwmods = "mmc1";
504 ti,dual-volt;
505 ti,needs-special-reset;
506 dmas = <&sdma 61>, <&sdma 62>;
507 dma-names = "tx", "rx";
508 pbias-supply = <&pbias_mmc_reg>;
509 };
510
511 mmc2: mmc@480b4000 {
512 compatible = "ti,omap4-hsmmc";
513 reg = <0x480b4000 0x400>;
514 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
515 ti,hwmods = "mmc2";
516 ti,needs-special-reset;
517 dmas = <&sdma 47>, <&sdma 48>;
518 dma-names = "tx", "rx";
519 };
520
521 mmc3: mmc@480ad000 {
522 compatible = "ti,omap4-hsmmc";
523 reg = <0x480ad000 0x400>;
524 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
525 ti,hwmods = "mmc3";
526 ti,needs-special-reset;
527 dmas = <&sdma 77>, <&sdma 78>;
528 dma-names = "tx", "rx";
529 };
530
531 mmc4: mmc@480d1000 {
532 compatible = "ti,omap4-hsmmc";
533 reg = <0x480d1000 0x400>;
534 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
535 ti,hwmods = "mmc4";
536 ti,needs-special-reset;
537 dmas = <&sdma 57>, <&sdma 58>;
538 dma-names = "tx", "rx";
539 };
540
541 mmc5: mmc@480d5000 {
542 compatible = "ti,omap4-hsmmc";
543 reg = <0x480d5000 0x400>;
544 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
545 ti,hwmods = "mmc5";
546 ti,needs-special-reset;
547 dmas = <&sdma 59>, <&sdma 60>;
548 dma-names = "tx", "rx";
549 };
550
551 mmu_dsp: mmu@4a066000 {
552 compatible = "ti,omap4-iommu";
553 reg = <0x4a066000 0x100>;
554 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
555 ti,hwmods = "mmu_dsp";
556 #iommu-cells = <0>;
557 };
558
559 mmu_ipu: mmu@55082000 {
560 compatible = "ti,omap4-iommu";
561 reg = <0x55082000 0x100>;
562 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
563 ti,hwmods = "mmu_ipu";
564 #iommu-cells = <0>;
565 ti,iommu-bus-err-back;
566 };
567
568 wdt2: wdt@4a314000 {
569 compatible = "ti,omap4-wdt", "ti,omap3-wdt";
570 reg = <0x4a314000 0x80>;
571 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
572 ti,hwmods = "wd_timer2";
573 };
574
575 mcpdm: mcpdm@40132000 {
576 compatible = "ti,omap4-mcpdm";
577 reg = <0x40132000 0x7f>, /* MPU private access */
578 <0x49032000 0x7f>; /* L3 Interconnect */
579 reg-names = "mpu", "dma";
580 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
581 ti,hwmods = "mcpdm";
582 dmas = <&sdma 65>,
583 <&sdma 66>;
584 dma-names = "up_link", "dn_link";
585 status = "disabled";
586 };
587
588 dmic: dmic@4012e000 {
589 compatible = "ti,omap4-dmic";
590 reg = <0x4012e000 0x7f>, /* MPU private access */
591 <0x4902e000 0x7f>; /* L3 Interconnect */
592 reg-names = "mpu", "dma";
593 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
594 ti,hwmods = "dmic";
595 dmas = <&sdma 67>;
596 dma-names = "up_link";
597 status = "disabled";
598 };
599
600 mcbsp1: mcbsp@40122000 {
601 compatible = "ti,omap4-mcbsp";
602 reg = <0x40122000 0xff>, /* MPU private access */
603 <0x49022000 0xff>; /* L3 Interconnect */
604 reg-names = "mpu", "dma";
605 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
606 interrupt-names = "common";
607 ti,buffer-size = <128>;
608 ti,hwmods = "mcbsp1";
609 dmas = <&sdma 33>,
610 <&sdma 34>;
611 dma-names = "tx", "rx";
612 status = "disabled";
613 };
614
615 mcbsp2: mcbsp@40124000 {
616 compatible = "ti,omap4-mcbsp";
617 reg = <0x40124000 0xff>, /* MPU private access */
618 <0x49024000 0xff>; /* L3 Interconnect */
619 reg-names = "mpu", "dma";
620 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
621 interrupt-names = "common";
622 ti,buffer-size = <128>;
623 ti,hwmods = "mcbsp2";
624 dmas = <&sdma 17>,
625 <&sdma 18>;
626 dma-names = "tx", "rx";
627 status = "disabled";
628 };
629
630 mcbsp3: mcbsp@40126000 {
631 compatible = "ti,omap4-mcbsp";
632 reg = <0x40126000 0xff>, /* MPU private access */
633 <0x49026000 0xff>; /* L3 Interconnect */
634 reg-names = "mpu", "dma";
635 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
636 interrupt-names = "common";
637 ti,buffer-size = <128>;
638 ti,hwmods = "mcbsp3";
639 dmas = <&sdma 19>,
640 <&sdma 20>;
641 dma-names = "tx", "rx";
642 status = "disabled";
643 };
644
645 mcbsp4: mcbsp@48096000 {
646 compatible = "ti,omap4-mcbsp";
647 reg = <0x48096000 0xff>; /* L4 Interconnect */
648 reg-names = "mpu";
649 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
650 interrupt-names = "common";
651 ti,buffer-size = <128>;
652 ti,hwmods = "mcbsp4";
653 dmas = <&sdma 31>,
654 <&sdma 32>;
655 dma-names = "tx", "rx";
656 status = "disabled";
657 };
658
659 keypad: keypad@4a31c000 {
660 compatible = "ti,omap4-keypad";
661 reg = <0x4a31c000 0x80>;
662 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
663 reg-names = "mpu";
664 ti,hwmods = "kbd";
665 };
666
667 dmm@4e000000 {
668 compatible = "ti,omap4-dmm";
669 reg = <0x4e000000 0x800>;
670 interrupts = <0 113 0x4>;
671 ti,hwmods = "dmm";
672 };
673
674 emif1: emif@4c000000 {
675 compatible = "ti,emif-4d";
676 reg = <0x4c000000 0x100>;
677 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
678 ti,hwmods = "emif1";
679 ti,no-idle-on-init;
680 phy-type = <1>;
681 hw-caps-read-idle-ctrl;
682 hw-caps-ll-interface;
683 hw-caps-temp-alert;
684 };
685
686 emif2: emif@4d000000 {
687 compatible = "ti,emif-4d";
688 reg = <0x4d000000 0x100>;
689 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
690 ti,hwmods = "emif2";
691 ti,no-idle-on-init;
692 phy-type = <1>;
693 hw-caps-read-idle-ctrl;
694 hw-caps-ll-interface;
695 hw-caps-temp-alert;
696 };
697
698 ocp2scp@4a0ad000 {
699 compatible = "ti,omap-ocp2scp";
700 reg = <0x4a0ad000 0x1f>;
701 #address-cells = <1>;
702 #size-cells = <1>;
703 ranges;
704 ti,hwmods = "ocp2scp_usb_phy";
705 usb2_phy: usb2phy@4a0ad080 {
706 compatible = "ti,omap-usb2";
707 reg = <0x4a0ad080 0x58>;
708 ctrl-module = <&omap_control_usb2phy>;
709 clocks = <&usb_phy_cm_clk32k>;
710 clock-names = "wkupclk";
711 #phy-cells = <0>;
712 };
713 };
714
715 mailbox: mailbox@4a0f4000 {
716 compatible = "ti,omap4-mailbox";
717 reg = <0x4a0f4000 0x200>;
718 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
719 ti,hwmods = "mailbox";
720 #mbox-cells = <1>;
721 ti,mbox-num-users = <3>;
722 ti,mbox-num-fifos = <8>;
723 mbox_ipu: mbox_ipu {
724 ti,mbox-tx = <0 0 0>;
725 ti,mbox-rx = <1 0 0>;
726 };
727 mbox_dsp: mbox_dsp {
728 ti,mbox-tx = <3 0 0>;
729 ti,mbox-rx = <2 0 0>;
730 };
731 };
732
733 timer1: timer@4a318000 {
734 compatible = "ti,omap3430-timer";
735 reg = <0x4a318000 0x80>;
736 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
737 ti,hwmods = "timer1";
738 ti,timer-alwon;
739 };
740
741 timer2: timer@48032000 {
742 compatible = "ti,omap3430-timer";
743 reg = <0x48032000 0x80>;
744 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
745 ti,hwmods = "timer2";
746 };
747
748 timer3: timer@48034000 {
749 compatible = "ti,omap4430-timer";
750 reg = <0x48034000 0x80>;
751 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
752 ti,hwmods = "timer3";
753 };
754
755 timer4: timer@48036000 {
756 compatible = "ti,omap4430-timer";
757 reg = <0x48036000 0x80>;
758 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
759 ti,hwmods = "timer4";
760 };
761
762 timer5: timer@40138000 {
763 compatible = "ti,omap4430-timer";
764 reg = <0x40138000 0x80>,
765 <0x49038000 0x80>;
766 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
767 ti,hwmods = "timer5";
768 ti,timer-dsp;
769 };
770
771 timer6: timer@4013a000 {
772 compatible = "ti,omap4430-timer";
773 reg = <0x4013a000 0x80>,
774 <0x4903a000 0x80>;
775 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
776 ti,hwmods = "timer6";
777 ti,timer-dsp;
778 };
779
780 timer7: timer@4013c000 {
781 compatible = "ti,omap4430-timer";
782 reg = <0x4013c000 0x80>,
783 <0x4903c000 0x80>;
784 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
785 ti,hwmods = "timer7";
786 ti,timer-dsp;
787 };
788
789 timer8: timer@4013e000 {
790 compatible = "ti,omap4430-timer";
791 reg = <0x4013e000 0x80>,
792 <0x4903e000 0x80>;
793 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
794 ti,hwmods = "timer8";
795 ti,timer-pwm;
796 ti,timer-dsp;
797 };
798
799 timer9: timer@4803e000 {
800 compatible = "ti,omap4430-timer";
801 reg = <0x4803e000 0x80>;
802 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
803 ti,hwmods = "timer9";
804 ti,timer-pwm;
805 };
806
807 timer10: timer@48086000 {
808 compatible = "ti,omap3430-timer";
809 reg = <0x48086000 0x80>;
810 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
811 ti,hwmods = "timer10";
812 ti,timer-pwm;
813 };
814
815 timer11: timer@48088000 {
816 compatible = "ti,omap4430-timer";
817 reg = <0x48088000 0x80>;
818 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
819 ti,hwmods = "timer11";
820 ti,timer-pwm;
821 };
822
823 usbhstll: usbhstll@4a062000 {
824 compatible = "ti,usbhs-tll";
825 reg = <0x4a062000 0x1000>;
826 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
827 ti,hwmods = "usb_tll_hs";
828 };
829
830 usbhshost: usbhshost@4a064000 {
831 compatible = "ti,usbhs-host";
832 reg = <0x4a064000 0x800>;
833 ti,hwmods = "usb_host_hs";
834 #address-cells = <1>;
835 #size-cells = <1>;
836 ranges;
837 clocks = <&init_60m_fclk>,
838 <&xclk60mhsp1_ck>,
839 <&xclk60mhsp2_ck>;
840 clock-names = "refclk_60m_int",
841 "refclk_60m_ext_p1",
842 "refclk_60m_ext_p2";
843
844 usbhsohci: ohci@4a064800 {
845 compatible = "ti,ohci-omap3";
846 reg = <0x4a064800 0x400>;
847 interrupt-parent = <&gic>;
848 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
849 };
850
851 usbhsehci: ehci@4a064c00 {
852 compatible = "ti,ehci-omap";
853 reg = <0x4a064c00 0x400>;
854 interrupt-parent = <&gic>;
855 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
856 };
857 };
858
859 omap_control_usb2phy: control-phy@4a002300 {
860 compatible = "ti,control-phy-usb2";
861 reg = <0x4a002300 0x4>;
862 reg-names = "power";
863 };
864
865 omap_control_usbotg: control-phy@4a00233c {
866 compatible = "ti,control-phy-otghs";
867 reg = <0x4a00233c 0x4>;
868 reg-names = "otghs_control";
869 };
870
871 usb_otg_hs: usb_otg_hs@4a0ab000 {
872 compatible = "ti,omap4-musb";
873 reg = <0x4a0ab000 0x7ff>;
874 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
875 interrupt-names = "mc", "dma";
876 ti,hwmods = "usb_otg_hs";
877 usb-phy = <&usb2_phy>;
878 phys = <&usb2_phy>;
879 phy-names = "usb2-phy";
880 multipoint = <1>;
881 num-eps = <16>;
882 ram-bits = <12>;
883 ctrl-module = <&omap_control_usbotg>;
884 };
885
886 aes: aes@4b501000 {
887 compatible = "ti,omap4-aes";
888 ti,hwmods = "aes";
889 reg = <0x4b501000 0xa0>;
890 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
891 dmas = <&sdma 111>, <&sdma 110>;
892 dma-names = "tx", "rx";
893 };
894
895 des: des@480a5000 {
896 compatible = "ti,omap4-des";
897 ti,hwmods = "des";
898 reg = <0x480a5000 0xa0>;
899 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
900 dmas = <&sdma 117>, <&sdma 116>;
901 dma-names = "tx", "rx";
902 };
903
904 abb_mpu: regulator-abb-mpu {
905 compatible = "ti,abb-v2";
906 regulator-name = "abb_mpu";
907 #address-cells = <0>;
908 #size-cells = <0>;
909 ti,tranxdone-status-mask = <0x80>;
910 clocks = <&sys_clkin_ck>;
911 ti,settling-time = <50>;
912 ti,clock-cycles = <16>;
913
914 status = "disabled";
915 };
916
917 abb_iva: regulator-abb-iva {
918 compatible = "ti,abb-v2";
919 regulator-name = "abb_iva";
920 #address-cells = <0>;
921 #size-cells = <0>;
922 ti,tranxdone-status-mask = <0x80000000>;
923 clocks = <&sys_clkin_ck>;
924 ti,settling-time = <50>;
925 ti,clock-cycles = <16>;
926
927 status = "disabled";
928 };
929
930 dss: dss@58000000 {
931 compatible = "ti,omap4-dss";
932 reg = <0x58000000 0x80>;
933 status = "disabled";
934 ti,hwmods = "dss_core";
935 clocks = <&dss_dss_clk>;
936 clock-names = "fck";
937 #address-cells = <1>;
938 #size-cells = <1>;
939 ranges;
940
941 dispc@58001000 {
942 compatible = "ti,omap4-dispc";
943 reg = <0x58001000 0x1000>;
944 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
945 ti,hwmods = "dss_dispc";
946 clocks = <&dss_dss_clk>;
947 clock-names = "fck";
948 };
949
950 rfbi: encoder@58002000 {
951 compatible = "ti,omap4-rfbi";
952 reg = <0x58002000 0x1000>;
953 status = "disabled";
954 ti,hwmods = "dss_rfbi";
955 clocks = <&dss_dss_clk>, <&l3_div_ck>;
956 clock-names = "fck", "ick";
957 };
958
959 venc: encoder@58003000 {
960 compatible = "ti,omap4-venc";
961 reg = <0x58003000 0x1000>;
962 status = "disabled";
963 ti,hwmods = "dss_venc";
964 clocks = <&dss_tv_clk>;
965 clock-names = "fck";
966 };
967
968 dsi1: encoder@58004000 {
969 compatible = "ti,omap4-dsi";
970 reg = <0x58004000 0x200>,
971 <0x58004200 0x40>,
972 <0x58004300 0x20>;
973 reg-names = "proto", "phy", "pll";
974 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
975 status = "disabled";
976 ti,hwmods = "dss_dsi1";
977 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
978 clock-names = "fck", "sys_clk";
979 };
980
981 dsi2: encoder@58005000 {
982 compatible = "ti,omap4-dsi";
983 reg = <0x58005000 0x200>,
984 <0x58005200 0x40>,
985 <0x58005300 0x20>;
986 reg-names = "proto", "phy", "pll";
987 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
988 status = "disabled";
989 ti,hwmods = "dss_dsi2";
990 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
991 clock-names = "fck", "sys_clk";
992 };
993
994 hdmi: encoder@58006000 {
995 compatible = "ti,omap4-hdmi";
996 reg = <0x58006000 0x200>,
997 <0x58006200 0x100>,
998 <0x58006300 0x100>,
999 <0x58006400 0x1000>;
1000 reg-names = "wp", "pll", "phy", "core";
1001 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1002 status = "disabled";
1003 ti,hwmods = "dss_hdmi";
1004 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
1005 clock-names = "fck", "sys_clk";
1006 dmas = <&sdma 76>;
1007 dma-names = "audio_tx";
1008 };
1009 };
1010 };
1011 };
1012
1013 /include/ "omap44xx-clocks.dtsi"
Linux kernel - Deliverables
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