2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #include "skeleton.dtsi"
12 compatible = "ti,omap4430", "ti,omap4";
13 interrupt-parent = <&gic>;
24 compatible = "arm,cortex-a9";
25 next-level-cache = <&L2>;
28 compatible = "arm,cortex-a9";
29 next-level-cache = <&L2>;
33 gic: interrupt-controller@48241000 {
34 compatible = "arm,cortex-a9-gic";
36 #interrupt-cells = <3>;
37 reg = <0x48241000 0x1000>,
41 L2: l2-cache-controller@48242000 {
42 compatible = "arm,pl310-cache";
43 reg = <0x48242000 0x1000>;
48 local-timer@0x48240600 {
49 compatible = "arm,cortex-a9-twd-timer";
50 reg = <0x48240600 0x20>;
51 interrupts = <1 13 0x304>;
55 * The soc node represents the soc top level view. It is uses for IPs
56 * that are not memory mapped in the MPU view or for the MPU itself.
59 compatible = "ti,omap-infra";
61 compatible = "ti,omap4-mpu";
66 compatible = "ti,omap3-c64";
71 compatible = "ti,ivahd";
77 * XXX: Use a flat representation of the OMAP4 interconnect.
78 * The real OMAP interconnect network is quite complex.
79 * Since that will not bring real advantage to represent that in DT for
80 * the moment, just use a fake OCP bus entry to represent the whole bus
84 compatible = "ti,omap4-l3-noc", "simple-bus";
88 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
89 reg = <0x44000000 0x1000>,
92 interrupts = <0 9 0x4>,
95 counter32k: counter@4a304000 {
96 compatible = "ti,omap-counter32k";
97 reg = <0x4a304000 0x20>;
98 ti,hwmods = "counter_32k";
101 omap4_pmx_core: pinmux@4a100040 {
102 compatible = "ti,omap4-padconf", "pinctrl-single";
103 reg = <0x4a100040 0x0196>;
104 #address-cells = <1>;
106 pinctrl-single,register-width = <16>;
107 pinctrl-single,function-mask = <0x7fff>;
109 omap4_pmx_wkup: pinmux@4a31e040 {
110 compatible = "ti,omap4-padconf", "pinctrl-single";
111 reg = <0x4a31e040 0x0038>;
112 #address-cells = <1>;
114 pinctrl-single,register-width = <16>;
115 pinctrl-single,function-mask = <0x7fff>;
118 sdma: dma-controller@4a056000 {
119 compatible = "ti,omap4430-sdma";
120 reg = <0x4a056000 0x1000>;
121 interrupts = <0 12 0x4>,
126 #dma-channels = <32>;
127 #dma-requests = <127>;
130 gpio1: gpio@4a310000 {
131 compatible = "ti,omap4-gpio";
132 reg = <0x4a310000 0x200>;
133 interrupts = <0 29 0x4>;
138 interrupt-controller;
139 #interrupt-cells = <2>;
142 gpio2: gpio@48055000 {
143 compatible = "ti,omap4-gpio";
144 reg = <0x48055000 0x200>;
145 interrupts = <0 30 0x4>;
149 interrupt-controller;
150 #interrupt-cells = <2>;
153 gpio3: gpio@48057000 {
154 compatible = "ti,omap4-gpio";
155 reg = <0x48057000 0x200>;
156 interrupts = <0 31 0x4>;
160 interrupt-controller;
161 #interrupt-cells = <2>;
164 gpio4: gpio@48059000 {
165 compatible = "ti,omap4-gpio";
166 reg = <0x48059000 0x200>;
167 interrupts = <0 32 0x4>;
171 interrupt-controller;
172 #interrupt-cells = <2>;
175 gpio5: gpio@4805b000 {
176 compatible = "ti,omap4-gpio";
177 reg = <0x4805b000 0x200>;
178 interrupts = <0 33 0x4>;
182 interrupt-controller;
183 #interrupt-cells = <2>;
186 gpio6: gpio@4805d000 {
187 compatible = "ti,omap4-gpio";
188 reg = <0x4805d000 0x200>;
189 interrupts = <0 34 0x4>;
193 interrupt-controller;
194 #interrupt-cells = <2>;
197 gpmc: gpmc@50000000 {
198 compatible = "ti,omap4430-gpmc";
199 reg = <0x50000000 0x1000>;
200 #address-cells = <2>;
202 interrupts = <0 20 0x4>;
204 gpmc,num-waitpins = <4>;
208 uart1: serial@4806a000 {
209 compatible = "ti,omap4-uart";
210 reg = <0x4806a000 0x100>;
211 interrupts = <0 72 0x4>;
213 clock-frequency = <48000000>;
216 uart2: serial@4806c000 {
217 compatible = "ti,omap4-uart";
218 reg = <0x4806c000 0x100>;
219 interrupts = <0 73 0x4>;
221 clock-frequency = <48000000>;
224 uart3: serial@48020000 {
225 compatible = "ti,omap4-uart";
226 reg = <0x48020000 0x100>;
227 interrupts = <0 74 0x4>;
229 clock-frequency = <48000000>;
232 uart4: serial@4806e000 {
233 compatible = "ti,omap4-uart";
234 reg = <0x4806e000 0x100>;
235 interrupts = <0 70 0x4>;
237 clock-frequency = <48000000>;
241 compatible = "ti,omap4-i2c";
242 reg = <0x48070000 0x100>;
243 interrupts = <0 56 0x4>;
244 #address-cells = <1>;
250 compatible = "ti,omap4-i2c";
251 reg = <0x48072000 0x100>;
252 interrupts = <0 57 0x4>;
253 #address-cells = <1>;
259 compatible = "ti,omap4-i2c";
260 reg = <0x48060000 0x100>;
261 interrupts = <0 61 0x4>;
262 #address-cells = <1>;
268 compatible = "ti,omap4-i2c";
269 reg = <0x48350000 0x100>;
270 interrupts = <0 62 0x4>;
271 #address-cells = <1>;
276 mcspi1: spi@48098000 {
277 compatible = "ti,omap4-mcspi";
278 reg = <0x48098000 0x200>;
279 interrupts = <0 65 0x4>;
280 #address-cells = <1>;
282 ti,hwmods = "mcspi1";
292 dma-names = "tx0", "rx0", "tx1", "rx1",
293 "tx2", "rx2", "tx3", "rx3";
296 mcspi2: spi@4809a000 {
297 compatible = "ti,omap4-mcspi";
298 reg = <0x4809a000 0x200>;
299 interrupts = <0 66 0x4>;
300 #address-cells = <1>;
302 ti,hwmods = "mcspi2";
308 dma-names = "tx0", "rx0", "tx1", "rx1";
311 mcspi3: spi@480b8000 {
312 compatible = "ti,omap4-mcspi";
313 reg = <0x480b8000 0x200>;
314 interrupts = <0 91 0x4>;
315 #address-cells = <1>;
317 ti,hwmods = "mcspi3";
319 dmas = <&sdma 15>, <&sdma 16>;
320 dma-names = "tx0", "rx0";
323 mcspi4: spi@480ba000 {
324 compatible = "ti,omap4-mcspi";
325 reg = <0x480ba000 0x200>;
326 interrupts = <0 48 0x4>;
327 #address-cells = <1>;
329 ti,hwmods = "mcspi4";
331 dmas = <&sdma 70>, <&sdma 71>;
332 dma-names = "tx0", "rx0";
336 compatible = "ti,omap4-hsmmc";
337 reg = <0x4809c000 0x400>;
338 interrupts = <0 83 0x4>;
341 ti,needs-special-reset;
342 dmas = <&sdma 61>, <&sdma 62>;
343 dma-names = "tx", "rx";
347 compatible = "ti,omap4-hsmmc";
348 reg = <0x480b4000 0x400>;
349 interrupts = <0 86 0x4>;
351 ti,needs-special-reset;
352 dmas = <&sdma 47>, <&sdma 48>;
353 dma-names = "tx", "rx";
357 compatible = "ti,omap4-hsmmc";
358 reg = <0x480ad000 0x400>;
359 interrupts = <0 94 0x4>;
361 ti,needs-special-reset;
362 dmas = <&sdma 77>, <&sdma 78>;
363 dma-names = "tx", "rx";
367 compatible = "ti,omap4-hsmmc";
368 reg = <0x480d1000 0x400>;
369 interrupts = <0 96 0x4>;
371 ti,needs-special-reset;
372 dmas = <&sdma 57>, <&sdma 58>;
373 dma-names = "tx", "rx";
377 compatible = "ti,omap4-hsmmc";
378 reg = <0x480d5000 0x400>;
379 interrupts = <0 59 0x4>;
381 ti,needs-special-reset;
382 dmas = <&sdma 59>, <&sdma 60>;
383 dma-names = "tx", "rx";
387 compatible = "ti,omap4-wdt", "ti,omap3-wdt";
388 reg = <0x4a314000 0x80>;
389 interrupts = <0 80 0x4>;
390 ti,hwmods = "wd_timer2";
393 mcpdm: mcpdm@40132000 {
394 compatible = "ti,omap4-mcpdm";
395 reg = <0x40132000 0x7f>, /* MPU private access */
396 <0x49032000 0x7f>; /* L3 Interconnect */
397 reg-names = "mpu", "dma";
398 interrupts = <0 112 0x4>;
402 dma-names = "up_link", "dn_link";
405 dmic: dmic@4012e000 {
406 compatible = "ti,omap4-dmic";
407 reg = <0x4012e000 0x7f>, /* MPU private access */
408 <0x4902e000 0x7f>; /* L3 Interconnect */
409 reg-names = "mpu", "dma";
410 interrupts = <0 114 0x4>;
413 dma-names = "up_link";
416 mcbsp1: mcbsp@40122000 {
417 compatible = "ti,omap4-mcbsp";
418 reg = <0x40122000 0xff>, /* MPU private access */
419 <0x49022000 0xff>; /* L3 Interconnect */
420 reg-names = "mpu", "dma";
421 interrupts = <0 17 0x4>;
422 interrupt-names = "common";
423 ti,buffer-size = <128>;
424 ti,hwmods = "mcbsp1";
427 dma-names = "tx", "rx";
430 mcbsp2: mcbsp@40124000 {
431 compatible = "ti,omap4-mcbsp";
432 reg = <0x40124000 0xff>, /* MPU private access */
433 <0x49024000 0xff>; /* L3 Interconnect */
434 reg-names = "mpu", "dma";
435 interrupts = <0 22 0x4>;
436 interrupt-names = "common";
437 ti,buffer-size = <128>;
438 ti,hwmods = "mcbsp2";
441 dma-names = "tx", "rx";
444 mcbsp3: mcbsp@40126000 {
445 compatible = "ti,omap4-mcbsp";
446 reg = <0x40126000 0xff>, /* MPU private access */
447 <0x49026000 0xff>; /* L3 Interconnect */
448 reg-names = "mpu", "dma";
449 interrupts = <0 23 0x4>;
450 interrupt-names = "common";
451 ti,buffer-size = <128>;
452 ti,hwmods = "mcbsp3";
455 dma-names = "tx", "rx";
458 mcbsp4: mcbsp@48096000 {
459 compatible = "ti,omap4-mcbsp";
460 reg = <0x48096000 0xff>; /* L4 Interconnect */
462 interrupts = <0 16 0x4>;
463 interrupt-names = "common";
464 ti,buffer-size = <128>;
465 ti,hwmods = "mcbsp4";
468 dma-names = "tx", "rx";
471 keypad: keypad@4a31c000 {
472 compatible = "ti,omap4-keypad";
473 reg = <0x4a31c000 0x80>;
474 interrupts = <0 120 0x4>;
479 emif1: emif@4c000000 {
480 compatible = "ti,emif-4d";
481 reg = <0x4c000000 0x100>;
482 interrupts = <0 110 0x4>;
485 hw-caps-read-idle-ctrl;
486 hw-caps-ll-interface;
490 emif2: emif@4d000000 {
491 compatible = "ti,emif-4d";
492 reg = <0x4d000000 0x100>;
493 interrupts = <0 111 0x4>;
496 hw-caps-read-idle-ctrl;
497 hw-caps-ll-interface;
502 compatible = "ti,omap-ocp2scp";
503 reg = <0x4a0ad000 0x1f>;
504 #address-cells = <1>;
507 ti,hwmods = "ocp2scp_usb_phy";
508 usb2_phy: usb2phy@4a0ad080 {
509 compatible = "ti,omap-usb2";
510 reg = <0x4a0ad080 0x58>;
511 ctrl-module = <&omap_control_usb>;
515 timer1: timer@4a318000 {
516 compatible = "ti,omap3430-timer";
517 reg = <0x4a318000 0x80>;
518 interrupts = <0 37 0x4>;
519 ti,hwmods = "timer1";
523 timer2: timer@48032000 {
524 compatible = "ti,omap3430-timer";
525 reg = <0x48032000 0x80>;
526 interrupts = <0 38 0x4>;
527 ti,hwmods = "timer2";
530 timer3: timer@48034000 {
531 compatible = "ti,omap4430-timer";
532 reg = <0x48034000 0x80>;
533 interrupts = <0 39 0x4>;
534 ti,hwmods = "timer3";
537 timer4: timer@48036000 {
538 compatible = "ti,omap4430-timer";
539 reg = <0x48036000 0x80>;
540 interrupts = <0 40 0x4>;
541 ti,hwmods = "timer4";
544 timer5: timer@40138000 {
545 compatible = "ti,omap4430-timer";
546 reg = <0x40138000 0x80>,
548 interrupts = <0 41 0x4>;
549 ti,hwmods = "timer5";
553 timer6: timer@4013a000 {
554 compatible = "ti,omap4430-timer";
555 reg = <0x4013a000 0x80>,
557 interrupts = <0 42 0x4>;
558 ti,hwmods = "timer6";
562 timer7: timer@4013c000 {
563 compatible = "ti,omap4430-timer";
564 reg = <0x4013c000 0x80>,
566 interrupts = <0 43 0x4>;
567 ti,hwmods = "timer7";
571 timer8: timer@4013e000 {
572 compatible = "ti,omap4430-timer";
573 reg = <0x4013e000 0x80>,
575 interrupts = <0 44 0x4>;
576 ti,hwmods = "timer8";
581 timer9: timer@4803e000 {
582 compatible = "ti,omap4430-timer";
583 reg = <0x4803e000 0x80>;
584 interrupts = <0 45 0x4>;
585 ti,hwmods = "timer9";
589 timer10: timer@48086000 {
590 compatible = "ti,omap3430-timer";
591 reg = <0x48086000 0x80>;
592 interrupts = <0 46 0x4>;
593 ti,hwmods = "timer10";
597 timer11: timer@48088000 {
598 compatible = "ti,omap4430-timer";
599 reg = <0x48088000 0x80>;
600 interrupts = <0 47 0x4>;
601 ti,hwmods = "timer11";
605 usbhstll: usbhstll@4a062000 {
606 compatible = "ti,usbhs-tll";
607 reg = <0x4a062000 0x1000>;
608 interrupts = <0 78 0x4>;
609 ti,hwmods = "usb_tll_hs";
612 usbhshost: usbhshost@4a064000 {
613 compatible = "ti,usbhs-host";
614 reg = <0x4a064000 0x800>;
615 ti,hwmods = "usb_host_hs";
616 #address-cells = <1>;
620 usbhsohci: ohci@4a064800 {
621 compatible = "ti,ohci-omap3", "usb-ohci";
622 reg = <0x4a064800 0x400>;
623 interrupt-parent = <&gic>;
624 interrupts = <0 76 0x4>;
627 usbhsehci: ehci@4a064c00 {
628 compatible = "ti,ehci-omap", "usb-ehci";
629 reg = <0x4a064c00 0x400>;
630 interrupt-parent = <&gic>;
631 interrupts = <0 77 0x4>;
635 omap_control_usb: omap-control-usb@4a002300 {
636 compatible = "ti,omap-control-usb";
637 reg = <0x4a002300 0x4>,
639 reg-names = "control_dev_conf", "otghs_control";
643 usb_otg_hs: usb_otg_hs@4a0ab000 {
644 compatible = "ti,omap4-musb";
645 reg = <0x4a0ab000 0x7ff>;
646 interrupts = <0 92 0x4>, <0 93 0x4>;
647 interrupt-names = "mc", "dma";
648 ti,hwmods = "usb_otg_hs";
649 usb-phy = <&usb2_phy>;