arch/arm/boot/dts/omap4.dtsi

   1 /*
   2  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /*
  10  * Carveout for multimedia usecases
  11  * It should be the last 48MB of the first 512MB memory part
  12  * In theory, it should not even exist. That zone should be reserved
  13  * dynamically during the .reserve callback.
  14  */
  15 /memreserve/ 0x9d000000 0x03000000;
  16
  17 /include/ "skeleton.dtsi"
  18
  19 / {
  20         compatible = "ti,omap4430", "ti,omap4";
  21         interrupt-parent = <&gic>;
  22
  23         aliases {
  24                 serial0 = &uart1;
  25                 serial1 = &uart2;
  26                 serial2 = &uart3;
  27                 serial3 = &uart4;
  28         };
  29
  30         cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33
  34                 cpu@0 {
  35                         compatible = "arm,cortex-a9";
  36                         device_type = "cpu";
  37                         next-level-cache = <&L2>;
  38                         reg = <0x0>;
  39                 };
  40                 cpu@1 {
  41                         compatible = "arm,cortex-a9";
  42                         device_type = "cpu";
  43                         next-level-cache = <&L2>;
  44                         reg = <0x1>;
  45                 };
  46         };
  47
  48         gic: interrupt-controller@48241000 {
  49                 compatible = "arm,cortex-a9-gic";
  50                 interrupt-controller;
  51                 #interrupt-cells = <3>;
  52                 reg = <0x48241000 0x1000>,
  53                       <0x48240100 0x0100>;
  54         };
  55
  56         L2: l2-cache-controller@48242000 {
  57                 compatible = "arm,pl310-cache";
  58                 reg = <0x48242000 0x1000>;
  59                 cache-unified;
  60                 cache-level = <2>;
  61         };
  62
  63         local-timer@0x48240600 {
  64                 compatible = "arm,cortex-a9-twd-timer";
  65                 reg = <0x48240600 0x20>;
  66                 interrupts = <1 13 0x304>;
  67         };
  68
  69         /*
  70          * The soc node represents the soc top level view. It is uses for IPs
  71          * that are not memory mapped in the MPU view or for the MPU itself.
  72          */
  73         soc {
  74                 compatible = "ti,omap-infra";
  75                 mpu {
  76                         compatible = "ti,omap4-mpu";
  77                         ti,hwmods = "mpu";
  78                 };
  79
  80                 dsp {
  81                         compatible = "ti,omap3-c64";
  82                         ti,hwmods = "dsp";
  83                 };
  84
  85                 iva {
  86                         compatible = "ti,ivahd";
  87                         ti,hwmods = "iva";
  88                 };
  89         };
  90
  91         /*
  92          * XXX: Use a flat representation of the OMAP4 interconnect.
  93          * The real OMAP interconnect network is quite complex.
  94          * Since that will not bring real advantage to represent that in DT for
  95          * the moment, just use a fake OCP bus entry to represent the whole bus
  96          * hierarchy.
  97          */
  98         ocp {
  99                 compatible = "ti,omap4-l3-noc", "simple-bus";
 100                 #address-cells = <1>;
 101                 #size-cells = <1>;
 102                 ranges;
 103                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
 104                 reg = <0x44000000 0x1000>,
 105                       <0x44800000 0x2000>,
 106                       <0x45000000 0x1000>;
 107                 interrupts = <0 9 0x4>,
 108                              <0 10 0x4>;
 109
 110                 counter32k: counter@4a304000 {
 111                         compatible = "ti,omap-counter32k";
 112                         reg = <0x4a304000 0x20>;
 113                         ti,hwmods = "counter_32k";
 114                 };
 115
 116                 omap4_pmx_core: pinmux@4a100040 {
 117                         compatible = "ti,omap4-padconf", "pinctrl-single";
 118                         reg = <0x4a100040 0x0196>;
 119                         #address-cells = <1>;
 120                         #size-cells = <0>;
 121                         pinctrl-single,register-width = <16>;
 122                         pinctrl-single,function-mask = <0x7fff>;
 123                 };
 124                 omap4_pmx_wkup: pinmux@4a31e040 {
 125                         compatible = "ti,omap4-padconf", "pinctrl-single";
 126                         reg = <0x4a31e040 0x0038>;
 127                         #address-cells = <1>;
 128                         #size-cells = <0>;
 129                         pinctrl-single,register-width = <16>;
 130                         pinctrl-single,function-mask = <0x7fff>;
 131                 };
 132
 133                 sdma: dma-controller@4a056000 {
 134                         compatible = "ti,omap4430-sdma";
 135                         reg = <0x4a056000 0x1000>;
 136                         interrupts = <0 12 0x4>,
 137                                      <0 13 0x4>,
 138                                      <0 14 0x4>,
 139                                      <0 15 0x4>;
 140                         #dma-cells = <1>;
 141                         #dma-channels = <32>;
 142                         #dma-requests = <127>;
 143                 };
 144
 145                 gpio1: gpio@4a310000 {
 146                         compatible = "ti,omap4-gpio";
 147                         reg = <0x4a310000 0x200>;
 148                         interrupts = <0 29 0x4>;
 149                         ti,hwmods = "gpio1";
 150                         ti,gpio-always-on;
 151                         gpio-controller;
 152                         #gpio-cells = <2>;
 153                         interrupt-controller;
 154                         #interrupt-cells = <2>;
 155                 };
 156
 157                 gpio2: gpio@48055000 {
 158                         compatible = "ti,omap4-gpio";
 159                         reg = <0x48055000 0x200>;
 160                         interrupts = <0 30 0x4>;
 161                         ti,hwmods = "gpio2";
 162                         gpio-controller;
 163                         #gpio-cells = <2>;
 164                         interrupt-controller;
 165                         #interrupt-cells = <2>;
 166                 };
 167
 168                 gpio3: gpio@48057000 {
 169                         compatible = "ti,omap4-gpio";
 170                         reg = <0x48057000 0x200>;
 171                         interrupts = <0 31 0x4>;
 172                         ti,hwmods = "gpio3";
 173                         gpio-controller;
 174                         #gpio-cells = <2>;
 175                         interrupt-controller;
 176                         #interrupt-cells = <2>;
 177                 };
 178
 179                 gpio4: gpio@48059000 {
 180                         compatible = "ti,omap4-gpio";
 181                         reg = <0x48059000 0x200>;
 182                         interrupts = <0 32 0x4>;
 183                         ti,hwmods = "gpio4";
 184                         gpio-controller;
 185                         #gpio-cells = <2>;
 186                         interrupt-controller;
 187                         #interrupt-cells = <2>;
 188                 };
 189
 190                 gpio5: gpio@4805b000 {
 191                         compatible = "ti,omap4-gpio";
 192                         reg = <0x4805b000 0x200>;
 193                         interrupts = <0 33 0x4>;
 194                         ti,hwmods = "gpio5";
 195                         gpio-controller;
 196                         #gpio-cells = <2>;
 197                         interrupt-controller;
 198                         #interrupt-cells = <2>;
 199                 };
 200
 201                 gpio6: gpio@4805d000 {
 202                         compatible = "ti,omap4-gpio";
 203                         reg = <0x4805d000 0x200>;
 204                         interrupts = <0 34 0x4>;
 205                         ti,hwmods = "gpio6";
 206                         gpio-controller;
 207                         #gpio-cells = <2>;
 208                         interrupt-controller;
 209                         #interrupt-cells = <2>;
 210                 };
 211
 212                 gpmc: gpmc@50000000 {
 213                         compatible = "ti,omap4430-gpmc";
 214                         reg = <0x50000000 0x1000>;
 215                         #address-cells = <2>;
 216                         #size-cells = <1>;
 217                         interrupts = <0 20 0x4>;
 218                         gpmc,num-cs = <8>;
 219                         gpmc,num-waitpins = <4>;
 220                         ti,hwmods = "gpmc";
 221                 };
 222
 223                 uart1: serial@4806a000 {
 224                         compatible = "ti,omap4-uart";
 225                         reg = <0x4806a000 0x100>;
 226                         interrupts = <0 72 0x4>;
 227                         ti,hwmods = "uart1";
 228                         clock-frequency = <48000000>;
 229                 };
 230
 231                 uart2: serial@4806c000 {
 232                         compatible = "ti,omap4-uart";
 233                         reg = <0x4806c000 0x100>;
 234                         interrupts = <0 73 0x4>;
 235                         ti,hwmods = "uart2";
 236                         clock-frequency = <48000000>;
 237                 };
 238
 239                 uart3: serial@48020000 {
 240                         compatible = "ti,omap4-uart";
 241                         reg = <0x48020000 0x100>;
 242                         interrupts = <0 74 0x4>;
 243                         ti,hwmods = "uart3";
 244                         clock-frequency = <48000000>;
 245                 };
 246
 247                 uart4: serial@4806e000 {
 248                         compatible = "ti,omap4-uart";
 249                         reg = <0x4806e000 0x100>;
 250                         interrupts = <0 70 0x4>;
 251                         ti,hwmods = "uart4";
 252                         clock-frequency = <48000000>;
 253                 };
 254
 255                 i2c1: i2c@48070000 {
 256                         compatible = "ti,omap4-i2c";
 257                         reg = <0x48070000 0x100>;
 258                         interrupts = <0 56 0x4>;
 259                         #address-cells = <1>;
 260                         #size-cells = <0>;
 261                         ti,hwmods = "i2c1";
 262                 };
 263
 264                 i2c2: i2c@48072000 {
 265                         compatible = "ti,omap4-i2c";
 266                         reg = <0x48072000 0x100>;
 267                         interrupts = <0 57 0x4>;
 268                         #address-cells = <1>;
 269                         #size-cells = <0>;
 270                         ti,hwmods = "i2c2";
 271                 };
 272
 273                 i2c3: i2c@48060000 {
 274                         compatible = "ti,omap4-i2c";
 275                         reg = <0x48060000 0x100>;
 276                         interrupts = <0 61 0x4>;
 277                         #address-cells = <1>;
 278                         #size-cells = <0>;
 279                         ti,hwmods = "i2c3";
 280                 };
 281
 282                 i2c4: i2c@48350000 {
 283                         compatible = "ti,omap4-i2c";
 284                         reg = <0x48350000 0x100>;
 285                         interrupts = <0 62 0x4>;
 286                         #address-cells = <1>;
 287                         #size-cells = <0>;
 288                         ti,hwmods = "i2c4";
 289                 };
 290
 291                 mcspi1: spi@48098000 {
 292                         compatible = "ti,omap4-mcspi";
 293                         reg = <0x48098000 0x200>;
 294                         interrupts = <0 65 0x4>;
 295                         #address-cells = <1>;
 296                         #size-cells = <0>;
 297                         ti,hwmods = "mcspi1";
 298                         ti,spi-num-cs = <4>;
 299                         dmas = <&sdma 35>,
 300                                <&sdma 36>,
 301                                <&sdma 37>,
 302                                <&sdma 38>,
 303                                <&sdma 39>,
 304                                <&sdma 40>,
 305                                <&sdma 41>,
 306                                <&sdma 42>;
 307                         dma-names = "tx0", "rx0", "tx1", "rx1",
 308                                     "tx2", "rx2", "tx3", "rx3";
 309                 };
 310
 311                 mcspi2: spi@4809a000 {
 312                         compatible = "ti,omap4-mcspi";
 313                         reg = <0x4809a000 0x200>;
 314                         interrupts = <0 66 0x4>;
 315                         #address-cells = <1>;
 316                         #size-cells = <0>;
 317                         ti,hwmods = "mcspi2";
 318                         ti,spi-num-cs = <2>;
 319                         dmas = <&sdma 43>,
 320                                <&sdma 44>,
 321                                <&sdma 45>,
 322                                <&sdma 46>;
 323                         dma-names = "tx0", "rx0", "tx1", "rx1";
 324                 };
 325
 326                 mcspi3: spi@480b8000 {
 327                         compatible = "ti,omap4-mcspi";
 328                         reg = <0x480b8000 0x200>;
 329                         interrupts = <0 91 0x4>;
 330                         #address-cells = <1>;
 331                         #size-cells = <0>;
 332                         ti,hwmods = "mcspi3";
 333                         ti,spi-num-cs = <2>;
 334                         dmas = <&sdma 15>, <&sdma 16>;
 335                         dma-names = "tx0", "rx0";
 336                 };
 337
 338                 mcspi4: spi@480ba000 {
 339                         compatible = "ti,omap4-mcspi";
 340                         reg = <0x480ba000 0x200>;
 341                         interrupts = <0 48 0x4>;
 342                         #address-cells = <1>;
 343                         #size-cells = <0>;
 344                         ti,hwmods = "mcspi4";
 345                         ti,spi-num-cs = <1>;
 346                         dmas = <&sdma 70>, <&sdma 71>;
 347                         dma-names = "tx0", "rx0";
 348                 };
 349
 350                 mmc1: mmc@4809c000 {
 351                         compatible = "ti,omap4-hsmmc";
 352                         reg = <0x4809c000 0x400>;
 353                         interrupts = <0 83 0x4>;
 354                         ti,hwmods = "mmc1";
 355                         ti,dual-volt;
 356                         ti,needs-special-reset;
 357                         dmas = <&sdma 61>, <&sdma 62>;
 358                         dma-names = "tx", "rx";
 359                 };
 360
 361                 mmc2: mmc@480b4000 {
 362                         compatible = "ti,omap4-hsmmc";
 363                         reg = <0x480b4000 0x400>;
 364                         interrupts = <0 86 0x4>;
 365                         ti,hwmods = "mmc2";
 366                         ti,needs-special-reset;
 367                         dmas = <&sdma 47>, <&sdma 48>;
 368                         dma-names = "tx", "rx";
 369                 };
 370
 371                 mmc3: mmc@480ad000 {
 372                         compatible = "ti,omap4-hsmmc";
 373                         reg = <0x480ad000 0x400>;
 374                         interrupts = <0 94 0x4>;
 375                         ti,hwmods = "mmc3";
 376                         ti,needs-special-reset;
 377                         dmas = <&sdma 77>, <&sdma 78>;
 378                         dma-names = "tx", "rx";
 379                 };
 380
 381                 mmc4: mmc@480d1000 {
 382                         compatible = "ti,omap4-hsmmc";
 383                         reg = <0x480d1000 0x400>;
 384                         interrupts = <0 96 0x4>;
 385                         ti,hwmods = "mmc4";
 386                         ti,needs-special-reset;
 387                         dmas = <&sdma 57>, <&sdma 58>;
 388                         dma-names = "tx", "rx";
 389                 };
 390
 391                 mmc5: mmc@480d5000 {
 392                         compatible = "ti,omap4-hsmmc";
 393                         reg = <0x480d5000 0x400>;
 394                         interrupts = <0 59 0x4>;
 395                         ti,hwmods = "mmc5";
 396                         ti,needs-special-reset;
 397                         dmas = <&sdma 59>, <&sdma 60>;
 398                         dma-names = "tx", "rx";
 399                 };
 400
 401                 wdt2: wdt@4a314000 {
 402                         compatible = "ti,omap4-wdt", "ti,omap3-wdt";
 403                         reg = <0x4a314000 0x80>;
 404                         interrupts = <0 80 0x4>;
 405                         ti,hwmods = "wd_timer2";
 406                 };
 407
 408                 mcpdm: mcpdm@40132000 {
 409                         compatible = "ti,omap4-mcpdm";
 410                         reg = <0x40132000 0x7f>, /* MPU private access */
 411                               <0x49032000 0x7f>; /* L3 Interconnect */
 412                         reg-names = "mpu", "dma";
 413                         interrupts = <0 112 0x4>;
 414                         ti,hwmods = "mcpdm";
 415                         dmas = <&sdma 65>,
 416                                <&sdma 66>;
 417                         dma-names = "up_link", "dn_link";
 418                 };
 419
 420                 dmic: dmic@4012e000 {
 421                         compatible = "ti,omap4-dmic";
 422                         reg = <0x4012e000 0x7f>, /* MPU private access */
 423                               <0x4902e000 0x7f>; /* L3 Interconnect */
 424                         reg-names = "mpu", "dma";
 425                         interrupts = <0 114 0x4>;
 426                         ti,hwmods = "dmic";
 427                         dmas = <&sdma 67>;
 428                         dma-names = "up_link";
 429                 };
 430
 431                 mcbsp1: mcbsp@40122000 {
 432                         compatible = "ti,omap4-mcbsp";
 433                         reg = <0x40122000 0xff>, /* MPU private access */
 434                               <0x49022000 0xff>; /* L3 Interconnect */
 435                         reg-names = "mpu", "dma";
 436                         interrupts = <0 17 0x4>;
 437                         interrupt-names = "common";
 438                         ti,buffer-size = <128>;
 439                         ti,hwmods = "mcbsp1";
 440                         dmas = <&sdma 33>,
 441                                <&sdma 34>;
 442                         dma-names = "tx", "rx";
 443                 };
 444
 445                 mcbsp2: mcbsp@40124000 {
 446                         compatible = "ti,omap4-mcbsp";
 447                         reg = <0x40124000 0xff>, /* MPU private access */
 448                               <0x49024000 0xff>; /* L3 Interconnect */
 449                         reg-names = "mpu", "dma";
 450                         interrupts = <0 22 0x4>;
 451                         interrupt-names = "common";
 452                         ti,buffer-size = <128>;
 453                         ti,hwmods = "mcbsp2";
 454                         dmas = <&sdma 17>,
 455                                <&sdma 18>;
 456                         dma-names = "tx", "rx";
 457                 };
 458
 459                 mcbsp3: mcbsp@40126000 {
 460                         compatible = "ti,omap4-mcbsp";
 461                         reg = <0x40126000 0xff>, /* MPU private access */
 462                               <0x49026000 0xff>; /* L3 Interconnect */
 463                         reg-names = "mpu", "dma";
 464                         interrupts = <0 23 0x4>;
 465                         interrupt-names = "common";
 466                         ti,buffer-size = <128>;
 467                         ti,hwmods = "mcbsp3";
 468                         dmas = <&sdma 19>,
 469                                <&sdma 20>;
 470                         dma-names = "tx", "rx";
 471                 };
 472
 473                 mcbsp4: mcbsp@48096000 {
 474                         compatible = "ti,omap4-mcbsp";
 475                         reg = <0x48096000 0xff>; /* L4 Interconnect */
 476                         reg-names = "mpu";
 477                         interrupts = <0 16 0x4>;
 478                         interrupt-names = "common";
 479                         ti,buffer-size = <128>;
 480                         ti,hwmods = "mcbsp4";
 481                         dmas = <&sdma 31>,
 482                                <&sdma 32>;
 483                         dma-names = "tx", "rx";
 484                 };
 485
 486                 keypad: keypad@4a31c000 {
 487                         compatible = "ti,omap4-keypad";
 488                         reg = <0x4a31c000 0x80>;
 489                         interrupts = <0 120 0x4>;
 490                         reg-names = "mpu";
 491                         ti,hwmods = "kbd";
 492                 };
 493
 494                 emif1: emif@4c000000 {
 495                         compatible = "ti,emif-4d";
 496                         reg = <0x4c000000 0x100>;
 497                         interrupts = <0 110 0x4>;
 498                         ti,hwmods = "emif1";
 499                         phy-type = <1>;
 500                         hw-caps-read-idle-ctrl;
 501                         hw-caps-ll-interface;
 502                         hw-caps-temp-alert;
 503                 };
 504
 505                 emif2: emif@4d000000 {
 506                         compatible = "ti,emif-4d";
 507                         reg = <0x4d000000 0x100>;
 508                         interrupts = <0 111 0x4>;
 509                         ti,hwmods = "emif2";
 510                         phy-type = <1>;
 511                         hw-caps-read-idle-ctrl;
 512                         hw-caps-ll-interface;
 513                         hw-caps-temp-alert;
 514                 };
 515
 516                 ocp2scp@4a0ad000 {
 517                         compatible = "ti,omap-ocp2scp";
 518                         reg = <0x4a0ad000 0x1f>;
 519                         #address-cells = <1>;
 520                         #size-cells = <1>;
 521                         ranges;
 522                         ti,hwmods = "ocp2scp_usb_phy";
 523                         usb2_phy: usb2phy@4a0ad080 {
 524                                 compatible = "ti,omap-usb2";
 525                                 reg = <0x4a0ad080 0x58>;
 526                                 ctrl-module = <&omap_control_usb>;
 527                         };
 528                 };
 529
 530                 timer1: timer@4a318000 {
 531                         compatible = "ti,omap3430-timer";
 532                         reg = <0x4a318000 0x80>;
 533                         interrupts = <0 37 0x4>;
 534                         ti,hwmods = "timer1";
 535                         ti,timer-alwon;
 536                 };
 537
 538                 timer2: timer@48032000 {
 539                         compatible = "ti,omap3430-timer";
 540                         reg = <0x48032000 0x80>;
 541                         interrupts = <0 38 0x4>;
 542                         ti,hwmods = "timer2";
 543                 };
 544
 545                 timer3: timer@48034000 {
 546                         compatible = "ti,omap4430-timer";
 547                         reg = <0x48034000 0x80>;
 548                         interrupts = <0 39 0x4>;
 549                         ti,hwmods = "timer3";
 550                 };
 551
 552                 timer4: timer@48036000 {
 553                         compatible = "ti,omap4430-timer";
 554                         reg = <0x48036000 0x80>;
 555                         interrupts = <0 40 0x4>;
 556                         ti,hwmods = "timer4";
 557                 };
 558
 559                 timer5: timer@40138000 {
 560                         compatible = "ti,omap4430-timer";
 561                         reg = <0x40138000 0x80>,
 562                               <0x49038000 0x80>;
 563                         interrupts = <0 41 0x4>;
 564                         ti,hwmods = "timer5";
 565                         ti,timer-dsp;
 566                 };
 567
 568                 timer6: timer@4013a000 {
 569                         compatible = "ti,omap4430-timer";
 570                         reg = <0x4013a000 0x80>,
 571                               <0x4903a000 0x80>;
 572                         interrupts = <0 42 0x4>;
 573                         ti,hwmods = "timer6";
 574                         ti,timer-dsp;
 575                 };
 576
 577                 timer7: timer@4013c000 {
 578                         compatible = "ti,omap4430-timer";
 579                         reg = <0x4013c000 0x80>,
 580                               <0x4903c000 0x80>;
 581                         interrupts = <0 43 0x4>;
 582                         ti,hwmods = "timer7";
 583                         ti,timer-dsp;
 584                 };
 585
 586                 timer8: timer@4013e000 {
 587                         compatible = "ti,omap4430-timer";
 588                         reg = <0x4013e000 0x80>,
 589                               <0x4903e000 0x80>;
 590                         interrupts = <0 44 0x4>;
 591                         ti,hwmods = "timer8";
 592                         ti,timer-pwm;
 593                         ti,timer-dsp;
 594                 };
 595
 596                 timer9: timer@4803e000 {
 597                         compatible = "ti,omap4430-timer";
 598                         reg = <0x4803e000 0x80>;
 599                         interrupts = <0 45 0x4>;
 600                         ti,hwmods = "timer9";
 601                         ti,timer-pwm;
 602                 };
 603
 604                 timer10: timer@48086000 {
 605                         compatible = "ti,omap3430-timer";
 606                         reg = <0x48086000 0x80>;
 607                         interrupts = <0 46 0x4>;
 608                         ti,hwmods = "timer10";
 609                         ti,timer-pwm;
 610                 };
 611
 612                 timer11: timer@48088000 {
 613                         compatible = "ti,omap4430-timer";
 614                         reg = <0x48088000 0x80>;
 615                         interrupts = <0 47 0x4>;
 616                         ti,hwmods = "timer11";
 617                         ti,timer-pwm;
 618                 };
 619
 620                 usbhstll: usbhstll@4a062000 {
 621                         compatible = "ti,usbhs-tll";
 622                         reg = <0x4a062000 0x1000>;
 623                         interrupts = <0 78 0x4>;
 624                         ti,hwmods = "usb_tll_hs";
 625                 };
 626
 627                 usbhshost: usbhshost@4a064000 {
 628                         compatible = "ti,usbhs-host";
 629                         reg = <0x4a064000 0x800>;
 630                         ti,hwmods = "usb_host_hs";
 631                         #address-cells = <1>;
 632                         #size-cells = <1>;
 633                         ranges;
 634
 635                         usbhsohci: ohci@4a064800 {
 636                                 compatible = "ti,ohci-omap3", "usb-ohci";
 637                                 reg = <0x4a064800 0x400>;
 638                                 interrupt-parent = <&gic>;
 639                                 interrupts = <0 76 0x4>;
 640                         };
 641
 642                         usbhsehci: ehci@4a064c00 {
 643                                 compatible = "ti,ehci-omap", "usb-ehci";
 644                                 reg = <0x4a064c00 0x400>;
 645                                 interrupt-parent = <&gic>;
 646                                 interrupts = <0 77 0x4>;
 647                         };
 648                 };
 649
 650                 omap_control_usb: omap-control-usb@4a002300 {
 651                         compatible = "ti,omap-control-usb";
 652                         reg = <0x4a002300 0x4>,
 653                               <0x4a00233c 0x4>;
 654                         reg-names = "control_dev_conf", "otghs_control";
 655                         ti,type = <1>;
 656                 };
 657
 658                 usb_otg_hs: usb_otg_hs@4a0ab000 {
 659                         compatible = "ti,omap4-musb";
 660                         reg = <0x4a0ab000 0x7ff>;
 661                         interrupts = <0 92 0x4>, <0 93 0x4>;
 662                         interrupt-names = "mc", "dma";
 663                         ti,hwmods = "usb_otg_hs";
 664                         usb-phy = <&usb2_phy>;
 665                         multipoint = <1>;
 666                         num-eps = <16>;
 667                         ram-bits = <12>;
 668                         ti,has-mailbox;
 669                 };
 670         };
 671 };