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1e84db866af62a4addcde14d431d87bf5235c7a4
[deliverable/linux.git] / arch / arm / boot / dts / omap5.dtsi
1 /*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
9
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/pinctrl/omap.h>
13
14 #include "skeleton.dtsi"
15
16 / {
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 compatible = "ti,omap5";
21 interrupt-parent = <&gic>;
22
23 aliases {
24 serial0 = &uart1;
25 serial1 = &uart2;
26 serial2 = &uart3;
27 serial3 = &uart4;
28 serial4 = &uart5;
29 serial5 = &uart6;
30 };
31
32 cpus {
33 cpu@0 {
34 compatible = "arm,cortex-a15";
35 };
36 cpu@1 {
37 compatible = "arm,cortex-a15";
38 };
39 };
40
41 timer {
42 compatible = "arm,armv7-timer";
43 /* PPI secure/nonsecure IRQ */
44 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
45 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
46 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
47 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
48 clock-frequency = <6144000>;
49 };
50
51 gic: interrupt-controller@48211000 {
52 compatible = "arm,cortex-a15-gic";
53 interrupt-controller;
54 #interrupt-cells = <3>;
55 reg = <0x48211000 0x1000>,
56 <0x48212000 0x1000>,
57 <0x48214000 0x2000>,
58 <0x48216000 0x2000>;
59 };
60
61 /*
62 * The soc node represents the soc top level view. It is uses for IPs
63 * that are not memory mapped in the MPU view or for the MPU itself.
64 */
65 soc {
66 compatible = "ti,omap-infra";
67 mpu {
68 compatible = "ti,omap5-mpu";
69 ti,hwmods = "mpu";
70 };
71 };
72
73 /*
74 * XXX: Use a flat representation of the OMAP3 interconnect.
75 * The real OMAP interconnect network is quite complex.
76 * Since that will not bring real advantage to represent that in DT for
77 * the moment, just use a fake OCP bus entry to represent the whole bus
78 * hierarchy.
79 */
80 ocp {
81 compatible = "ti,omap4-l3-noc", "simple-bus";
82 #address-cells = <1>;
83 #size-cells = <1>;
84 ranges;
85 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
86 reg = <0x44000000 0x2000>,
87 <0x44800000 0x3000>,
88 <0x45000000 0x4000>;
89 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
90 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
91
92 counter32k: counter@4ae04000 {
93 compatible = "ti,omap-counter32k";
94 reg = <0x4ae04000 0x40>;
95 ti,hwmods = "counter_32k";
96 };
97
98 omap5_pmx_core: pinmux@4a002840 {
99 compatible = "ti,omap4-padconf", "pinctrl-single";
100 reg = <0x4a002840 0x01b6>;
101 #address-cells = <1>;
102 #size-cells = <0>;
103 pinctrl-single,register-width = <16>;
104 pinctrl-single,function-mask = <0x7fff>;
105 };
106 omap5_pmx_wkup: pinmux@4ae0c840 {
107 compatible = "ti,omap4-padconf", "pinctrl-single";
108 reg = <0x4ae0c840 0x0038>;
109 #address-cells = <1>;
110 #size-cells = <0>;
111 pinctrl-single,register-width = <16>;
112 pinctrl-single,function-mask = <0x7fff>;
113 };
114
115 sdma: dma-controller@4a056000 {
116 compatible = "ti,omap4430-sdma";
117 reg = <0x4a056000 0x1000>;
118 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
119 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
120 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
121 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
122 #dma-cells = <1>;
123 #dma-channels = <32>;
124 #dma-requests = <127>;
125 };
126
127 gpio1: gpio@4ae10000 {
128 compatible = "ti,omap4-gpio";
129 reg = <0x4ae10000 0x200>;
130 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
131 ti,hwmods = "gpio1";
132 ti,gpio-always-on;
133 gpio-controller;
134 #gpio-cells = <2>;
135 interrupt-controller;
136 #interrupt-cells = <2>;
137 };
138
139 gpio2: gpio@48055000 {
140 compatible = "ti,omap4-gpio";
141 reg = <0x48055000 0x200>;
142 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
143 ti,hwmods = "gpio2";
144 gpio-controller;
145 #gpio-cells = <2>;
146 interrupt-controller;
147 #interrupt-cells = <2>;
148 };
149
150 gpio3: gpio@48057000 {
151 compatible = "ti,omap4-gpio";
152 reg = <0x48057000 0x200>;
153 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
154 ti,hwmods = "gpio3";
155 gpio-controller;
156 #gpio-cells = <2>;
157 interrupt-controller;
158 #interrupt-cells = <2>;
159 };
160
161 gpio4: gpio@48059000 {
162 compatible = "ti,omap4-gpio";
163 reg = <0x48059000 0x200>;
164 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
165 ti,hwmods = "gpio4";
166 gpio-controller;
167 #gpio-cells = <2>;
168 interrupt-controller;
169 #interrupt-cells = <2>;
170 };
171
172 gpio5: gpio@4805b000 {
173 compatible = "ti,omap4-gpio";
174 reg = <0x4805b000 0x200>;
175 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
176 ti,hwmods = "gpio5";
177 gpio-controller;
178 #gpio-cells = <2>;
179 interrupt-controller;
180 #interrupt-cells = <2>;
181 };
182
183 gpio6: gpio@4805d000 {
184 compatible = "ti,omap4-gpio";
185 reg = <0x4805d000 0x200>;
186 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
187 ti,hwmods = "gpio6";
188 gpio-controller;
189 #gpio-cells = <2>;
190 interrupt-controller;
191 #interrupt-cells = <2>;
192 };
193
194 gpio7: gpio@48051000 {
195 compatible = "ti,omap4-gpio";
196 reg = <0x48051000 0x200>;
197 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
198 ti,hwmods = "gpio7";
199 gpio-controller;
200 #gpio-cells = <2>;
201 interrupt-controller;
202 #interrupt-cells = <2>;
203 };
204
205 gpio8: gpio@48053000 {
206 compatible = "ti,omap4-gpio";
207 reg = <0x48053000 0x200>;
208 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
209 ti,hwmods = "gpio8";
210 gpio-controller;
211 #gpio-cells = <2>;
212 interrupt-controller;
213 #interrupt-cells = <2>;
214 };
215
216 gpmc: gpmc@50000000 {
217 compatible = "ti,omap4430-gpmc";
218 reg = <0x50000000 0x1000>;
219 #address-cells = <2>;
220 #size-cells = <1>;
221 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
222 gpmc,num-cs = <8>;
223 gpmc,num-waitpins = <4>;
224 ti,hwmods = "gpmc";
225 };
226
227 i2c1: i2c@48070000 {
228 compatible = "ti,omap4-i2c";
229 reg = <0x48070000 0x100>;
230 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
231 #address-cells = <1>;
232 #size-cells = <0>;
233 ti,hwmods = "i2c1";
234 };
235
236 i2c2: i2c@48072000 {
237 compatible = "ti,omap4-i2c";
238 reg = <0x48072000 0x100>;
239 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
240 #address-cells = <1>;
241 #size-cells = <0>;
242 ti,hwmods = "i2c2";
243 };
244
245 i2c3: i2c@48060000 {
246 compatible = "ti,omap4-i2c";
247 reg = <0x48060000 0x100>;
248 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
249 #address-cells = <1>;
250 #size-cells = <0>;
251 ti,hwmods = "i2c3";
252 };
253
254 i2c4: i2c@4807a000 {
255 compatible = "ti,omap4-i2c";
256 reg = <0x4807a000 0x100>;
257 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
258 #address-cells = <1>;
259 #size-cells = <0>;
260 ti,hwmods = "i2c4";
261 };
262
263 i2c5: i2c@4807c000 {
264 compatible = "ti,omap4-i2c";
265 reg = <0x4807c000 0x100>;
266 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
267 #address-cells = <1>;
268 #size-cells = <0>;
269 ti,hwmods = "i2c5";
270 };
271
272 mcspi1: spi@48098000 {
273 compatible = "ti,omap4-mcspi";
274 reg = <0x48098000 0x200>;
275 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
276 #address-cells = <1>;
277 #size-cells = <0>;
278 ti,hwmods = "mcspi1";
279 ti,spi-num-cs = <4>;
280 dmas = <&sdma 35>,
281 <&sdma 36>,
282 <&sdma 37>,
283 <&sdma 38>,
284 <&sdma 39>,
285 <&sdma 40>,
286 <&sdma 41>,
287 <&sdma 42>;
288 dma-names = "tx0", "rx0", "tx1", "rx1",
289 "tx2", "rx2", "tx3", "rx3";
290 };
291
292 mcspi2: spi@4809a000 {
293 compatible = "ti,omap4-mcspi";
294 reg = <0x4809a000 0x200>;
295 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
296 #address-cells = <1>;
297 #size-cells = <0>;
298 ti,hwmods = "mcspi2";
299 ti,spi-num-cs = <2>;
300 dmas = <&sdma 43>,
301 <&sdma 44>,
302 <&sdma 45>,
303 <&sdma 46>;
304 dma-names = "tx0", "rx0", "tx1", "rx1";
305 };
306
307 mcspi3: spi@480b8000 {
308 compatible = "ti,omap4-mcspi";
309 reg = <0x480b8000 0x200>;
310 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
311 #address-cells = <1>;
312 #size-cells = <0>;
313 ti,hwmods = "mcspi3";
314 ti,spi-num-cs = <2>;
315 dmas = <&sdma 15>, <&sdma 16>;
316 dma-names = "tx0", "rx0";
317 };
318
319 mcspi4: spi@480ba000 {
320 compatible = "ti,omap4-mcspi";
321 reg = <0x480ba000 0x200>;
322 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
323 #address-cells = <1>;
324 #size-cells = <0>;
325 ti,hwmods = "mcspi4";
326 ti,spi-num-cs = <1>;
327 dmas = <&sdma 70>, <&sdma 71>;
328 dma-names = "tx0", "rx0";
329 };
330
331 uart1: serial@4806a000 {
332 compatible = "ti,omap4-uart";
333 reg = <0x4806a000 0x100>;
334 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
335 ti,hwmods = "uart1";
336 clock-frequency = <48000000>;
337 };
338
339 uart2: serial@4806c000 {
340 compatible = "ti,omap4-uart";
341 reg = <0x4806c000 0x100>;
342 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
343 ti,hwmods = "uart2";
344 clock-frequency = <48000000>;
345 };
346
347 uart3: serial@48020000 {
348 compatible = "ti,omap4-uart";
349 reg = <0x48020000 0x100>;
350 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
351 ti,hwmods = "uart3";
352 clock-frequency = <48000000>;
353 };
354
355 uart4: serial@4806e000 {
356 compatible = "ti,omap4-uart";
357 reg = <0x4806e000 0x100>;
358 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
359 ti,hwmods = "uart4";
360 clock-frequency = <48000000>;
361 };
362
363 uart5: serial@48066000 {
364 compatible = "ti,omap4-uart";
365 reg = <0x48066000 0x100>;
366 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
367 ti,hwmods = "uart5";
368 clock-frequency = <48000000>;
369 };
370
371 uart6: serial@48068000 {
372 compatible = "ti,omap4-uart";
373 reg = <0x48068000 0x100>;
374 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
375 ti,hwmods = "uart6";
376 clock-frequency = <48000000>;
377 };
378
379 mmc1: mmc@4809c000 {
380 compatible = "ti,omap4-hsmmc";
381 reg = <0x4809c000 0x400>;
382 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
383 ti,hwmods = "mmc1";
384 ti,dual-volt;
385 ti,needs-special-reset;
386 dmas = <&sdma 61>, <&sdma 62>;
387 dma-names = "tx", "rx";
388 };
389
390 mmc2: mmc@480b4000 {
391 compatible = "ti,omap4-hsmmc";
392 reg = <0x480b4000 0x400>;
393 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
394 ti,hwmods = "mmc2";
395 ti,needs-special-reset;
396 dmas = <&sdma 47>, <&sdma 48>;
397 dma-names = "tx", "rx";
398 };
399
400 mmc3: mmc@480ad000 {
401 compatible = "ti,omap4-hsmmc";
402 reg = <0x480ad000 0x400>;
403 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
404 ti,hwmods = "mmc3";
405 ti,needs-special-reset;
406 dmas = <&sdma 77>, <&sdma 78>;
407 dma-names = "tx", "rx";
408 };
409
410 mmc4: mmc@480d1000 {
411 compatible = "ti,omap4-hsmmc";
412 reg = <0x480d1000 0x400>;
413 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
414 ti,hwmods = "mmc4";
415 ti,needs-special-reset;
416 dmas = <&sdma 57>, <&sdma 58>;
417 dma-names = "tx", "rx";
418 };
419
420 mmc5: mmc@480d5000 {
421 compatible = "ti,omap4-hsmmc";
422 reg = <0x480d5000 0x400>;
423 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
424 ti,hwmods = "mmc5";
425 ti,needs-special-reset;
426 dmas = <&sdma 59>, <&sdma 60>;
427 dma-names = "tx", "rx";
428 };
429
430 keypad: keypad@4ae1c000 {
431 compatible = "ti,omap4-keypad";
432 reg = <0x4ae1c000 0x400>;
433 ti,hwmods = "kbd";
434 };
435
436 mcpdm: mcpdm@40132000 {
437 compatible = "ti,omap4-mcpdm";
438 reg = <0x40132000 0x7f>, /* MPU private access */
439 <0x49032000 0x7f>; /* L3 Interconnect */
440 reg-names = "mpu", "dma";
441 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
442 ti,hwmods = "mcpdm";
443 dmas = <&sdma 65>,
444 <&sdma 66>;
445 dma-names = "up_link", "dn_link";
446 };
447
448 dmic: dmic@4012e000 {
449 compatible = "ti,omap4-dmic";
450 reg = <0x4012e000 0x7f>, /* MPU private access */
451 <0x4902e000 0x7f>; /* L3 Interconnect */
452 reg-names = "mpu", "dma";
453 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
454 ti,hwmods = "dmic";
455 dmas = <&sdma 67>;
456 dma-names = "up_link";
457 };
458
459 mcbsp1: mcbsp@40122000 {
460 compatible = "ti,omap4-mcbsp";
461 reg = <0x40122000 0xff>, /* MPU private access */
462 <0x49022000 0xff>; /* L3 Interconnect */
463 reg-names = "mpu", "dma";
464 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
465 interrupt-names = "common";
466 ti,buffer-size = <128>;
467 ti,hwmods = "mcbsp1";
468 dmas = <&sdma 33>,
469 <&sdma 34>;
470 dma-names = "tx", "rx";
471 };
472
473 mcbsp2: mcbsp@40124000 {
474 compatible = "ti,omap4-mcbsp";
475 reg = <0x40124000 0xff>, /* MPU private access */
476 <0x49024000 0xff>; /* L3 Interconnect */
477 reg-names = "mpu", "dma";
478 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
479 interrupt-names = "common";
480 ti,buffer-size = <128>;
481 ti,hwmods = "mcbsp2";
482 dmas = <&sdma 17>,
483 <&sdma 18>;
484 dma-names = "tx", "rx";
485 };
486
487 mcbsp3: mcbsp@40126000 {
488 compatible = "ti,omap4-mcbsp";
489 reg = <0x40126000 0xff>, /* MPU private access */
490 <0x49026000 0xff>; /* L3 Interconnect */
491 reg-names = "mpu", "dma";
492 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
493 interrupt-names = "common";
494 ti,buffer-size = <128>;
495 ti,hwmods = "mcbsp3";
496 dmas = <&sdma 19>,
497 <&sdma 20>;
498 dma-names = "tx", "rx";
499 };
500
501 timer1: timer@4ae18000 {
502 compatible = "ti,omap5430-timer";
503 reg = <0x4ae18000 0x80>;
504 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
505 ti,hwmods = "timer1";
506 ti,timer-alwon;
507 };
508
509 timer2: timer@48032000 {
510 compatible = "ti,omap5430-timer";
511 reg = <0x48032000 0x80>;
512 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
513 ti,hwmods = "timer2";
514 };
515
516 timer3: timer@48034000 {
517 compatible = "ti,omap5430-timer";
518 reg = <0x48034000 0x80>;
519 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
520 ti,hwmods = "timer3";
521 };
522
523 timer4: timer@48036000 {
524 compatible = "ti,omap5430-timer";
525 reg = <0x48036000 0x80>;
526 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
527 ti,hwmods = "timer4";
528 };
529
530 timer5: timer@40138000 {
531 compatible = "ti,omap5430-timer";
532 reg = <0x40138000 0x80>,
533 <0x49038000 0x80>;
534 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
535 ti,hwmods = "timer5";
536 ti,timer-dsp;
537 ti,timer-pwm;
538 };
539
540 timer6: timer@4013a000 {
541 compatible = "ti,omap5430-timer";
542 reg = <0x4013a000 0x80>,
543 <0x4903a000 0x80>;
544 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
545 ti,hwmods = "timer6";
546 ti,timer-dsp;
547 ti,timer-pwm;
548 };
549
550 timer7: timer@4013c000 {
551 compatible = "ti,omap5430-timer";
552 reg = <0x4013c000 0x80>,
553 <0x4903c000 0x80>;
554 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
555 ti,hwmods = "timer7";
556 ti,timer-dsp;
557 };
558
559 timer8: timer@4013e000 {
560 compatible = "ti,omap5430-timer";
561 reg = <0x4013e000 0x80>,
562 <0x4903e000 0x80>;
563 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
564 ti,hwmods = "timer8";
565 ti,timer-dsp;
566 ti,timer-pwm;
567 };
568
569 timer9: timer@4803e000 {
570 compatible = "ti,omap5430-timer";
571 reg = <0x4803e000 0x80>;
572 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
573 ti,hwmods = "timer9";
574 ti,timer-pwm;
575 };
576
577 timer10: timer@48086000 {
578 compatible = "ti,omap5430-timer";
579 reg = <0x48086000 0x80>;
580 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
581 ti,hwmods = "timer10";
582 ti,timer-pwm;
583 };
584
585 timer11: timer@48088000 {
586 compatible = "ti,omap5430-timer";
587 reg = <0x48088000 0x80>;
588 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
589 ti,hwmods = "timer11";
590 ti,timer-pwm;
591 };
592
593 wdt2: wdt@4ae14000 {
594 compatible = "ti,omap5-wdt", "ti,omap3-wdt";
595 reg = <0x4ae14000 0x80>;
596 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
597 ti,hwmods = "wd_timer2";
598 };
599
600 emif1: emif@0x4c000000 {
601 compatible = "ti,emif-4d5";
602 ti,hwmods = "emif1";
603 phy-type = <2>; /* DDR PHY type: Intelli PHY */
604 reg = <0x4c000000 0x400>;
605 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
606 hw-caps-read-idle-ctrl;
607 hw-caps-ll-interface;
608 hw-caps-temp-alert;
609 };
610
611 emif2: emif@0x4d000000 {
612 compatible = "ti,emif-4d5";
613 ti,hwmods = "emif2";
614 phy-type = <2>; /* DDR PHY type: Intelli PHY */
615 reg = <0x4d000000 0x400>;
616 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
617 hw-caps-read-idle-ctrl;
618 hw-caps-ll-interface;
619 hw-caps-temp-alert;
620 };
621
622 omap_control_usb: omap-control-usb@4a002300 {
623 compatible = "ti,omap-control-usb";
624 reg = <0x4a002300 0x4>,
625 <0x4a002370 0x4>;
626 reg-names = "control_dev_conf", "phy_power_usb";
627 ti,type = <2>;
628 };
629
630 omap_dwc3@4a020000 {
631 compatible = "ti,dwc3";
632 ti,hwmods = "usb_otg_ss";
633 reg = <0x4a020000 0x1000>;
634 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
635 #address-cells = <1>;
636 #size-cells = <1>;
637 utmi-mode = <2>;
638 ranges;
639 dwc3@4a030000 {
640 compatible = "synopsys,dwc3";
641 reg = <0x4a030000 0x1000>;
642 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
643 usb-phy = <&usb2_phy>, <&usb3_phy>;
644 tx-fifo-resize;
645 };
646 };
647
648 ocp2scp {
649 compatible = "ti,omap-ocp2scp";
650 #address-cells = <1>;
651 #size-cells = <1>;
652 ranges;
653 ti,hwmods = "ocp2scp1";
654 usb2_phy: usb2phy@4a084000 {
655 compatible = "ti,omap-usb2";
656 reg = <0x4a084000 0x7c>;
657 ctrl-module = <&omap_control_usb>;
658 };
659
660 usb3_phy: usb3phy@4a084400 {
661 compatible = "ti,omap-usb3";
662 reg = <0x4a084400 0x80>,
663 <0x4a084800 0x64>,
664 <0x4a084c00 0x40>;
665 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
666 ctrl-module = <&omap_control_usb>;
667 };
668 };
669 };
670 };
Linux kernel - Deliverables
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