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ARM: meson: dts: add basic Meson/Meson6/Meson6-atv1200 DTSI/DTS
[deliverable/linux.git] / arch / arm / boot / dts / omap5.dtsi
1 /*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
9
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/pinctrl/omap.h>
13
14 #include "skeleton.dtsi"
15
16 / {
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 compatible = "ti,omap5";
21 interrupt-parent = <&gic>;
22
23 aliases {
24 i2c0 = &i2c1;
25 i2c1 = &i2c2;
26 i2c2 = &i2c3;
27 i2c3 = &i2c4;
28 i2c4 = &i2c5;
29 serial0 = &uart1;
30 serial1 = &uart2;
31 serial2 = &uart3;
32 serial3 = &uart4;
33 serial4 = &uart5;
34 serial5 = &uart6;
35 };
36
37 cpus {
38 #address-cells = <1>;
39 #size-cells = <0>;
40
41 cpu0: cpu@0 {
42 device_type = "cpu";
43 compatible = "arm,cortex-a15";
44 reg = <0x0>;
45
46 operating-points = <
47 /* kHz uV */
48 1000000 1060000
49 1500000 1250000
50 >;
51
52 clocks = <&dpll_mpu_ck>;
53 clock-names = "cpu";
54
55 clock-latency = <300000>; /* From omap-cpufreq driver */
56
57 /* cooling options */
58 cooling-min-level = <0>;
59 cooling-max-level = <2>;
60 #cooling-cells = <2>; /* min followed by max */
61 };
62 cpu@1 {
63 device_type = "cpu";
64 compatible = "arm,cortex-a15";
65 reg = <0x1>;
66 };
67 };
68
69 thermal-zones {
70 #include "omap4-cpu-thermal.dtsi"
71 #include "omap5-gpu-thermal.dtsi"
72 #include "omap5-core-thermal.dtsi"
73 };
74
75 timer {
76 compatible = "arm,armv7-timer";
77 /* PPI secure/nonsecure IRQ */
78 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
79 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
80 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
81 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
82 };
83
84 pmu {
85 compatible = "arm,cortex-a15-pmu";
86 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
87 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
88 };
89
90 gic: interrupt-controller@48211000 {
91 compatible = "arm,cortex-a15-gic";
92 interrupt-controller;
93 #interrupt-cells = <3>;
94 reg = <0x48211000 0x1000>,
95 <0x48212000 0x1000>,
96 <0x48214000 0x2000>,
97 <0x48216000 0x2000>;
98 };
99
100 /*
101 * The soc node represents the soc top level view. It is used for IPs
102 * that are not memory mapped in the MPU view or for the MPU itself.
103 */
104 soc {
105 compatible = "ti,omap-infra";
106 mpu {
107 compatible = "ti,omap5-mpu";
108 ti,hwmods = "mpu";
109 };
110 };
111
112 /*
113 * XXX: Use a flat representation of the OMAP3 interconnect.
114 * The real OMAP interconnect network is quite complex.
115 * Since it will not bring real advantage to represent that in DT for
116 * the moment, just use a fake OCP bus entry to represent the whole bus
117 * hierarchy.
118 */
119 ocp {
120 compatible = "ti,omap4-l3-noc", "simple-bus";
121 #address-cells = <1>;
122 #size-cells = <1>;
123 ranges;
124 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
125 reg = <0x44000000 0x2000>,
126 <0x44800000 0x3000>,
127 <0x45000000 0x4000>;
128 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
129 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
130
131 prm: prm@4ae06000 {
132 compatible = "ti,omap5-prm";
133 reg = <0x4ae06000 0x3000>;
134
135 prm_clocks: clocks {
136 #address-cells = <1>;
137 #size-cells = <0>;
138 };
139
140 prm_clockdomains: clockdomains {
141 };
142 };
143
144 cm_core_aon: cm_core_aon@4a004000 {
145 compatible = "ti,omap5-cm-core-aon";
146 reg = <0x4a004000 0x2000>;
147
148 cm_core_aon_clocks: clocks {
149 #address-cells = <1>;
150 #size-cells = <0>;
151 };
152
153 cm_core_aon_clockdomains: clockdomains {
154 };
155 };
156
157 scrm: scrm@4ae0a000 {
158 compatible = "ti,omap5-scrm";
159 reg = <0x4ae0a000 0x2000>;
160
161 scrm_clocks: clocks {
162 #address-cells = <1>;
163 #size-cells = <0>;
164 };
165
166 scrm_clockdomains: clockdomains {
167 };
168 };
169
170 cm_core: cm_core@4a008000 {
171 compatible = "ti,omap5-cm-core";
172 reg = <0x4a008000 0x3000>;
173
174 cm_core_clocks: clocks {
175 #address-cells = <1>;
176 #size-cells = <0>;
177 };
178
179 cm_core_clockdomains: clockdomains {
180 };
181 };
182
183 counter32k: counter@4ae04000 {
184 compatible = "ti,omap-counter32k";
185 reg = <0x4ae04000 0x40>;
186 ti,hwmods = "counter_32k";
187 };
188
189 omap5_pmx_core: pinmux@4a002840 {
190 compatible = "ti,omap5-padconf", "pinctrl-single";
191 reg = <0x4a002840 0x01b6>;
192 #address-cells = <1>;
193 #size-cells = <0>;
194 #interrupt-cells = <1>;
195 interrupt-controller;
196 pinctrl-single,register-width = <16>;
197 pinctrl-single,function-mask = <0x7fff>;
198 };
199 omap5_pmx_wkup: pinmux@4ae0c840 {
200 compatible = "ti,omap5-padconf", "pinctrl-single";
201 reg = <0x4ae0c840 0x0038>;
202 #address-cells = <1>;
203 #size-cells = <0>;
204 #interrupt-cells = <1>;
205 interrupt-controller;
206 pinctrl-single,register-width = <16>;
207 pinctrl-single,function-mask = <0x7fff>;
208 };
209
210 omap5_padconf_global: tisyscon@4a002da0 {
211 compatible = "syscon";
212 reg = <0x4A002da0 0xec>;
213 };
214
215 pbias_regulator: pbias_regulator {
216 compatible = "ti,pbias-omap";
217 reg = <0x60 0x4>;
218 syscon = <&omap5_padconf_global>;
219 pbias_mmc_reg: pbias_mmc_omap5 {
220 regulator-name = "pbias_mmc_omap5";
221 regulator-min-microvolt = <1800000>;
222 regulator-max-microvolt = <3000000>;
223 };
224 };
225
226 sdma: dma-controller@4a056000 {
227 compatible = "ti,omap4430-sdma";
228 reg = <0x4a056000 0x1000>;
229 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
230 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
231 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
232 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
233 #dma-cells = <1>;
234 #dma-channels = <32>;
235 #dma-requests = <127>;
236 };
237
238 gpio1: gpio@4ae10000 {
239 compatible = "ti,omap4-gpio";
240 reg = <0x4ae10000 0x200>;
241 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
242 ti,hwmods = "gpio1";
243 ti,gpio-always-on;
244 gpio-controller;
245 #gpio-cells = <2>;
246 interrupt-controller;
247 #interrupt-cells = <2>;
248 };
249
250 gpio2: gpio@48055000 {
251 compatible = "ti,omap4-gpio";
252 reg = <0x48055000 0x200>;
253 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
254 ti,hwmods = "gpio2";
255 gpio-controller;
256 #gpio-cells = <2>;
257 interrupt-controller;
258 #interrupt-cells = <2>;
259 };
260
261 gpio3: gpio@48057000 {
262 compatible = "ti,omap4-gpio";
263 reg = <0x48057000 0x200>;
264 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
265 ti,hwmods = "gpio3";
266 gpio-controller;
267 #gpio-cells = <2>;
268 interrupt-controller;
269 #interrupt-cells = <2>;
270 };
271
272 gpio4: gpio@48059000 {
273 compatible = "ti,omap4-gpio";
274 reg = <0x48059000 0x200>;
275 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
276 ti,hwmods = "gpio4";
277 gpio-controller;
278 #gpio-cells = <2>;
279 interrupt-controller;
280 #interrupt-cells = <2>;
281 };
282
283 gpio5: gpio@4805b000 {
284 compatible = "ti,omap4-gpio";
285 reg = <0x4805b000 0x200>;
286 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
287 ti,hwmods = "gpio5";
288 gpio-controller;
289 #gpio-cells = <2>;
290 interrupt-controller;
291 #interrupt-cells = <2>;
292 };
293
294 gpio6: gpio@4805d000 {
295 compatible = "ti,omap4-gpio";
296 reg = <0x4805d000 0x200>;
297 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
298 ti,hwmods = "gpio6";
299 gpio-controller;
300 #gpio-cells = <2>;
301 interrupt-controller;
302 #interrupt-cells = <2>;
303 };
304
305 gpio7: gpio@48051000 {
306 compatible = "ti,omap4-gpio";
307 reg = <0x48051000 0x200>;
308 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
309 ti,hwmods = "gpio7";
310 gpio-controller;
311 #gpio-cells = <2>;
312 interrupt-controller;
313 #interrupt-cells = <2>;
314 };
315
316 gpio8: gpio@48053000 {
317 compatible = "ti,omap4-gpio";
318 reg = <0x48053000 0x200>;
319 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
320 ti,hwmods = "gpio8";
321 gpio-controller;
322 #gpio-cells = <2>;
323 interrupt-controller;
324 #interrupt-cells = <2>;
325 };
326
327 gpmc: gpmc@50000000 {
328 compatible = "ti,omap4430-gpmc";
329 reg = <0x50000000 0x1000>;
330 #address-cells = <2>;
331 #size-cells = <1>;
332 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
333 gpmc,num-cs = <8>;
334 gpmc,num-waitpins = <4>;
335 ti,hwmods = "gpmc";
336 clocks = <&l3_iclk_div>;
337 clock-names = "fck";
338 };
339
340 i2c1: i2c@48070000 {
341 compatible = "ti,omap4-i2c";
342 reg = <0x48070000 0x100>;
343 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
344 #address-cells = <1>;
345 #size-cells = <0>;
346 ti,hwmods = "i2c1";
347 };
348
349 i2c2: i2c@48072000 {
350 compatible = "ti,omap4-i2c";
351 reg = <0x48072000 0x100>;
352 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
353 #address-cells = <1>;
354 #size-cells = <0>;
355 ti,hwmods = "i2c2";
356 };
357
358 i2c3: i2c@48060000 {
359 compatible = "ti,omap4-i2c";
360 reg = <0x48060000 0x100>;
361 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
362 #address-cells = <1>;
363 #size-cells = <0>;
364 ti,hwmods = "i2c3";
365 };
366
367 i2c4: i2c@4807a000 {
368 compatible = "ti,omap4-i2c";
369 reg = <0x4807a000 0x100>;
370 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
371 #address-cells = <1>;
372 #size-cells = <0>;
373 ti,hwmods = "i2c4";
374 };
375
376 i2c5: i2c@4807c000 {
377 compatible = "ti,omap4-i2c";
378 reg = <0x4807c000 0x100>;
379 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
380 #address-cells = <1>;
381 #size-cells = <0>;
382 ti,hwmods = "i2c5";
383 };
384
385 hwspinlock: spinlock@4a0f6000 {
386 compatible = "ti,omap4-hwspinlock";
387 reg = <0x4a0f6000 0x1000>;
388 ti,hwmods = "spinlock";
389 #hwlock-cells = <1>;
390 };
391
392 mcspi1: spi@48098000 {
393 compatible = "ti,omap4-mcspi";
394 reg = <0x48098000 0x200>;
395 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
396 #address-cells = <1>;
397 #size-cells = <0>;
398 ti,hwmods = "mcspi1";
399 ti,spi-num-cs = <4>;
400 dmas = <&sdma 35>,
401 <&sdma 36>,
402 <&sdma 37>,
403 <&sdma 38>,
404 <&sdma 39>,
405 <&sdma 40>,
406 <&sdma 41>,
407 <&sdma 42>;
408 dma-names = "tx0", "rx0", "tx1", "rx1",
409 "tx2", "rx2", "tx3", "rx3";
410 };
411
412 mcspi2: spi@4809a000 {
413 compatible = "ti,omap4-mcspi";
414 reg = <0x4809a000 0x200>;
415 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
416 #address-cells = <1>;
417 #size-cells = <0>;
418 ti,hwmods = "mcspi2";
419 ti,spi-num-cs = <2>;
420 dmas = <&sdma 43>,
421 <&sdma 44>,
422 <&sdma 45>,
423 <&sdma 46>;
424 dma-names = "tx0", "rx0", "tx1", "rx1";
425 };
426
427 mcspi3: spi@480b8000 {
428 compatible = "ti,omap4-mcspi";
429 reg = <0x480b8000 0x200>;
430 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
431 #address-cells = <1>;
432 #size-cells = <0>;
433 ti,hwmods = "mcspi3";
434 ti,spi-num-cs = <2>;
435 dmas = <&sdma 15>, <&sdma 16>;
436 dma-names = "tx0", "rx0";
437 };
438
439 mcspi4: spi@480ba000 {
440 compatible = "ti,omap4-mcspi";
441 reg = <0x480ba000 0x200>;
442 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
443 #address-cells = <1>;
444 #size-cells = <0>;
445 ti,hwmods = "mcspi4";
446 ti,spi-num-cs = <1>;
447 dmas = <&sdma 70>, <&sdma 71>;
448 dma-names = "tx0", "rx0";
449 };
450
451 uart1: serial@4806a000 {
452 compatible = "ti,omap4-uart";
453 reg = <0x4806a000 0x100>;
454 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
455 ti,hwmods = "uart1";
456 clock-frequency = <48000000>;
457 };
458
459 uart2: serial@4806c000 {
460 compatible = "ti,omap4-uart";
461 reg = <0x4806c000 0x100>;
462 interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
463 ti,hwmods = "uart2";
464 clock-frequency = <48000000>;
465 };
466
467 uart3: serial@48020000 {
468 compatible = "ti,omap4-uart";
469 reg = <0x48020000 0x100>;
470 interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
471 ti,hwmods = "uart3";
472 clock-frequency = <48000000>;
473 };
474
475 uart4: serial@4806e000 {
476 compatible = "ti,omap4-uart";
477 reg = <0x4806e000 0x100>;
478 interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
479 ti,hwmods = "uart4";
480 clock-frequency = <48000000>;
481 };
482
483 uart5: serial@48066000 {
484 compatible = "ti,omap4-uart";
485 reg = <0x48066000 0x100>;
486 interrupts-extended = <&gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
487 ti,hwmods = "uart5";
488 clock-frequency = <48000000>;
489 };
490
491 uart6: serial@48068000 {
492 compatible = "ti,omap4-uart";
493 reg = <0x48068000 0x100>;
494 interrupts-extended = <&gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
495 ti,hwmods = "uart6";
496 clock-frequency = <48000000>;
497 };
498
499 mmc1: mmc@4809c000 {
500 compatible = "ti,omap4-hsmmc";
501 reg = <0x4809c000 0x400>;
502 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
503 ti,hwmods = "mmc1";
504 ti,dual-volt;
505 ti,needs-special-reset;
506 dmas = <&sdma 61>, <&sdma 62>;
507 dma-names = "tx", "rx";
508 pbias-supply = <&pbias_mmc_reg>;
509 };
510
511 mmc2: mmc@480b4000 {
512 compatible = "ti,omap4-hsmmc";
513 reg = <0x480b4000 0x400>;
514 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
515 ti,hwmods = "mmc2";
516 ti,needs-special-reset;
517 dmas = <&sdma 47>, <&sdma 48>;
518 dma-names = "tx", "rx";
519 };
520
521 mmc3: mmc@480ad000 {
522 compatible = "ti,omap4-hsmmc";
523 reg = <0x480ad000 0x400>;
524 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
525 ti,hwmods = "mmc3";
526 ti,needs-special-reset;
527 dmas = <&sdma 77>, <&sdma 78>;
528 dma-names = "tx", "rx";
529 };
530
531 mmc4: mmc@480d1000 {
532 compatible = "ti,omap4-hsmmc";
533 reg = <0x480d1000 0x400>;
534 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
535 ti,hwmods = "mmc4";
536 ti,needs-special-reset;
537 dmas = <&sdma 57>, <&sdma 58>;
538 dma-names = "tx", "rx";
539 };
540
541 mmc5: mmc@480d5000 {
542 compatible = "ti,omap4-hsmmc";
543 reg = <0x480d5000 0x400>;
544 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
545 ti,hwmods = "mmc5";
546 ti,needs-special-reset;
547 dmas = <&sdma 59>, <&sdma 60>;
548 dma-names = "tx", "rx";
549 };
550
551 mmu_dsp: mmu@4a066000 {
552 compatible = "ti,omap4-iommu";
553 reg = <0x4a066000 0x100>;
554 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
555 ti,hwmods = "mmu_dsp";
556 };
557
558 mmu_ipu: mmu@55082000 {
559 compatible = "ti,omap4-iommu";
560 reg = <0x55082000 0x100>;
561 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
562 ti,hwmods = "mmu_ipu";
563 ti,iommu-bus-err-back;
564 };
565
566 keypad: keypad@4ae1c000 {
567 compatible = "ti,omap4-keypad";
568 reg = <0x4ae1c000 0x400>;
569 ti,hwmods = "kbd";
570 };
571
572 mcpdm: mcpdm@40132000 {
573 compatible = "ti,omap4-mcpdm";
574 reg = <0x40132000 0x7f>, /* MPU private access */
575 <0x49032000 0x7f>; /* L3 Interconnect */
576 reg-names = "mpu", "dma";
577 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
578 ti,hwmods = "mcpdm";
579 dmas = <&sdma 65>,
580 <&sdma 66>;
581 dma-names = "up_link", "dn_link";
582 status = "disabled";
583 };
584
585 dmic: dmic@4012e000 {
586 compatible = "ti,omap4-dmic";
587 reg = <0x4012e000 0x7f>, /* MPU private access */
588 <0x4902e000 0x7f>; /* L3 Interconnect */
589 reg-names = "mpu", "dma";
590 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
591 ti,hwmods = "dmic";
592 dmas = <&sdma 67>;
593 dma-names = "up_link";
594 status = "disabled";
595 };
596
597 mcbsp1: mcbsp@40122000 {
598 compatible = "ti,omap4-mcbsp";
599 reg = <0x40122000 0xff>, /* MPU private access */
600 <0x49022000 0xff>; /* L3 Interconnect */
601 reg-names = "mpu", "dma";
602 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
603 interrupt-names = "common";
604 ti,buffer-size = <128>;
605 ti,hwmods = "mcbsp1";
606 dmas = <&sdma 33>,
607 <&sdma 34>;
608 dma-names = "tx", "rx";
609 status = "disabled";
610 };
611
612 mcbsp2: mcbsp@40124000 {
613 compatible = "ti,omap4-mcbsp";
614 reg = <0x40124000 0xff>, /* MPU private access */
615 <0x49024000 0xff>; /* L3 Interconnect */
616 reg-names = "mpu", "dma";
617 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
618 interrupt-names = "common";
619 ti,buffer-size = <128>;
620 ti,hwmods = "mcbsp2";
621 dmas = <&sdma 17>,
622 <&sdma 18>;
623 dma-names = "tx", "rx";
624 status = "disabled";
625 };
626
627 mcbsp3: mcbsp@40126000 {
628 compatible = "ti,omap4-mcbsp";
629 reg = <0x40126000 0xff>, /* MPU private access */
630 <0x49026000 0xff>; /* L3 Interconnect */
631 reg-names = "mpu", "dma";
632 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
633 interrupt-names = "common";
634 ti,buffer-size = <128>;
635 ti,hwmods = "mcbsp3";
636 dmas = <&sdma 19>,
637 <&sdma 20>;
638 dma-names = "tx", "rx";
639 status = "disabled";
640 };
641
642 mailbox: mailbox@4a0f4000 {
643 compatible = "ti,omap4-mailbox";
644 reg = <0x4a0f4000 0x200>;
645 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
646 ti,hwmods = "mailbox";
647 ti,mbox-num-users = <3>;
648 ti,mbox-num-fifos = <8>;
649 mbox_ipu: mbox_ipu {
650 ti,mbox-tx = <0 0 0>;
651 ti,mbox-rx = <1 0 0>;
652 };
653 mbox_dsp: mbox_dsp {
654 ti,mbox-tx = <3 0 0>;
655 ti,mbox-rx = <2 0 0>;
656 };
657 };
658
659 timer1: timer@4ae18000 {
660 compatible = "ti,omap5430-timer";
661 reg = <0x4ae18000 0x80>;
662 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
663 ti,hwmods = "timer1";
664 ti,timer-alwon;
665 };
666
667 timer2: timer@48032000 {
668 compatible = "ti,omap5430-timer";
669 reg = <0x48032000 0x80>;
670 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
671 ti,hwmods = "timer2";
672 };
673
674 timer3: timer@48034000 {
675 compatible = "ti,omap5430-timer";
676 reg = <0x48034000 0x80>;
677 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
678 ti,hwmods = "timer3";
679 };
680
681 timer4: timer@48036000 {
682 compatible = "ti,omap5430-timer";
683 reg = <0x48036000 0x80>;
684 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
685 ti,hwmods = "timer4";
686 };
687
688 timer5: timer@40138000 {
689 compatible = "ti,omap5430-timer";
690 reg = <0x40138000 0x80>,
691 <0x49038000 0x80>;
692 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
693 ti,hwmods = "timer5";
694 ti,timer-dsp;
695 ti,timer-pwm;
696 };
697
698 timer6: timer@4013a000 {
699 compatible = "ti,omap5430-timer";
700 reg = <0x4013a000 0x80>,
701 <0x4903a000 0x80>;
702 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
703 ti,hwmods = "timer6";
704 ti,timer-dsp;
705 ti,timer-pwm;
706 };
707
708 timer7: timer@4013c000 {
709 compatible = "ti,omap5430-timer";
710 reg = <0x4013c000 0x80>,
711 <0x4903c000 0x80>;
712 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
713 ti,hwmods = "timer7";
714 ti,timer-dsp;
715 };
716
717 timer8: timer@4013e000 {
718 compatible = "ti,omap5430-timer";
719 reg = <0x4013e000 0x80>,
720 <0x4903e000 0x80>;
721 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
722 ti,hwmods = "timer8";
723 ti,timer-dsp;
724 ti,timer-pwm;
725 };
726
727 timer9: timer@4803e000 {
728 compatible = "ti,omap5430-timer";
729 reg = <0x4803e000 0x80>;
730 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
731 ti,hwmods = "timer9";
732 ti,timer-pwm;
733 };
734
735 timer10: timer@48086000 {
736 compatible = "ti,omap5430-timer";
737 reg = <0x48086000 0x80>;
738 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
739 ti,hwmods = "timer10";
740 ti,timer-pwm;
741 };
742
743 timer11: timer@48088000 {
744 compatible = "ti,omap5430-timer";
745 reg = <0x48088000 0x80>;
746 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
747 ti,hwmods = "timer11";
748 ti,timer-pwm;
749 };
750
751 wdt2: wdt@4ae14000 {
752 compatible = "ti,omap5-wdt", "ti,omap3-wdt";
753 reg = <0x4ae14000 0x80>;
754 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
755 ti,hwmods = "wd_timer2";
756 };
757
758 dmm@4e000000 {
759 compatible = "ti,omap5-dmm";
760 reg = <0x4e000000 0x800>;
761 interrupts = <0 113 0x4>;
762 ti,hwmods = "dmm";
763 };
764
765 emif1: emif@4c000000 {
766 compatible = "ti,emif-4d5";
767 ti,hwmods = "emif1";
768 ti,no-idle-on-init;
769 phy-type = <2>; /* DDR PHY type: Intelli PHY */
770 reg = <0x4c000000 0x400>;
771 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
772 hw-caps-read-idle-ctrl;
773 hw-caps-ll-interface;
774 hw-caps-temp-alert;
775 };
776
777 emif2: emif@4d000000 {
778 compatible = "ti,emif-4d5";
779 ti,hwmods = "emif2";
780 ti,no-idle-on-init;
781 phy-type = <2>; /* DDR PHY type: Intelli PHY */
782 reg = <0x4d000000 0x400>;
783 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
784 hw-caps-read-idle-ctrl;
785 hw-caps-ll-interface;
786 hw-caps-temp-alert;
787 };
788
789 omap_control_usb2phy: control-phy@4a002300 {
790 compatible = "ti,control-phy-usb2";
791 reg = <0x4a002300 0x4>;
792 reg-names = "power";
793 };
794
795 omap_control_usb3phy: control-phy@4a002370 {
796 compatible = "ti,control-phy-pipe3";
797 reg = <0x4a002370 0x4>;
798 reg-names = "power";
799 };
800
801 usb3: omap_dwc3@4a020000 {
802 compatible = "ti,dwc3";
803 ti,hwmods = "usb_otg_ss";
804 reg = <0x4a020000 0x10000>;
805 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
806 #address-cells = <1>;
807 #size-cells = <1>;
808 utmi-mode = <2>;
809 ranges;
810 dwc3@4a030000 {
811 compatible = "snps,dwc3";
812 reg = <0x4a030000 0x10000>;
813 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
814 phys = <&usb2_phy>, <&usb3_phy>;
815 phy-names = "usb2-phy", "usb3-phy";
816 dr_mode = "peripheral";
817 tx-fifo-resize;
818 };
819 };
820
821 ocp2scp@4a080000 {
822 compatible = "ti,omap-ocp2scp";
823 #address-cells = <1>;
824 #size-cells = <1>;
825 reg = <0x4a080000 0x20>;
826 ranges;
827 ti,hwmods = "ocp2scp1";
828 usb2_phy: usb2phy@4a084000 {
829 compatible = "ti,omap-usb2";
830 reg = <0x4a084000 0x7c>;
831 ctrl-module = <&omap_control_usb2phy>;
832 clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
833 clock-names = "wkupclk", "refclk";
834 #phy-cells = <0>;
835 };
836
837 usb3_phy: usb3phy@4a084400 {
838 compatible = "ti,omap-usb3";
839 reg = <0x4a084400 0x80>,
840 <0x4a084800 0x64>,
841 <0x4a084c00 0x40>;
842 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
843 ctrl-module = <&omap_control_usb3phy>;
844 clocks = <&usb_phy_cm_clk32k>,
845 <&sys_clkin>,
846 <&usb_otg_ss_refclk960m>;
847 clock-names = "wkupclk",
848 "sysclk",
849 "refclk";
850 #phy-cells = <0>;
851 };
852 };
853
854 usbhstll: usbhstll@4a062000 {
855 compatible = "ti,usbhs-tll";
856 reg = <0x4a062000 0x1000>;
857 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
858 ti,hwmods = "usb_tll_hs";
859 };
860
861 usbhshost: usbhshost@4a064000 {
862 compatible = "ti,usbhs-host";
863 reg = <0x4a064000 0x800>;
864 ti,hwmods = "usb_host_hs";
865 #address-cells = <1>;
866 #size-cells = <1>;
867 ranges;
868 clocks = <&l3init_60m_fclk>,
869 <&xclk60mhsp1_ck>,
870 <&xclk60mhsp2_ck>;
871 clock-names = "refclk_60m_int",
872 "refclk_60m_ext_p1",
873 "refclk_60m_ext_p2";
874
875 usbhsohci: ohci@4a064800 {
876 compatible = "ti,ohci-omap3";
877 reg = <0x4a064800 0x400>;
878 interrupt-parent = <&gic>;
879 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
880 };
881
882 usbhsehci: ehci@4a064c00 {
883 compatible = "ti,ehci-omap";
884 reg = <0x4a064c00 0x400>;
885 interrupt-parent = <&gic>;
886 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
887 };
888 };
889
890 bandgap: bandgap@4a0021e0 {
891 reg = <0x4a0021e0 0xc
892 0x4a00232c 0xc
893 0x4a002380 0x2c
894 0x4a0023C0 0x3c>;
895 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
896 compatible = "ti,omap5430-bandgap";
897
898 #thermal-sensor-cells = <1>;
899 };
900
901 omap_control_sata: control-phy@4a002374 {
902 compatible = "ti,control-phy-pipe3";
903 reg = <0x4a002374 0x4>;
904 reg-names = "power";
905 clocks = <&sys_clkin>;
906 clock-names = "sysclk";
907 };
908
909 /* OCP2SCP3 */
910 ocp2scp@4a090000 {
911 compatible = "ti,omap-ocp2scp";
912 #address-cells = <1>;
913 #size-cells = <1>;
914 reg = <0x4a090000 0x20>;
915 ranges;
916 ti,hwmods = "ocp2scp3";
917 sata_phy: phy@4a096000 {
918 compatible = "ti,phy-pipe3-sata";
919 reg = <0x4A096000 0x80>, /* phy_rx */
920 <0x4A096400 0x64>, /* phy_tx */
921 <0x4A096800 0x40>; /* pll_ctrl */
922 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
923 ctrl-module = <&omap_control_sata>;
924 clocks = <&sys_clkin>;
925 clock-names = "sysclk";
926 #phy-cells = <0>;
927 };
928 };
929
930 sata: sata@4a141100 {
931 compatible = "snps,dwc-ahci";
932 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
933 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
934 phys = <&sata_phy>;
935 phy-names = "sata-phy";
936 clocks = <&sata_ref_clk>;
937 ti,hwmods = "sata";
938 };
939
940 dss: dss@58000000 {
941 compatible = "ti,omap5-dss";
942 reg = <0x58000000 0x80>;
943 status = "disabled";
944 ti,hwmods = "dss_core";
945 clocks = <&dss_dss_clk>;
946 clock-names = "fck";
947 #address-cells = <1>;
948 #size-cells = <1>;
949 ranges;
950
951 dispc@58001000 {
952 compatible = "ti,omap5-dispc";
953 reg = <0x58001000 0x1000>;
954 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
955 ti,hwmods = "dss_dispc";
956 clocks = <&dss_dss_clk>;
957 clock-names = "fck";
958 };
959
960 rfbi: encoder@58002000 {
961 compatible = "ti,omap5-rfbi";
962 reg = <0x58002000 0x100>;
963 status = "disabled";
964 ti,hwmods = "dss_rfbi";
965 clocks = <&dss_dss_clk>, <&l3_iclk_div>;
966 clock-names = "fck", "ick";
967 };
968
969 dsi1: encoder@58004000 {
970 compatible = "ti,omap5-dsi";
971 reg = <0x58004000 0x200>,
972 <0x58004200 0x40>,
973 <0x58004300 0x40>;
974 reg-names = "proto", "phy", "pll";
975 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
976 status = "disabled";
977 ti,hwmods = "dss_dsi1";
978 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
979 clock-names = "fck", "sys_clk";
980 };
981
982 dsi2: encoder@58005000 {
983 compatible = "ti,omap5-dsi";
984 reg = <0x58009000 0x200>,
985 <0x58009200 0x40>,
986 <0x58009300 0x40>;
987 reg-names = "proto", "phy", "pll";
988 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
989 status = "disabled";
990 ti,hwmods = "dss_dsi2";
991 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
992 clock-names = "fck", "sys_clk";
993 };
994
995 hdmi: encoder@58060000 {
996 compatible = "ti,omap5-hdmi";
997 reg = <0x58040000 0x200>,
998 <0x58040200 0x80>,
999 <0x58040300 0x80>,
1000 <0x58060000 0x19000>;
1001 reg-names = "wp", "pll", "phy", "core";
1002 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1003 status = "disabled";
1004 ti,hwmods = "dss_hdmi";
1005 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
1006 clock-names = "fck", "sys_clk";
1007 dmas = <&sdma 76>;
1008 dma-names = "audio_tx";
1009 };
1010 };
1011
1012 abb_mpu: regulator-abb-mpu {
1013 compatible = "ti,abb-v2";
1014 regulator-name = "abb_mpu";
1015 #address-cells = <0>;
1016 #size-cells = <0>;
1017 clocks = <&sys_clkin>;
1018 ti,settling-time = <50>;
1019 ti,clock-cycles = <16>;
1020
1021 reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
1022 <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
1023 reg-names = "base-address", "int-address",
1024 "efuse-address", "ldo-address";
1025 ti,tranxdone-status-mask = <0x80>;
1026 /* LDOVBBMPU_MUX_CTRL */
1027 ti,ldovbb-override-mask = <0x400>;
1028 /* LDOVBBMPU_VSET_OUT */
1029 ti,ldovbb-vset-mask = <0x1F>;
1030
1031 /*
1032 * NOTE: only FBB mode used but actual vset will
1033 * determine final biasing
1034 */
1035 ti,abb_info = <
1036 /*uV ABB efuse rbb_m fbb_m vset_m*/
1037 1060000 0 0x0 0 0x02000000 0x01F00000
1038 1250000 0 0x4 0 0x02000000 0x01F00000
1039 >;
1040 };
1041
1042 abb_mm: regulator-abb-mm {
1043 compatible = "ti,abb-v2";
1044 regulator-name = "abb_mm";
1045 #address-cells = <0>;
1046 #size-cells = <0>;
1047 clocks = <&sys_clkin>;
1048 ti,settling-time = <50>;
1049 ti,clock-cycles = <16>;
1050
1051 reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
1052 <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
1053 reg-names = "base-address", "int-address",
1054 "efuse-address", "ldo-address";
1055 ti,tranxdone-status-mask = <0x80000000>;
1056 /* LDOVBBMM_MUX_CTRL */
1057 ti,ldovbb-override-mask = <0x400>;
1058 /* LDOVBBMM_VSET_OUT */
1059 ti,ldovbb-vset-mask = <0x1F>;
1060
1061 /*
1062 * NOTE: only FBB mode used but actual vset will
1063 * determine final biasing
1064 */
1065 ti,abb_info = <
1066 /*uV ABB efuse rbb_m fbb_m vset_m*/
1067 1025000 0 0x0 0 0x02000000 0x01F00000
1068 1120000 0 0x4 0 0x02000000 0x01F00000
1069 >;
1070 };
1071 };
1072 };
1073
1074 /include/ "omap54xx-clocks.dtsi"
Linux kernel - Deliverables
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