arch/arm/boot/dts/omap5.dtsi

   1 /*
   2  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include <dt-bindings/pinctrl/omap.h>
  13
  14 #include "skeleton.dtsi"
  15
  16 / {
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         compatible = "ti,omap5";
  21         interrupt-parent = <&gic>;
  22
  23         aliases {
  24                 i2c0 = &i2c1;
  25                 i2c1 = &i2c2;
  26                 i2c2 = &i2c3;
  27                 i2c3 = &i2c4;
  28                 i2c4 = &i2c5;
  29                 serial0 = &uart1;
  30                 serial1 = &uart2;
  31                 serial2 = &uart3;
  32                 serial3 = &uart4;
  33                 serial4 = &uart5;
  34                 serial5 = &uart6;
  35         };
  36
  37         cpus {
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40
  41                 cpu0: cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a15";
  44                         reg = <0x0>;
  45
  46                         operating-points = <
  47                                 /* kHz    uV */
  48                                 500000  880000
  49                                 1000000 1060000
  50                                 1500000 1250000
  51                         >;
  52
  53                         clocks = <&dpll_mpu_ck>;
  54                         clock-names = "cpu";
  55
  56                         clock-latency = <300000>; /* From omap-cpufreq driver */
  57
  58                         /* cooling options */
  59                         cooling-min-level = <0>;
  60                         cooling-max-level = <2>;
  61                         #cooling-cells = <2>; /* min followed by max */
  62                 };
  63                 cpu@1 {
  64                         device_type = "cpu";
  65                         compatible = "arm,cortex-a15";
  66                         reg = <0x1>;
  67                 };
  68         };
  69
  70         thermal-zones {
  71                 #include "omap4-cpu-thermal.dtsi"
  72                 #include "omap5-gpu-thermal.dtsi"
  73                 #include "omap5-core-thermal.dtsi"
  74         };
  75
  76         timer {
  77                 compatible = "arm,armv7-timer";
  78                 /* PPI secure/nonsecure IRQ */
  79                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  80                              <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  81                              <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  82                              <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
  83         };
  84
  85         gic: interrupt-controller@48211000 {
  86                 compatible = "arm,cortex-a15-gic";
  87                 interrupt-controller;
  88                 #interrupt-cells = <3>;
  89                 reg = <0x48211000 0x1000>,
  90                       <0x48212000 0x1000>,
  91                       <0x48214000 0x2000>,
  92                       <0x48216000 0x2000>;
  93         };
  94
  95         /*
  96          * The soc node represents the soc top level view. It is used for IPs
  97          * that are not memory mapped in the MPU view or for the MPU itself.
  98          */
  99         soc {
 100                 compatible = "ti,omap-infra";
 101                 mpu {
 102                         compatible = "ti,omap5-mpu";
 103                         ti,hwmods = "mpu";
 104                 };
 105         };
 106
 107         /*
 108          * XXX: Use a flat representation of the OMAP3 interconnect.
 109          * The real OMAP interconnect network is quite complex.
 110          * Since it will not bring real advantage to represent that in DT for
 111          * the moment, just use a fake OCP bus entry to represent the whole bus
 112          * hierarchy.
 113          */
 114         ocp {
 115                 compatible = "ti,omap4-l3-noc", "simple-bus";
 116                 #address-cells = <1>;
 117                 #size-cells = <1>;
 118                 ranges;
 119                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
 120                 reg = <0x44000000 0x2000>,
 121                       <0x44800000 0x3000>,
 122                       <0x45000000 0x4000>;
 123                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 124                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 125
 126                 prm: prm@4ae06000 {
 127                         compatible = "ti,omap5-prm";
 128                         reg = <0x4ae06000 0x3000>;
 129
 130                         prm_clocks: clocks {
 131                                 #address-cells = <1>;
 132                                 #size-cells = <0>;
 133                         };
 134
 135                         prm_clockdomains: clockdomains {
 136                         };
 137                 };
 138
 139                 cm_core_aon: cm_core_aon@4a004000 {
 140                         compatible = "ti,omap5-cm-core-aon";
 141                         reg = <0x4a004000 0x2000>;
 142
 143                         cm_core_aon_clocks: clocks {
 144                                 #address-cells = <1>;
 145                                 #size-cells = <0>;
 146                         };
 147
 148                         cm_core_aon_clockdomains: clockdomains {
 149                         };
 150                 };
 151
 152                 scrm: scrm@4ae0a000 {
 153                         compatible = "ti,omap5-scrm";
 154                         reg = <0x4ae0a000 0x2000>;
 155
 156                         scrm_clocks: clocks {
 157                                 #address-cells = <1>;
 158                                 #size-cells = <0>;
 159                         };
 160
 161                         scrm_clockdomains: clockdomains {
 162                         };
 163                 };
 164
 165                 cm_core: cm_core@4a008000 {
 166                         compatible = "ti,omap5-cm-core";
 167                         reg = <0x4a008000 0x3000>;
 168
 169                         cm_core_clocks: clocks {
 170                                 #address-cells = <1>;
 171                                 #size-cells = <0>;
 172                         };
 173
 174                         cm_core_clockdomains: clockdomains {
 175                         };
 176                 };
 177
 178                 counter32k: counter@4ae04000 {
 179                         compatible = "ti,omap-counter32k";
 180                         reg = <0x4ae04000 0x40>;
 181                         ti,hwmods = "counter_32k";
 182                 };
 183
 184                 omap5_pmx_core: pinmux@4a002840 {
 185                         compatible = "ti,omap4-padconf", "pinctrl-single";
 186                         reg = <0x4a002840 0x01b6>;
 187                         #address-cells = <1>;
 188                         #size-cells = <0>;
 189                         pinctrl-single,register-width = <16>;
 190                         pinctrl-single,function-mask = <0x7fff>;
 191                 };
 192                 omap5_pmx_wkup: pinmux@4ae0c840 {
 193                         compatible = "ti,omap4-padconf", "pinctrl-single";
 194                         reg = <0x4ae0c840 0x0038>;
 195                         #address-cells = <1>;
 196                         #size-cells = <0>;
 197                         pinctrl-single,register-width = <16>;
 198                         pinctrl-single,function-mask = <0x7fff>;
 199                 };
 200
 201                 omap5_padconf_global: tisyscon@4a002da0 {
 202                         compatible = "syscon";
 203                         reg = <0x4A002da0 0xec>;
 204                 };
 205
 206                 pbias_regulator: pbias_regulator {
 207                         compatible = "ti,pbias-omap";
 208                         reg = <0x60 0x4>;
 209                         syscon = <&omap5_padconf_global>;
 210                         pbias_mmc_reg: pbias_mmc_omap5 {
 211                                 regulator-name = "pbias_mmc_omap5";
 212                                 regulator-min-microvolt = <1800000>;
 213                                 regulator-max-microvolt = <3000000>;
 214                         };
 215                 };
 216
 217                 sdma: dma-controller@4a056000 {
 218                         compatible = "ti,omap4430-sdma";
 219                         reg = <0x4a056000 0x1000>;
 220                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 221                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 222                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 223                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 224                         #dma-cells = <1>;
 225                         #dma-channels = <32>;
 226                         #dma-requests = <127>;
 227                 };
 228
 229                 gpio1: gpio@4ae10000 {
 230                         compatible = "ti,omap4-gpio";
 231                         reg = <0x4ae10000 0x200>;
 232                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 233                         ti,hwmods = "gpio1";
 234                         ti,gpio-always-on;
 235                         gpio-controller;
 236                         #gpio-cells = <2>;
 237                         interrupt-controller;
 238                         #interrupt-cells = <2>;
 239                 };
 240
 241                 gpio2: gpio@48055000 {
 242                         compatible = "ti,omap4-gpio";
 243                         reg = <0x48055000 0x200>;
 244                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 245                         ti,hwmods = "gpio2";
 246                         gpio-controller;
 247                         #gpio-cells = <2>;
 248                         interrupt-controller;
 249                         #interrupt-cells = <2>;
 250                 };
 251
 252                 gpio3: gpio@48057000 {
 253                         compatible = "ti,omap4-gpio";
 254                         reg = <0x48057000 0x200>;
 255                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 256                         ti,hwmods = "gpio3";
 257                         gpio-controller;
 258                         #gpio-cells = <2>;
 259                         interrupt-controller;
 260                         #interrupt-cells = <2>;
 261                 };
 262
 263                 gpio4: gpio@48059000 {
 264                         compatible = "ti,omap4-gpio";
 265                         reg = <0x48059000 0x200>;
 266                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 267                         ti,hwmods = "gpio4";
 268                         gpio-controller;
 269                         #gpio-cells = <2>;
 270                         interrupt-controller;
 271                         #interrupt-cells = <2>;
 272                 };
 273
 274                 gpio5: gpio@4805b000 {
 275                         compatible = "ti,omap4-gpio";
 276                         reg = <0x4805b000 0x200>;
 277                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 278                         ti,hwmods = "gpio5";
 279                         gpio-controller;
 280                         #gpio-cells = <2>;
 281                         interrupt-controller;
 282                         #interrupt-cells = <2>;
 283                 };
 284
 285                 gpio6: gpio@4805d000 {
 286                         compatible = "ti,omap4-gpio";
 287                         reg = <0x4805d000 0x200>;
 288                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 289                         ti,hwmods = "gpio6";
 290                         gpio-controller;
 291                         #gpio-cells = <2>;
 292                         interrupt-controller;
 293                         #interrupt-cells = <2>;
 294                 };
 295
 296                 gpio7: gpio@48051000 {
 297                         compatible = "ti,omap4-gpio";
 298                         reg = <0x48051000 0x200>;
 299                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 300                         ti,hwmods = "gpio7";
 301                         gpio-controller;
 302                         #gpio-cells = <2>;
 303                         interrupt-controller;
 304                         #interrupt-cells = <2>;
 305                 };
 306
 307                 gpio8: gpio@48053000 {
 308                         compatible = "ti,omap4-gpio";
 309                         reg = <0x48053000 0x200>;
 310                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 311                         ti,hwmods = "gpio8";
 312                         gpio-controller;
 313                         #gpio-cells = <2>;
 314                         interrupt-controller;
 315                         #interrupt-cells = <2>;
 316                 };
 317
 318                 gpmc: gpmc@50000000 {
 319                         compatible = "ti,omap4430-gpmc";
 320                         reg = <0x50000000 0x1000>;
 321                         #address-cells = <2>;
 322                         #size-cells = <1>;
 323                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 324                         gpmc,num-cs = <8>;
 325                         gpmc,num-waitpins = <4>;
 326                         ti,hwmods = "gpmc";
 327                         clocks = <&l3_iclk_div>;
 328                         clock-names = "fck";
 329                 };
 330
 331                 i2c1: i2c@48070000 {
 332                         compatible = "ti,omap4-i2c";
 333                         reg = <0x48070000 0x100>;
 334                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 335                         #address-cells = <1>;
 336                         #size-cells = <0>;
 337                         ti,hwmods = "i2c1";
 338                 };
 339
 340                 i2c2: i2c@48072000 {
 341                         compatible = "ti,omap4-i2c";
 342                         reg = <0x48072000 0x100>;
 343                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 344                         #address-cells = <1>;
 345                         #size-cells = <0>;
 346                         ti,hwmods = "i2c2";
 347                 };
 348
 349                 i2c3: i2c@48060000 {
 350                         compatible = "ti,omap4-i2c";
 351                         reg = <0x48060000 0x100>;
 352                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 353                         #address-cells = <1>;
 354                         #size-cells = <0>;
 355                         ti,hwmods = "i2c3";
 356                 };
 357
 358                 i2c4: i2c@4807a000 {
 359                         compatible = "ti,omap4-i2c";
 360                         reg = <0x4807a000 0x100>;
 361                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 362                         #address-cells = <1>;
 363                         #size-cells = <0>;
 364                         ti,hwmods = "i2c4";
 365                 };
 366
 367                 i2c5: i2c@4807c000 {
 368                         compatible = "ti,omap4-i2c";
 369                         reg = <0x4807c000 0x100>;
 370                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 371                         #address-cells = <1>;
 372                         #size-cells = <0>;
 373                         ti,hwmods = "i2c5";
 374                 };
 375
 376                 hwspinlock: spinlock@4a0f6000 {
 377                         compatible = "ti,omap4-hwspinlock";
 378                         reg = <0x4a0f6000 0x1000>;
 379                         ti,hwmods = "spinlock";
 380                         #hwlock-cells = <1>;
 381                 };
 382
 383                 mcspi1: spi@48098000 {
 384                         compatible = "ti,omap4-mcspi";
 385                         reg = <0x48098000 0x200>;
 386                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 387                         #address-cells = <1>;
 388                         #size-cells = <0>;
 389                         ti,hwmods = "mcspi1";
 390                         ti,spi-num-cs = <4>;
 391                         dmas = <&sdma 35>,
 392                                <&sdma 36>,
 393                                <&sdma 37>,
 394                                <&sdma 38>,
 395                                <&sdma 39>,
 396                                <&sdma 40>,
 397                                <&sdma 41>,
 398                                <&sdma 42>;
 399                         dma-names = "tx0", "rx0", "tx1", "rx1",
 400                                     "tx2", "rx2", "tx3", "rx3";
 401                 };
 402
 403                 mcspi2: spi@4809a000 {
 404                         compatible = "ti,omap4-mcspi";
 405                         reg = <0x4809a000 0x200>;
 406                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 407                         #address-cells = <1>;
 408                         #size-cells = <0>;
 409                         ti,hwmods = "mcspi2";
 410                         ti,spi-num-cs = <2>;
 411                         dmas = <&sdma 43>,
 412                                <&sdma 44>,
 413                                <&sdma 45>,
 414                                <&sdma 46>;
 415                         dma-names = "tx0", "rx0", "tx1", "rx1";
 416                 };
 417
 418                 mcspi3: spi@480b8000 {
 419                         compatible = "ti,omap4-mcspi";
 420                         reg = <0x480b8000 0x200>;
 421                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 422                         #address-cells = <1>;
 423                         #size-cells = <0>;
 424                         ti,hwmods = "mcspi3";
 425                         ti,spi-num-cs = <2>;
 426                         dmas = <&sdma 15>, <&sdma 16>;
 427                         dma-names = "tx0", "rx0";
 428                 };
 429
 430                 mcspi4: spi@480ba000 {
 431                         compatible = "ti,omap4-mcspi";
 432                         reg = <0x480ba000 0x200>;
 433                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 434                         #address-cells = <1>;
 435                         #size-cells = <0>;
 436                         ti,hwmods = "mcspi4";
 437                         ti,spi-num-cs = <1>;
 438                         dmas = <&sdma 70>, <&sdma 71>;
 439                         dma-names = "tx0", "rx0";
 440                 };
 441
 442                 uart1: serial@4806a000 {
 443                         compatible = "ti,omap4-uart";
 444                         reg = <0x4806a000 0x100>;
 445                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 446                         ti,hwmods = "uart1";
 447                         clock-frequency = <48000000>;
 448                 };
 449
 450                 uart2: serial@4806c000 {
 451                         compatible = "ti,omap4-uart";
 452                         reg = <0x4806c000 0x100>;
 453                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 454                         ti,hwmods = "uart2";
 455                         clock-frequency = <48000000>;
 456                 };
 457
 458                 uart3: serial@48020000 {
 459                         compatible = "ti,omap4-uart";
 460                         reg = <0x48020000 0x100>;
 461                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 462                         ti,hwmods = "uart3";
 463                         clock-frequency = <48000000>;
 464                 };
 465
 466                 uart4: serial@4806e000 {
 467                         compatible = "ti,omap4-uart";
 468                         reg = <0x4806e000 0x100>;
 469                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 470                         ti,hwmods = "uart4";
 471                         clock-frequency = <48000000>;
 472                 };
 473
 474                 uart5: serial@48066000 {
 475                         compatible = "ti,omap4-uart";
 476                         reg = <0x48066000 0x100>;
 477                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 478                         ti,hwmods = "uart5";
 479                         clock-frequency = <48000000>;
 480                 };
 481
 482                 uart6: serial@48068000 {
 483                         compatible = "ti,omap4-uart";
 484                         reg = <0x48068000 0x100>;
 485                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 486                         ti,hwmods = "uart6";
 487                         clock-frequency = <48000000>;
 488                 };
 489
 490                 mmc1: mmc@4809c000 {
 491                         compatible = "ti,omap4-hsmmc";
 492                         reg = <0x4809c000 0x400>;
 493                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 494                         ti,hwmods = "mmc1";
 495                         ti,dual-volt;
 496                         ti,needs-special-reset;
 497                         dmas = <&sdma 61>, <&sdma 62>;
 498                         dma-names = "tx", "rx";
 499                         pbias-supply = <&pbias_mmc_reg>;
 500                 };
 501
 502                 mmc2: mmc@480b4000 {
 503                         compatible = "ti,omap4-hsmmc";
 504                         reg = <0x480b4000 0x400>;
 505                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 506                         ti,hwmods = "mmc2";
 507                         ti,needs-special-reset;
 508                         dmas = <&sdma 47>, <&sdma 48>;
 509                         dma-names = "tx", "rx";
 510                 };
 511
 512                 mmc3: mmc@480ad000 {
 513                         compatible = "ti,omap4-hsmmc";
 514                         reg = <0x480ad000 0x400>;
 515                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 516                         ti,hwmods = "mmc3";
 517                         ti,needs-special-reset;
 518                         dmas = <&sdma 77>, <&sdma 78>;
 519                         dma-names = "tx", "rx";
 520                 };
 521
 522                 mmc4: mmc@480d1000 {
 523                         compatible = "ti,omap4-hsmmc";
 524                         reg = <0x480d1000 0x400>;
 525                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 526                         ti,hwmods = "mmc4";
 527                         ti,needs-special-reset;
 528                         dmas = <&sdma 57>, <&sdma 58>;
 529                         dma-names = "tx", "rx";
 530                 };
 531
 532                 mmc5: mmc@480d5000 {
 533                         compatible = "ti,omap4-hsmmc";
 534                         reg = <0x480d5000 0x400>;
 535                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 536                         ti,hwmods = "mmc5";
 537                         ti,needs-special-reset;
 538                         dmas = <&sdma 59>, <&sdma 60>;
 539                         dma-names = "tx", "rx";
 540                 };
 541
 542                 mmu_dsp: mmu@4a066000 {
 543                         compatible = "ti,omap4-iommu";
 544                         reg = <0x4a066000 0x100>;
 545                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 546                         ti,hwmods = "mmu_dsp";
 547                 };
 548
 549                 mmu_ipu: mmu@55082000 {
 550                         compatible = "ti,omap4-iommu";
 551                         reg = <0x55082000 0x100>;
 552                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 553                         ti,hwmods = "mmu_ipu";
 554                         ti,iommu-bus-err-back;
 555                 };
 556
 557                 keypad: keypad@4ae1c000 {
 558                         compatible = "ti,omap4-keypad";
 559                         reg = <0x4ae1c000 0x400>;
 560                         ti,hwmods = "kbd";
 561                 };
 562
 563                 mcpdm: mcpdm@40132000 {
 564                         compatible = "ti,omap4-mcpdm";
 565                         reg = <0x40132000 0x7f>, /* MPU private access */
 566                               <0x49032000 0x7f>; /* L3 Interconnect */
 567                         reg-names = "mpu", "dma";
 568                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 569                         ti,hwmods = "mcpdm";
 570                         dmas = <&sdma 65>,
 571                                <&sdma 66>;
 572                         dma-names = "up_link", "dn_link";
 573                         status = "disabled";
 574                 };
 575
 576                 dmic: dmic@4012e000 {
 577                         compatible = "ti,omap4-dmic";
 578                         reg = <0x4012e000 0x7f>, /* MPU private access */
 579                               <0x4902e000 0x7f>; /* L3 Interconnect */
 580                         reg-names = "mpu", "dma";
 581                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 582                         ti,hwmods = "dmic";
 583                         dmas = <&sdma 67>;
 584                         dma-names = "up_link";
 585                         status = "disabled";
 586                 };
 587
 588                 mcbsp1: mcbsp@40122000 {
 589                         compatible = "ti,omap4-mcbsp";
 590                         reg = <0x40122000 0xff>, /* MPU private access */
 591                               <0x49022000 0xff>; /* L3 Interconnect */
 592                         reg-names = "mpu", "dma";
 593                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 594                         interrupt-names = "common";
 595                         ti,buffer-size = <128>;
 596                         ti,hwmods = "mcbsp1";
 597                         dmas = <&sdma 33>,
 598                                <&sdma 34>;
 599                         dma-names = "tx", "rx";
 600                         status = "disabled";
 601                 };
 602
 603                 mcbsp2: mcbsp@40124000 {
 604                         compatible = "ti,omap4-mcbsp";
 605                         reg = <0x40124000 0xff>, /* MPU private access */
 606                               <0x49024000 0xff>; /* L3 Interconnect */
 607                         reg-names = "mpu", "dma";
 608                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 609                         interrupt-names = "common";
 610                         ti,buffer-size = <128>;
 611                         ti,hwmods = "mcbsp2";
 612                         dmas = <&sdma 17>,
 613                                <&sdma 18>;
 614                         dma-names = "tx", "rx";
 615                         status = "disabled";
 616                 };
 617
 618                 mcbsp3: mcbsp@40126000 {
 619                         compatible = "ti,omap4-mcbsp";
 620                         reg = <0x40126000 0xff>, /* MPU private access */
 621                               <0x49026000 0xff>; /* L3 Interconnect */
 622                         reg-names = "mpu", "dma";
 623                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 624                         interrupt-names = "common";
 625                         ti,buffer-size = <128>;
 626                         ti,hwmods = "mcbsp3";
 627                         dmas = <&sdma 19>,
 628                                <&sdma 20>;
 629                         dma-names = "tx", "rx";
 630                         status = "disabled";
 631                 };
 632
 633                 mailbox: mailbox@4a0f4000 {
 634                         compatible = "ti,omap4-mailbox";
 635                         reg = <0x4a0f4000 0x200>;
 636                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 637                         ti,hwmods = "mailbox";
 638                 };
 639
 640                 timer1: timer@4ae18000 {
 641                         compatible = "ti,omap5430-timer";
 642                         reg = <0x4ae18000 0x80>;
 643                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 644                         ti,hwmods = "timer1";
 645                         ti,timer-alwon;
 646                 };
 647
 648                 timer2: timer@48032000 {
 649                         compatible = "ti,omap5430-timer";
 650                         reg = <0x48032000 0x80>;
 651                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 652                         ti,hwmods = "timer2";
 653                 };
 654
 655                 timer3: timer@48034000 {
 656                         compatible = "ti,omap5430-timer";
 657                         reg = <0x48034000 0x80>;
 658                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 659                         ti,hwmods = "timer3";
 660                 };
 661
 662                 timer4: timer@48036000 {
 663                         compatible = "ti,omap5430-timer";
 664                         reg = <0x48036000 0x80>;
 665                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 666                         ti,hwmods = "timer4";
 667                 };
 668
 669                 timer5: timer@40138000 {
 670                         compatible = "ti,omap5430-timer";
 671                         reg = <0x40138000 0x80>,
 672                               <0x49038000 0x80>;
 673                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 674                         ti,hwmods = "timer5";
 675                         ti,timer-dsp;
 676                         ti,timer-pwm;
 677                 };
 678
 679                 timer6: timer@4013a000 {
 680                         compatible = "ti,omap5430-timer";
 681                         reg = <0x4013a000 0x80>,
 682                               <0x4903a000 0x80>;
 683                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 684                         ti,hwmods = "timer6";
 685                         ti,timer-dsp;
 686                         ti,timer-pwm;
 687                 };
 688
 689                 timer7: timer@4013c000 {
 690                         compatible = "ti,omap5430-timer";
 691                         reg = <0x4013c000 0x80>,
 692                               <0x4903c000 0x80>;
 693                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 694                         ti,hwmods = "timer7";
 695                         ti,timer-dsp;
 696                 };
 697
 698                 timer8: timer@4013e000 {
 699                         compatible = "ti,omap5430-timer";
 700                         reg = <0x4013e000 0x80>,
 701                               <0x4903e000 0x80>;
 702                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 703                         ti,hwmods = "timer8";
 704                         ti,timer-dsp;
 705                         ti,timer-pwm;
 706                 };
 707
 708                 timer9: timer@4803e000 {
 709                         compatible = "ti,omap5430-timer";
 710                         reg = <0x4803e000 0x80>;
 711                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 712                         ti,hwmods = "timer9";
 713                         ti,timer-pwm;
 714                 };
 715
 716                 timer10: timer@48086000 {
 717                         compatible = "ti,omap5430-timer";
 718                         reg = <0x48086000 0x80>;
 719                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 720                         ti,hwmods = "timer10";
 721                         ti,timer-pwm;
 722                 };
 723
 724                 timer11: timer@48088000 {
 725                         compatible = "ti,omap5430-timer";
 726                         reg = <0x48088000 0x80>;
 727                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 728                         ti,hwmods = "timer11";
 729                         ti,timer-pwm;
 730                 };
 731
 732                 wdt2: wdt@4ae14000 {
 733                         compatible = "ti,omap5-wdt", "ti,omap3-wdt";
 734                         reg = <0x4ae14000 0x80>;
 735                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 736                         ti,hwmods = "wd_timer2";
 737                 };
 738
 739                 dmm@4e000000 {
 740                         compatible = "ti,omap5-dmm";
 741                         reg = <0x4e000000 0x800>;
 742                         interrupts = <0 113 0x4>;
 743                         ti,hwmods = "dmm";
 744                 };
 745
 746                 emif1: emif@4c000000 {
 747                         compatible      = "ti,emif-4d5";
 748                         ti,hwmods       = "emif1";
 749                         ti,no-idle-on-init;
 750                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 751                         reg = <0x4c000000 0x400>;
 752                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 753                         hw-caps-read-idle-ctrl;
 754                         hw-caps-ll-interface;
 755                         hw-caps-temp-alert;
 756                 };
 757
 758                 emif2: emif@4d000000 {
 759                         compatible      = "ti,emif-4d5";
 760                         ti,hwmods       = "emif2";
 761                         ti,no-idle-on-init;
 762                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 763                         reg = <0x4d000000 0x400>;
 764                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 765                         hw-caps-read-idle-ctrl;
 766                         hw-caps-ll-interface;
 767                         hw-caps-temp-alert;
 768                 };
 769
 770                 omap_control_usb2phy: control-phy@4a002300 {
 771                         compatible = "ti,control-phy-usb2";
 772                         reg = <0x4a002300 0x4>;
 773                         reg-names = "power";
 774                 };
 775
 776                 omap_control_usb3phy: control-phy@4a002370 {
 777                         compatible = "ti,control-phy-pipe3";
 778                         reg = <0x4a002370 0x4>;
 779                         reg-names = "power";
 780                 };
 781
 782                 usb3: omap_dwc3@4a020000 {
 783                         compatible = "ti,dwc3";
 784                         ti,hwmods = "usb_otg_ss";
 785                         reg = <0x4a020000 0x10000>;
 786                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 787                         #address-cells = <1>;
 788                         #size-cells = <1>;
 789                         utmi-mode = <2>;
 790                         ranges;
 791                         dwc3@4a030000 {
 792                                 compatible = "snps,dwc3";
 793                                 reg = <0x4a030000 0x10000>;
 794                                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 795                                 phys = <&usb2_phy>, <&usb3_phy>;
 796                                 phy-names = "usb2-phy", "usb3-phy";
 797                                 dr_mode = "peripheral";
 798                                 tx-fifo-resize;
 799                         };
 800                 };
 801
 802                 ocp2scp@4a080000 {
 803                         compatible = "ti,omap-ocp2scp";
 804                         #address-cells = <1>;
 805                         #size-cells = <1>;
 806                         reg = <0x4a080000 0x20>;
 807                         ranges;
 808                         ti,hwmods = "ocp2scp1";
 809                         usb2_phy: usb2phy@4a084000 {
 810                                 compatible = "ti,omap-usb2";
 811                                 reg = <0x4a084000 0x7c>;
 812                                 ctrl-module = <&omap_control_usb2phy>;
 813                                 #phy-cells = <0>;
 814                         };
 815
 816                         usb3_phy: usb3phy@4a084400 {
 817                                 compatible = "ti,omap-usb3";
 818                                 reg = <0x4a084400 0x80>,
 819                                       <0x4a084800 0x64>,
 820                                       <0x4a084c00 0x40>;
 821                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
 822                                 ctrl-module = <&omap_control_usb3phy>;
 823                                 clocks = <&usb_phy_cm_clk32k>,
 824                                          <&sys_clkin>,
 825                                          <&usb_otg_ss_refclk960m>;
 826                                 clock-names =   "wkupclk",
 827                                                 "sysclk",
 828                                                 "refclk";
 829                                 #phy-cells = <0>;
 830                         };
 831                 };
 832
 833                 usbhstll: usbhstll@4a062000 {
 834                         compatible = "ti,usbhs-tll";
 835                         reg = <0x4a062000 0x1000>;
 836                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 837                         ti,hwmods = "usb_tll_hs";
 838                 };
 839
 840                 usbhshost: usbhshost@4a064000 {
 841                         compatible = "ti,usbhs-host";
 842                         reg = <0x4a064000 0x800>;
 843                         ti,hwmods = "usb_host_hs";
 844                         #address-cells = <1>;
 845                         #size-cells = <1>;
 846                         ranges;
 847                         clocks = <&l3init_60m_fclk>,
 848                                  <&xclk60mhsp1_ck>,
 849                                  <&xclk60mhsp2_ck>;
 850                         clock-names = "refclk_60m_int",
 851                                       "refclk_60m_ext_p1",
 852                                       "refclk_60m_ext_p2";
 853
 854                         usbhsohci: ohci@4a064800 {
 855                                 compatible = "ti,ohci-omap3";
 856                                 reg = <0x4a064800 0x400>;
 857                                 interrupt-parent = <&gic>;
 858                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 859                         };
 860
 861                         usbhsehci: ehci@4a064c00 {
 862                                 compatible = "ti,ehci-omap";
 863                                 reg = <0x4a064c00 0x400>;
 864                                 interrupt-parent = <&gic>;
 865                                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 866                         };
 867                 };
 868
 869                 bandgap: bandgap@4a0021e0 {
 870                         reg = <0x4a0021e0 0xc
 871                                0x4a00232c 0xc
 872                                0x4a002380 0x2c
 873                                0x4a0023C0 0x3c>;
 874                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 875                         compatible = "ti,omap5430-bandgap";
 876
 877                         #thermal-sensor-cells = <1>;
 878                 };
 879         };
 880 };
 881
 882 /include/ "omap54xx-clocks.dtsi"