projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
ARM: dts: omap5: Update CPU OPP table as per final production Manual
[deliverable/linux.git] / arch / arm / boot / dts / omap5.dtsi
1 /*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
9
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/pinctrl/omap.h>
13
14 #include "skeleton.dtsi"
15
16 / {
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 compatible = "ti,omap5";
21 interrupt-parent = <&gic>;
22
23 aliases {
24 i2c0 = &i2c1;
25 i2c1 = &i2c2;
26 i2c2 = &i2c3;
27 i2c3 = &i2c4;
28 i2c4 = &i2c5;
29 serial0 = &uart1;
30 serial1 = &uart2;
31 serial2 = &uart3;
32 serial3 = &uart4;
33 serial4 = &uart5;
34 serial5 = &uart6;
35 };
36
37 cpus {
38 #address-cells = <1>;
39 #size-cells = <0>;
40
41 cpu0: cpu@0 {
42 device_type = "cpu";
43 compatible = "arm,cortex-a15";
44 reg = <0x0>;
45
46 operating-points = <
47 /* kHz uV */
48 1000000 1060000
49 1500000 1250000
50 >;
51
52 clocks = <&dpll_mpu_ck>;
53 clock-names = "cpu";
54
55 clock-latency = <300000>; /* From omap-cpufreq driver */
56
57 /* cooling options */
58 cooling-min-level = <0>;
59 cooling-max-level = <2>;
60 #cooling-cells = <2>; /* min followed by max */
61 };
62 cpu@1 {
63 device_type = "cpu";
64 compatible = "arm,cortex-a15";
65 reg = <0x1>;
66 };
67 };
68
69 thermal-zones {
70 #include "omap4-cpu-thermal.dtsi"
71 #include "omap5-gpu-thermal.dtsi"
72 #include "omap5-core-thermal.dtsi"
73 };
74
75 timer {
76 compatible = "arm,armv7-timer";
77 /* PPI secure/nonsecure IRQ */
78 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
79 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
80 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
81 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
82 };
83
84 pmu {
85 compatible = "arm,cortex-a15-pmu";
86 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
87 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
88 };
89
90 gic: interrupt-controller@48211000 {
91 compatible = "arm,cortex-a15-gic";
92 interrupt-controller;
93 #interrupt-cells = <3>;
94 reg = <0x48211000 0x1000>,
95 <0x48212000 0x1000>,
96 <0x48214000 0x2000>,
97 <0x48216000 0x2000>;
98 };
99
100 /*
101 * The soc node represents the soc top level view. It is used for IPs
102 * that are not memory mapped in the MPU view or for the MPU itself.
103 */
104 soc {
105 compatible = "ti,omap-infra";
106 mpu {
107 compatible = "ti,omap5-mpu";
108 ti,hwmods = "mpu";
109 };
110 };
111
112 /*
113 * XXX: Use a flat representation of the OMAP3 interconnect.
114 * The real OMAP interconnect network is quite complex.
115 * Since it will not bring real advantage to represent that in DT for
116 * the moment, just use a fake OCP bus entry to represent the whole bus
117 * hierarchy.
118 */
119 ocp {
120 compatible = "ti,omap4-l3-noc", "simple-bus";
121 #address-cells = <1>;
122 #size-cells = <1>;
123 ranges;
124 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
125 reg = <0x44000000 0x2000>,
126 <0x44800000 0x3000>,
127 <0x45000000 0x4000>;
128 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
129 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
130
131 prm: prm@4ae06000 {
132 compatible = "ti,omap5-prm";
133 reg = <0x4ae06000 0x3000>;
134
135 prm_clocks: clocks {
136 #address-cells = <1>;
137 #size-cells = <0>;
138 };
139
140 prm_clockdomains: clockdomains {
141 };
142 };
143
144 cm_core_aon: cm_core_aon@4a004000 {
145 compatible = "ti,omap5-cm-core-aon";
146 reg = <0x4a004000 0x2000>;
147
148 cm_core_aon_clocks: clocks {
149 #address-cells = <1>;
150 #size-cells = <0>;
151 };
152
153 cm_core_aon_clockdomains: clockdomains {
154 };
155 };
156
157 scrm: scrm@4ae0a000 {
158 compatible = "ti,omap5-scrm";
159 reg = <0x4ae0a000 0x2000>;
160
161 scrm_clocks: clocks {
162 #address-cells = <1>;
163 #size-cells = <0>;
164 };
165
166 scrm_clockdomains: clockdomains {
167 };
168 };
169
170 cm_core: cm_core@4a008000 {
171 compatible = "ti,omap5-cm-core";
172 reg = <0x4a008000 0x3000>;
173
174 cm_core_clocks: clocks {
175 #address-cells = <1>;
176 #size-cells = <0>;
177 };
178
179 cm_core_clockdomains: clockdomains {
180 };
181 };
182
183 counter32k: counter@4ae04000 {
184 compatible = "ti,omap-counter32k";
185 reg = <0x4ae04000 0x40>;
186 ti,hwmods = "counter_32k";
187 };
188
189 omap5_pmx_core: pinmux@4a002840 {
190 compatible = "ti,omap4-padconf", "pinctrl-single";
191 reg = <0x4a002840 0x01b6>;
192 #address-cells = <1>;
193 #size-cells = <0>;
194 pinctrl-single,register-width = <16>;
195 pinctrl-single,function-mask = <0x7fff>;
196 };
197 omap5_pmx_wkup: pinmux@4ae0c840 {
198 compatible = "ti,omap4-padconf", "pinctrl-single";
199 reg = <0x4ae0c840 0x0038>;
200 #address-cells = <1>;
201 #size-cells = <0>;
202 pinctrl-single,register-width = <16>;
203 pinctrl-single,function-mask = <0x7fff>;
204 };
205
206 omap5_padconf_global: tisyscon@4a002da0 {
207 compatible = "syscon";
208 reg = <0x4A002da0 0xec>;
209 };
210
211 pbias_regulator: pbias_regulator {
212 compatible = "ti,pbias-omap";
213 reg = <0x60 0x4>;
214 syscon = <&omap5_padconf_global>;
215 pbias_mmc_reg: pbias_mmc_omap5 {
216 regulator-name = "pbias_mmc_omap5";
217 regulator-min-microvolt = <1800000>;
218 regulator-max-microvolt = <3000000>;
219 };
220 };
221
222 sdma: dma-controller@4a056000 {
223 compatible = "ti,omap4430-sdma";
224 reg = <0x4a056000 0x1000>;
225 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
226 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
227 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
228 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
229 #dma-cells = <1>;
230 #dma-channels = <32>;
231 #dma-requests = <127>;
232 };
233
234 gpio1: gpio@4ae10000 {
235 compatible = "ti,omap4-gpio";
236 reg = <0x4ae10000 0x200>;
237 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
238 ti,hwmods = "gpio1";
239 ti,gpio-always-on;
240 gpio-controller;
241 #gpio-cells = <2>;
242 interrupt-controller;
243 #interrupt-cells = <2>;
244 };
245
246 gpio2: gpio@48055000 {
247 compatible = "ti,omap4-gpio";
248 reg = <0x48055000 0x200>;
249 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
250 ti,hwmods = "gpio2";
251 gpio-controller;
252 #gpio-cells = <2>;
253 interrupt-controller;
254 #interrupt-cells = <2>;
255 };
256
257 gpio3: gpio@48057000 {
258 compatible = "ti,omap4-gpio";
259 reg = <0x48057000 0x200>;
260 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
261 ti,hwmods = "gpio3";
262 gpio-controller;
263 #gpio-cells = <2>;
264 interrupt-controller;
265 #interrupt-cells = <2>;
266 };
267
268 gpio4: gpio@48059000 {
269 compatible = "ti,omap4-gpio";
270 reg = <0x48059000 0x200>;
271 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
272 ti,hwmods = "gpio4";
273 gpio-controller;
274 #gpio-cells = <2>;
275 interrupt-controller;
276 #interrupt-cells = <2>;
277 };
278
279 gpio5: gpio@4805b000 {
280 compatible = "ti,omap4-gpio";
281 reg = <0x4805b000 0x200>;
282 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
283 ti,hwmods = "gpio5";
284 gpio-controller;
285 #gpio-cells = <2>;
286 interrupt-controller;
287 #interrupt-cells = <2>;
288 };
289
290 gpio6: gpio@4805d000 {
291 compatible = "ti,omap4-gpio";
292 reg = <0x4805d000 0x200>;
293 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
294 ti,hwmods = "gpio6";
295 gpio-controller;
296 #gpio-cells = <2>;
297 interrupt-controller;
298 #interrupt-cells = <2>;
299 };
300
301 gpio7: gpio@48051000 {
302 compatible = "ti,omap4-gpio";
303 reg = <0x48051000 0x200>;
304 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
305 ti,hwmods = "gpio7";
306 gpio-controller;
307 #gpio-cells = <2>;
308 interrupt-controller;
309 #interrupt-cells = <2>;
310 };
311
312 gpio8: gpio@48053000 {
313 compatible = "ti,omap4-gpio";
314 reg = <0x48053000 0x200>;
315 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
316 ti,hwmods = "gpio8";
317 gpio-controller;
318 #gpio-cells = <2>;
319 interrupt-controller;
320 #interrupt-cells = <2>;
321 };
322
323 gpmc: gpmc@50000000 {
324 compatible = "ti,omap4430-gpmc";
325 reg = <0x50000000 0x1000>;
326 #address-cells = <2>;
327 #size-cells = <1>;
328 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
329 gpmc,num-cs = <8>;
330 gpmc,num-waitpins = <4>;
331 ti,hwmods = "gpmc";
332 clocks = <&l3_iclk_div>;
333 clock-names = "fck";
334 };
335
336 i2c1: i2c@48070000 {
337 compatible = "ti,omap4-i2c";
338 reg = <0x48070000 0x100>;
339 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
340 #address-cells = <1>;
341 #size-cells = <0>;
342 ti,hwmods = "i2c1";
343 };
344
345 i2c2: i2c@48072000 {
346 compatible = "ti,omap4-i2c";
347 reg = <0x48072000 0x100>;
348 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
349 #address-cells = <1>;
350 #size-cells = <0>;
351 ti,hwmods = "i2c2";
352 };
353
354 i2c3: i2c@48060000 {
355 compatible = "ti,omap4-i2c";
356 reg = <0x48060000 0x100>;
357 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
358 #address-cells = <1>;
359 #size-cells = <0>;
360 ti,hwmods = "i2c3";
361 };
362
363 i2c4: i2c@4807a000 {
364 compatible = "ti,omap4-i2c";
365 reg = <0x4807a000 0x100>;
366 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
367 #address-cells = <1>;
368 #size-cells = <0>;
369 ti,hwmods = "i2c4";
370 };
371
372 i2c5: i2c@4807c000 {
373 compatible = "ti,omap4-i2c";
374 reg = <0x4807c000 0x100>;
375 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
376 #address-cells = <1>;
377 #size-cells = <0>;
378 ti,hwmods = "i2c5";
379 };
380
381 hwspinlock: spinlock@4a0f6000 {
382 compatible = "ti,omap4-hwspinlock";
383 reg = <0x4a0f6000 0x1000>;
384 ti,hwmods = "spinlock";
385 #hwlock-cells = <1>;
386 };
387
388 mcspi1: spi@48098000 {
389 compatible = "ti,omap4-mcspi";
390 reg = <0x48098000 0x200>;
391 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
392 #address-cells = <1>;
393 #size-cells = <0>;
394 ti,hwmods = "mcspi1";
395 ti,spi-num-cs = <4>;
396 dmas = <&sdma 35>,
397 <&sdma 36>,
398 <&sdma 37>,
399 <&sdma 38>,
400 <&sdma 39>,
401 <&sdma 40>,
402 <&sdma 41>,
403 <&sdma 42>;
404 dma-names = "tx0", "rx0", "tx1", "rx1",
405 "tx2", "rx2", "tx3", "rx3";
406 };
407
408 mcspi2: spi@4809a000 {
409 compatible = "ti,omap4-mcspi";
410 reg = <0x4809a000 0x200>;
411 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
412 #address-cells = <1>;
413 #size-cells = <0>;
414 ti,hwmods = "mcspi2";
415 ti,spi-num-cs = <2>;
416 dmas = <&sdma 43>,
417 <&sdma 44>,
418 <&sdma 45>,
419 <&sdma 46>;
420 dma-names = "tx0", "rx0", "tx1", "rx1";
421 };
422
423 mcspi3: spi@480b8000 {
424 compatible = "ti,omap4-mcspi";
425 reg = <0x480b8000 0x200>;
426 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
427 #address-cells = <1>;
428 #size-cells = <0>;
429 ti,hwmods = "mcspi3";
430 ti,spi-num-cs = <2>;
431 dmas = <&sdma 15>, <&sdma 16>;
432 dma-names = "tx0", "rx0";
433 };
434
435 mcspi4: spi@480ba000 {
436 compatible = "ti,omap4-mcspi";
437 reg = <0x480ba000 0x200>;
438 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
439 #address-cells = <1>;
440 #size-cells = <0>;
441 ti,hwmods = "mcspi4";
442 ti,spi-num-cs = <1>;
443 dmas = <&sdma 70>, <&sdma 71>;
444 dma-names = "tx0", "rx0";
445 };
446
447 uart1: serial@4806a000 {
448 compatible = "ti,omap4-uart";
449 reg = <0x4806a000 0x100>;
450 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
451 ti,hwmods = "uart1";
452 clock-frequency = <48000000>;
453 };
454
455 uart2: serial@4806c000 {
456 compatible = "ti,omap4-uart";
457 reg = <0x4806c000 0x100>;
458 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
459 ti,hwmods = "uart2";
460 clock-frequency = <48000000>;
461 };
462
463 uart3: serial@48020000 {
464 compatible = "ti,omap4-uart";
465 reg = <0x48020000 0x100>;
466 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
467 ti,hwmods = "uart3";
468 clock-frequency = <48000000>;
469 };
470
471 uart4: serial@4806e000 {
472 compatible = "ti,omap4-uart";
473 reg = <0x4806e000 0x100>;
474 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
475 ti,hwmods = "uart4";
476 clock-frequency = <48000000>;
477 };
478
479 uart5: serial@48066000 {
480 compatible = "ti,omap4-uart";
481 reg = <0x48066000 0x100>;
482 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
483 ti,hwmods = "uart5";
484 clock-frequency = <48000000>;
485 };
486
487 uart6: serial@48068000 {
488 compatible = "ti,omap4-uart";
489 reg = <0x48068000 0x100>;
490 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
491 ti,hwmods = "uart6";
492 clock-frequency = <48000000>;
493 };
494
495 mmc1: mmc@4809c000 {
496 compatible = "ti,omap4-hsmmc";
497 reg = <0x4809c000 0x400>;
498 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
499 ti,hwmods = "mmc1";
500 ti,dual-volt;
501 ti,needs-special-reset;
502 dmas = <&sdma 61>, <&sdma 62>;
503 dma-names = "tx", "rx";
504 pbias-supply = <&pbias_mmc_reg>;
505 };
506
507 mmc2: mmc@480b4000 {
508 compatible = "ti,omap4-hsmmc";
509 reg = <0x480b4000 0x400>;
510 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
511 ti,hwmods = "mmc2";
512 ti,needs-special-reset;
513 dmas = <&sdma 47>, <&sdma 48>;
514 dma-names = "tx", "rx";
515 };
516
517 mmc3: mmc@480ad000 {
518 compatible = "ti,omap4-hsmmc";
519 reg = <0x480ad000 0x400>;
520 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
521 ti,hwmods = "mmc3";
522 ti,needs-special-reset;
523 dmas = <&sdma 77>, <&sdma 78>;
524 dma-names = "tx", "rx";
525 };
526
527 mmc4: mmc@480d1000 {
528 compatible = "ti,omap4-hsmmc";
529 reg = <0x480d1000 0x400>;
530 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
531 ti,hwmods = "mmc4";
532 ti,needs-special-reset;
533 dmas = <&sdma 57>, <&sdma 58>;
534 dma-names = "tx", "rx";
535 };
536
537 mmc5: mmc@480d5000 {
538 compatible = "ti,omap4-hsmmc";
539 reg = <0x480d5000 0x400>;
540 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
541 ti,hwmods = "mmc5";
542 ti,needs-special-reset;
543 dmas = <&sdma 59>, <&sdma 60>;
544 dma-names = "tx", "rx";
545 };
546
547 mmu_dsp: mmu@4a066000 {
548 compatible = "ti,omap4-iommu";
549 reg = <0x4a066000 0x100>;
550 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
551 ti,hwmods = "mmu_dsp";
552 };
553
554 mmu_ipu: mmu@55082000 {
555 compatible = "ti,omap4-iommu";
556 reg = <0x55082000 0x100>;
557 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
558 ti,hwmods = "mmu_ipu";
559 ti,iommu-bus-err-back;
560 };
561
562 keypad: keypad@4ae1c000 {
563 compatible = "ti,omap4-keypad";
564 reg = <0x4ae1c000 0x400>;
565 ti,hwmods = "kbd";
566 };
567
568 mcpdm: mcpdm@40132000 {
569 compatible = "ti,omap4-mcpdm";
570 reg = <0x40132000 0x7f>, /* MPU private access */
571 <0x49032000 0x7f>; /* L3 Interconnect */
572 reg-names = "mpu", "dma";
573 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
574 ti,hwmods = "mcpdm";
575 dmas = <&sdma 65>,
576 <&sdma 66>;
577 dma-names = "up_link", "dn_link";
578 status = "disabled";
579 };
580
581 dmic: dmic@4012e000 {
582 compatible = "ti,omap4-dmic";
583 reg = <0x4012e000 0x7f>, /* MPU private access */
584 <0x4902e000 0x7f>; /* L3 Interconnect */
585 reg-names = "mpu", "dma";
586 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
587 ti,hwmods = "dmic";
588 dmas = <&sdma 67>;
589 dma-names = "up_link";
590 status = "disabled";
591 };
592
593 mcbsp1: mcbsp@40122000 {
594 compatible = "ti,omap4-mcbsp";
595 reg = <0x40122000 0xff>, /* MPU private access */
596 <0x49022000 0xff>; /* L3 Interconnect */
597 reg-names = "mpu", "dma";
598 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
599 interrupt-names = "common";
600 ti,buffer-size = <128>;
601 ti,hwmods = "mcbsp1";
602 dmas = <&sdma 33>,
603 <&sdma 34>;
604 dma-names = "tx", "rx";
605 status = "disabled";
606 };
607
608 mcbsp2: mcbsp@40124000 {
609 compatible = "ti,omap4-mcbsp";
610 reg = <0x40124000 0xff>, /* MPU private access */
611 <0x49024000 0xff>; /* L3 Interconnect */
612 reg-names = "mpu", "dma";
613 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
614 interrupt-names = "common";
615 ti,buffer-size = <128>;
616 ti,hwmods = "mcbsp2";
617 dmas = <&sdma 17>,
618 <&sdma 18>;
619 dma-names = "tx", "rx";
620 status = "disabled";
621 };
622
623 mcbsp3: mcbsp@40126000 {
624 compatible = "ti,omap4-mcbsp";
625 reg = <0x40126000 0xff>, /* MPU private access */
626 <0x49026000 0xff>; /* L3 Interconnect */
627 reg-names = "mpu", "dma";
628 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
629 interrupt-names = "common";
630 ti,buffer-size = <128>;
631 ti,hwmods = "mcbsp3";
632 dmas = <&sdma 19>,
633 <&sdma 20>;
634 dma-names = "tx", "rx";
635 status = "disabled";
636 };
637
638 mailbox: mailbox@4a0f4000 {
639 compatible = "ti,omap4-mailbox";
640 reg = <0x4a0f4000 0x200>;
641 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
642 ti,hwmods = "mailbox";
643 };
644
645 timer1: timer@4ae18000 {
646 compatible = "ti,omap5430-timer";
647 reg = <0x4ae18000 0x80>;
648 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
649 ti,hwmods = "timer1";
650 ti,timer-alwon;
651 };
652
653 timer2: timer@48032000 {
654 compatible = "ti,omap5430-timer";
655 reg = <0x48032000 0x80>;
656 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
657 ti,hwmods = "timer2";
658 };
659
660 timer3: timer@48034000 {
661 compatible = "ti,omap5430-timer";
662 reg = <0x48034000 0x80>;
663 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
664 ti,hwmods = "timer3";
665 };
666
667 timer4: timer@48036000 {
668 compatible = "ti,omap5430-timer";
669 reg = <0x48036000 0x80>;
670 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
671 ti,hwmods = "timer4";
672 };
673
674 timer5: timer@40138000 {
675 compatible = "ti,omap5430-timer";
676 reg = <0x40138000 0x80>,
677 <0x49038000 0x80>;
678 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
679 ti,hwmods = "timer5";
680 ti,timer-dsp;
681 ti,timer-pwm;
682 };
683
684 timer6: timer@4013a000 {
685 compatible = "ti,omap5430-timer";
686 reg = <0x4013a000 0x80>,
687 <0x4903a000 0x80>;
688 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
689 ti,hwmods = "timer6";
690 ti,timer-dsp;
691 ti,timer-pwm;
692 };
693
694 timer7: timer@4013c000 {
695 compatible = "ti,omap5430-timer";
696 reg = <0x4013c000 0x80>,
697 <0x4903c000 0x80>;
698 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
699 ti,hwmods = "timer7";
700 ti,timer-dsp;
701 };
702
703 timer8: timer@4013e000 {
704 compatible = "ti,omap5430-timer";
705 reg = <0x4013e000 0x80>,
706 <0x4903e000 0x80>;
707 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
708 ti,hwmods = "timer8";
709 ti,timer-dsp;
710 ti,timer-pwm;
711 };
712
713 timer9: timer@4803e000 {
714 compatible = "ti,omap5430-timer";
715 reg = <0x4803e000 0x80>;
716 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
717 ti,hwmods = "timer9";
718 ti,timer-pwm;
719 };
720
721 timer10: timer@48086000 {
722 compatible = "ti,omap5430-timer";
723 reg = <0x48086000 0x80>;
724 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
725 ti,hwmods = "timer10";
726 ti,timer-pwm;
727 };
728
729 timer11: timer@48088000 {
730 compatible = "ti,omap5430-timer";
731 reg = <0x48088000 0x80>;
732 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
733 ti,hwmods = "timer11";
734 ti,timer-pwm;
735 };
736
737 wdt2: wdt@4ae14000 {
738 compatible = "ti,omap5-wdt", "ti,omap3-wdt";
739 reg = <0x4ae14000 0x80>;
740 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
741 ti,hwmods = "wd_timer2";
742 };
743
744 dmm@4e000000 {
745 compatible = "ti,omap5-dmm";
746 reg = <0x4e000000 0x800>;
747 interrupts = <0 113 0x4>;
748 ti,hwmods = "dmm";
749 };
750
751 emif1: emif@4c000000 {
752 compatible = "ti,emif-4d5";
753 ti,hwmods = "emif1";
754 ti,no-idle-on-init;
755 phy-type = <2>; /* DDR PHY type: Intelli PHY */
756 reg = <0x4c000000 0x400>;
757 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
758 hw-caps-read-idle-ctrl;
759 hw-caps-ll-interface;
760 hw-caps-temp-alert;
761 };
762
763 emif2: emif@4d000000 {
764 compatible = "ti,emif-4d5";
765 ti,hwmods = "emif2";
766 ti,no-idle-on-init;
767 phy-type = <2>; /* DDR PHY type: Intelli PHY */
768 reg = <0x4d000000 0x400>;
769 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
770 hw-caps-read-idle-ctrl;
771 hw-caps-ll-interface;
772 hw-caps-temp-alert;
773 };
774
775 omap_control_usb2phy: control-phy@4a002300 {
776 compatible = "ti,control-phy-usb2";
777 reg = <0x4a002300 0x4>;
778 reg-names = "power";
779 };
780
781 omap_control_usb3phy: control-phy@4a002370 {
782 compatible = "ti,control-phy-pipe3";
783 reg = <0x4a002370 0x4>;
784 reg-names = "power";
785 };
786
787 usb3: omap_dwc3@4a020000 {
788 compatible = "ti,dwc3";
789 ti,hwmods = "usb_otg_ss";
790 reg = <0x4a020000 0x10000>;
791 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
792 #address-cells = <1>;
793 #size-cells = <1>;
794 utmi-mode = <2>;
795 ranges;
796 dwc3@4a030000 {
797 compatible = "snps,dwc3";
798 reg = <0x4a030000 0x10000>;
799 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
800 phys = <&usb2_phy>, <&usb3_phy>;
801 phy-names = "usb2-phy", "usb3-phy";
802 dr_mode = "peripheral";
803 tx-fifo-resize;
804 };
805 };
806
807 ocp2scp@4a080000 {
808 compatible = "ti,omap-ocp2scp";
809 #address-cells = <1>;
810 #size-cells = <1>;
811 reg = <0x4a080000 0x20>;
812 ranges;
813 ti,hwmods = "ocp2scp1";
814 usb2_phy: usb2phy@4a084000 {
815 compatible = "ti,omap-usb2";
816 reg = <0x4a084000 0x7c>;
817 ctrl-module = <&omap_control_usb2phy>;
818 clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
819 clock-names = "wkupclk", "refclk";
820 #phy-cells = <0>;
821 };
822
823 usb3_phy: usb3phy@4a084400 {
824 compatible = "ti,omap-usb3";
825 reg = <0x4a084400 0x80>,
826 <0x4a084800 0x64>,
827 <0x4a084c00 0x40>;
828 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
829 ctrl-module = <&omap_control_usb3phy>;
830 clocks = <&usb_phy_cm_clk32k>,
831 <&sys_clkin>,
832 <&usb_otg_ss_refclk960m>;
833 clock-names = "wkupclk",
834 "sysclk",
835 "refclk";
836 #phy-cells = <0>;
837 };
838 };
839
840 usbhstll: usbhstll@4a062000 {
841 compatible = "ti,usbhs-tll";
842 reg = <0x4a062000 0x1000>;
843 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
844 ti,hwmods = "usb_tll_hs";
845 };
846
847 usbhshost: usbhshost@4a064000 {
848 compatible = "ti,usbhs-host";
849 reg = <0x4a064000 0x800>;
850 ti,hwmods = "usb_host_hs";
851 #address-cells = <1>;
852 #size-cells = <1>;
853 ranges;
854 clocks = <&l3init_60m_fclk>,
855 <&xclk60mhsp1_ck>,
856 <&xclk60mhsp2_ck>;
857 clock-names = "refclk_60m_int",
858 "refclk_60m_ext_p1",
859 "refclk_60m_ext_p2";
860
861 usbhsohci: ohci@4a064800 {
862 compatible = "ti,ohci-omap3";
863 reg = <0x4a064800 0x400>;
864 interrupt-parent = <&gic>;
865 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
866 };
867
868 usbhsehci: ehci@4a064c00 {
869 compatible = "ti,ehci-omap";
870 reg = <0x4a064c00 0x400>;
871 interrupt-parent = <&gic>;
872 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
873 };
874 };
875
876 bandgap: bandgap@4a0021e0 {
877 reg = <0x4a0021e0 0xc
878 0x4a00232c 0xc
879 0x4a002380 0x2c
880 0x4a0023C0 0x3c>;
881 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
882 compatible = "ti,omap5430-bandgap";
883
884 #thermal-sensor-cells = <1>;
885 };
886
887 omap_control_sata: control-phy@4a002374 {
888 compatible = "ti,control-phy-pipe3";
889 reg = <0x4a002374 0x4>;
890 reg-names = "power";
891 clocks = <&sys_clkin>;
892 clock-names = "sysclk";
893 };
894
895 /* OCP2SCP3 */
896 ocp2scp@4a090000 {
897 compatible = "ti,omap-ocp2scp";
898 #address-cells = <1>;
899 #size-cells = <1>;
900 reg = <0x4a090000 0x20>;
901 ranges;
902 ti,hwmods = "ocp2scp3";
903 sata_phy: phy@4a096000 {
904 compatible = "ti,phy-pipe3-sata";
905 reg = <0x4A096000 0x80>, /* phy_rx */
906 <0x4A096400 0x64>, /* phy_tx */
907 <0x4A096800 0x40>; /* pll_ctrl */
908 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
909 ctrl-module = <&omap_control_sata>;
910 clocks = <&sys_clkin>;
911 clock-names = "sysclk";
912 #phy-cells = <0>;
913 };
914 };
915
916 sata: sata@4a141100 {
917 compatible = "snps,dwc-ahci";
918 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
919 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
920 phys = <&sata_phy>;
921 phy-names = "sata-phy";
922 clocks = <&sata_ref_clk>;
923 ti,hwmods = "sata";
924 };
925
926 dss: dss@58000000 {
927 compatible = "ti,omap5-dss";
928 reg = <0x58000000 0x80>;
929 status = "disabled";
930 ti,hwmods = "dss_core";
931 clocks = <&dss_dss_clk>;
932 clock-names = "fck";
933 #address-cells = <1>;
934 #size-cells = <1>;
935 ranges;
936
937 dispc@58001000 {
938 compatible = "ti,omap5-dispc";
939 reg = <0x58001000 0x1000>;
940 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
941 ti,hwmods = "dss_dispc";
942 clocks = <&dss_dss_clk>;
943 clock-names = "fck";
944 };
945
946 dsi1: encoder@58004000 {
947 compatible = "ti,omap5-dsi";
948 reg = <0x58004000 0x200>,
949 <0x58004200 0x40>,
950 <0x58004300 0x40>;
951 reg-names = "proto", "phy", "pll";
952 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
953 status = "disabled";
954 ti,hwmods = "dss_dsi1";
955 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
956 clock-names = "fck", "sys_clk";
957 };
958
959 dsi2: encoder@58005000 {
960 compatible = "ti,omap5-dsi";
961 reg = <0x58009000 0x200>,
962 <0x58009200 0x40>,
963 <0x58009300 0x40>;
964 reg-names = "proto", "phy", "pll";
965 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
966 status = "disabled";
967 ti,hwmods = "dss_dsi2";
968 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
969 clock-names = "fck", "sys_clk";
970 };
971
972 hdmi: encoder@58060000 {
973 compatible = "ti,omap5-hdmi";
974 reg = <0x58040000 0x200>,
975 <0x58040200 0x80>,
976 <0x58040300 0x80>,
977 <0x58060000 0x19000>;
978 reg-names = "wp", "pll", "phy", "core";
979 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
980 status = "disabled";
981 ti,hwmods = "dss_hdmi";
982 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
983 clock-names = "fck", "sys_clk";
984 dmas = <&sdma 76>;
985 dma-names = "audio_tx";
986 };
987 };
988 };
989 };
990
991 /include/ "omap54xx-clocks.dtsi"
Linux kernel - Deliverables
This page took 0.053966 seconds and 5 git commands to generate.