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ARM: STi: STiH416: Add Pinctrl settings for PWM
[deliverable/linux.git] / arch / arm / boot / dts / omap5.dtsi
1 /*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
9
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/pinctrl/omap.h>
13
14 #include "skeleton.dtsi"
15
16 / {
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 compatible = "ti,omap5";
21 interrupt-parent = <&wakeupgen>;
22
23 aliases {
24 i2c0 = &i2c1;
25 i2c1 = &i2c2;
26 i2c2 = &i2c3;
27 i2c3 = &i2c4;
28 i2c4 = &i2c5;
29 serial0 = &uart1;
30 serial1 = &uart2;
31 serial2 = &uart3;
32 serial3 = &uart4;
33 serial4 = &uart5;
34 serial5 = &uart6;
35 };
36
37 cpus {
38 #address-cells = <1>;
39 #size-cells = <0>;
40
41 cpu0: cpu@0 {
42 device_type = "cpu";
43 compatible = "arm,cortex-a15";
44 reg = <0x0>;
45
46 operating-points = <
47 /* kHz uV */
48 1000000 1060000
49 1500000 1250000
50 >;
51
52 clocks = <&dpll_mpu_ck>;
53 clock-names = "cpu";
54
55 clock-latency = <300000>; /* From omap-cpufreq driver */
56
57 /* cooling options */
58 cooling-min-level = <0>;
59 cooling-max-level = <2>;
60 #cooling-cells = <2>; /* min followed by max */
61 };
62 cpu@1 {
63 device_type = "cpu";
64 compatible = "arm,cortex-a15";
65 reg = <0x1>;
66 };
67 };
68
69 thermal-zones {
70 #include "omap4-cpu-thermal.dtsi"
71 #include "omap5-gpu-thermal.dtsi"
72 #include "omap5-core-thermal.dtsi"
73 };
74
75 timer {
76 compatible = "arm,armv7-timer";
77 /* PPI secure/nonsecure IRQ */
78 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
79 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
80 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
81 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
82 interrupt-parent = <&gic>;
83 };
84
85 pmu {
86 compatible = "arm,cortex-a15-pmu";
87 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
88 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
89 };
90
91 gic: interrupt-controller@48211000 {
92 compatible = "arm,cortex-a15-gic";
93 interrupt-controller;
94 #interrupt-cells = <3>;
95 reg = <0x48211000 0x1000>,
96 <0x48212000 0x1000>,
97 <0x48214000 0x2000>,
98 <0x48216000 0x2000>;
99 interrupt-parent = <&gic>;
100 };
101
102 wakeupgen: interrupt-controller@48281000 {
103 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
104 interrupt-controller;
105 #interrupt-cells = <3>;
106 reg = <0x48281000 0x1000>;
107 interrupt-parent = <&gic>;
108 };
109
110 /*
111 * The soc node represents the soc top level view. It is used for IPs
112 * that are not memory mapped in the MPU view or for the MPU itself.
113 */
114 soc {
115 compatible = "ti,omap-infra";
116 mpu {
117 compatible = "ti,omap4-mpu";
118 ti,hwmods = "mpu";
119 sram = <&ocmcram>;
120 };
121 };
122
123 /*
124 * XXX: Use a flat representation of the OMAP3 interconnect.
125 * The real OMAP interconnect network is quite complex.
126 * Since it will not bring real advantage to represent that in DT for
127 * the moment, just use a fake OCP bus entry to represent the whole bus
128 * hierarchy.
129 */
130 ocp {
131 compatible = "ti,omap4-l3-noc", "simple-bus";
132 #address-cells = <1>;
133 #size-cells = <1>;
134 ranges;
135 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
136 reg = <0x44000000 0x2000>,
137 <0x44800000 0x3000>,
138 <0x45000000 0x4000>;
139 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
140 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
141
142 l4_cfg: l4@4a000000 {
143 compatible = "ti,omap5-l4-cfg", "simple-bus";
144 #address-cells = <1>;
145 #size-cells = <1>;
146 ranges = <0 0x4a000000 0x22a000>;
147
148 scm_core: scm@2000 {
149 compatible = "ti,omap5-scm-core", "simple-bus";
150 reg = <0x2000 0x1000>;
151 #address-cells = <1>;
152 #size-cells = <1>;
153 ranges = <0 0x2000 0x800>;
154
155 scm_conf: scm_conf@0 {
156 compatible = "syscon";
157 reg = <0x0 0x800>;
158 #address-cells = <1>;
159 #size-cells = <1>;
160 };
161 };
162
163 scm_padconf_core: scm@2800 {
164 compatible = "ti,omap5-scm-padconf-core",
165 "simple-bus";
166 #address-cells = <1>;
167 #size-cells = <1>;
168 ranges = <0 0x2800 0x800>;
169
170 omap5_pmx_core: pinmux@40 {
171 compatible = "ti,omap5-padconf",
172 "pinctrl-single";
173 reg = <0x40 0x01b6>;
174 #address-cells = <1>;
175 #size-cells = <0>;
176 #interrupt-cells = <1>;
177 interrupt-controller;
178 pinctrl-single,register-width = <16>;
179 pinctrl-single,function-mask = <0x7fff>;
180 };
181
182 omap5_padconf_global: omap5_padconf_global@5a0 {
183 compatible = "syscon";
184 reg = <0x5a0 0xec>;
185 #address-cells = <1>;
186 #size-cells = <1>;
187
188 pbias_regulator: pbias_regulator {
189 compatible = "ti,pbias-omap";
190 reg = <0x60 0x4>;
191 syscon = <&omap5_padconf_global>;
192 pbias_mmc_reg: pbias_mmc_omap5 {
193 regulator-name = "pbias_mmc_omap5";
194 regulator-min-microvolt = <1800000>;
195 regulator-max-microvolt = <3000000>;
196 };
197 };
198 };
199 };
200
201 cm_core_aon: cm_core_aon@4000 {
202 compatible = "ti,omap5-cm-core-aon";
203 reg = <0x4000 0x2000>;
204
205 cm_core_aon_clocks: clocks {
206 #address-cells = <1>;
207 #size-cells = <0>;
208 };
209
210 cm_core_aon_clockdomains: clockdomains {
211 };
212 };
213
214 cm_core: cm_core@8000 {
215 compatible = "ti,omap5-cm-core";
216 reg = <0x8000 0x3000>;
217
218 cm_core_clocks: clocks {
219 #address-cells = <1>;
220 #size-cells = <0>;
221 };
222
223 cm_core_clockdomains: clockdomains {
224 };
225 };
226 };
227
228 l4_wkup: l4@4ae00000 {
229 compatible = "ti,omap5-l4-wkup", "simple-bus";
230 #address-cells = <1>;
231 #size-cells = <1>;
232 ranges = <0 0x4ae00000 0x2b000>;
233
234 counter32k: counter@4000 {
235 compatible = "ti,omap-counter32k";
236 reg = <0x4000 0x40>;
237 ti,hwmods = "counter_32k";
238 };
239
240 prm: prm@6000 {
241 compatible = "ti,omap5-prm";
242 reg = <0x6000 0x3000>;
243 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
244
245 prm_clocks: clocks {
246 #address-cells = <1>;
247 #size-cells = <0>;
248 };
249
250 prm_clockdomains: clockdomains {
251 };
252 };
253
254 scrm: scrm@a000 {
255 compatible = "ti,omap5-scrm";
256 reg = <0xa000 0x2000>;
257
258 scrm_clocks: clocks {
259 #address-cells = <1>;
260 #size-cells = <0>;
261 };
262
263 scrm_clockdomains: clockdomains {
264 };
265 };
266
267 omap5_pmx_wkup: pinmux@c840 {
268 compatible = "ti,omap5-padconf",
269 "pinctrl-single";
270 reg = <0xc840 0x0038>;
271 #address-cells = <1>;
272 #size-cells = <0>;
273 #interrupt-cells = <1>;
274 interrupt-controller;
275 pinctrl-single,register-width = <16>;
276 pinctrl-single,function-mask = <0x7fff>;
277 };
278 };
279
280 ocmcram: ocmcram@40300000 {
281 compatible = "mmio-sram";
282 reg = <0x40300000 0x20000>; /* 128k */
283 };
284
285 sdma: dma-controller@4a056000 {
286 compatible = "ti,omap4430-sdma";
287 reg = <0x4a056000 0x1000>;
288 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
292 #dma-cells = <1>;
293 dma-channels = <32>;
294 dma-requests = <127>;
295 };
296
297 gpio1: gpio@4ae10000 {
298 compatible = "ti,omap4-gpio";
299 reg = <0x4ae10000 0x200>;
300 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
301 ti,hwmods = "gpio1";
302 ti,gpio-always-on;
303 gpio-controller;
304 #gpio-cells = <2>;
305 interrupt-controller;
306 #interrupt-cells = <2>;
307 };
308
309 gpio2: gpio@48055000 {
310 compatible = "ti,omap4-gpio";
311 reg = <0x48055000 0x200>;
312 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
313 ti,hwmods = "gpio2";
314 gpio-controller;
315 #gpio-cells = <2>;
316 interrupt-controller;
317 #interrupt-cells = <2>;
318 };
319
320 gpio3: gpio@48057000 {
321 compatible = "ti,omap4-gpio";
322 reg = <0x48057000 0x200>;
323 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
324 ti,hwmods = "gpio3";
325 gpio-controller;
326 #gpio-cells = <2>;
327 interrupt-controller;
328 #interrupt-cells = <2>;
329 };
330
331 gpio4: gpio@48059000 {
332 compatible = "ti,omap4-gpio";
333 reg = <0x48059000 0x200>;
334 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
335 ti,hwmods = "gpio4";
336 gpio-controller;
337 #gpio-cells = <2>;
338 interrupt-controller;
339 #interrupt-cells = <2>;
340 };
341
342 gpio5: gpio@4805b000 {
343 compatible = "ti,omap4-gpio";
344 reg = <0x4805b000 0x200>;
345 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
346 ti,hwmods = "gpio5";
347 gpio-controller;
348 #gpio-cells = <2>;
349 interrupt-controller;
350 #interrupt-cells = <2>;
351 };
352
353 gpio6: gpio@4805d000 {
354 compatible = "ti,omap4-gpio";
355 reg = <0x4805d000 0x200>;
356 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
357 ti,hwmods = "gpio6";
358 gpio-controller;
359 #gpio-cells = <2>;
360 interrupt-controller;
361 #interrupt-cells = <2>;
362 };
363
364 gpio7: gpio@48051000 {
365 compatible = "ti,omap4-gpio";
366 reg = <0x48051000 0x200>;
367 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
368 ti,hwmods = "gpio7";
369 gpio-controller;
370 #gpio-cells = <2>;
371 interrupt-controller;
372 #interrupt-cells = <2>;
373 };
374
375 gpio8: gpio@48053000 {
376 compatible = "ti,omap4-gpio";
377 reg = <0x48053000 0x200>;
378 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
379 ti,hwmods = "gpio8";
380 gpio-controller;
381 #gpio-cells = <2>;
382 interrupt-controller;
383 #interrupt-cells = <2>;
384 };
385
386 gpmc: gpmc@50000000 {
387 compatible = "ti,omap4430-gpmc";
388 reg = <0x50000000 0x1000>;
389 #address-cells = <2>;
390 #size-cells = <1>;
391 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
392 gpmc,num-cs = <8>;
393 gpmc,num-waitpins = <4>;
394 ti,hwmods = "gpmc";
395 clocks = <&l3_iclk_div>;
396 clock-names = "fck";
397 };
398
399 i2c1: i2c@48070000 {
400 compatible = "ti,omap4-i2c";
401 reg = <0x48070000 0x100>;
402 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
403 #address-cells = <1>;
404 #size-cells = <0>;
405 ti,hwmods = "i2c1";
406 };
407
408 i2c2: i2c@48072000 {
409 compatible = "ti,omap4-i2c";
410 reg = <0x48072000 0x100>;
411 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
412 #address-cells = <1>;
413 #size-cells = <0>;
414 ti,hwmods = "i2c2";
415 };
416
417 i2c3: i2c@48060000 {
418 compatible = "ti,omap4-i2c";
419 reg = <0x48060000 0x100>;
420 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
421 #address-cells = <1>;
422 #size-cells = <0>;
423 ti,hwmods = "i2c3";
424 };
425
426 i2c4: i2c@4807a000 {
427 compatible = "ti,omap4-i2c";
428 reg = <0x4807a000 0x100>;
429 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
430 #address-cells = <1>;
431 #size-cells = <0>;
432 ti,hwmods = "i2c4";
433 };
434
435 i2c5: i2c@4807c000 {
436 compatible = "ti,omap4-i2c";
437 reg = <0x4807c000 0x100>;
438 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
439 #address-cells = <1>;
440 #size-cells = <0>;
441 ti,hwmods = "i2c5";
442 };
443
444 hwspinlock: spinlock@4a0f6000 {
445 compatible = "ti,omap4-hwspinlock";
446 reg = <0x4a0f6000 0x1000>;
447 ti,hwmods = "spinlock";
448 #hwlock-cells = <1>;
449 };
450
451 mcspi1: spi@48098000 {
452 compatible = "ti,omap4-mcspi";
453 reg = <0x48098000 0x200>;
454 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
455 #address-cells = <1>;
456 #size-cells = <0>;
457 ti,hwmods = "mcspi1";
458 ti,spi-num-cs = <4>;
459 dmas = <&sdma 35>,
460 <&sdma 36>,
461 <&sdma 37>,
462 <&sdma 38>,
463 <&sdma 39>,
464 <&sdma 40>,
465 <&sdma 41>,
466 <&sdma 42>;
467 dma-names = "tx0", "rx0", "tx1", "rx1",
468 "tx2", "rx2", "tx3", "rx3";
469 };
470
471 mcspi2: spi@4809a000 {
472 compatible = "ti,omap4-mcspi";
473 reg = <0x4809a000 0x200>;
474 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
475 #address-cells = <1>;
476 #size-cells = <0>;
477 ti,hwmods = "mcspi2";
478 ti,spi-num-cs = <2>;
479 dmas = <&sdma 43>,
480 <&sdma 44>,
481 <&sdma 45>,
482 <&sdma 46>;
483 dma-names = "tx0", "rx0", "tx1", "rx1";
484 };
485
486 mcspi3: spi@480b8000 {
487 compatible = "ti,omap4-mcspi";
488 reg = <0x480b8000 0x200>;
489 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
490 #address-cells = <1>;
491 #size-cells = <0>;
492 ti,hwmods = "mcspi3";
493 ti,spi-num-cs = <2>;
494 dmas = <&sdma 15>, <&sdma 16>;
495 dma-names = "tx0", "rx0";
496 };
497
498 mcspi4: spi@480ba000 {
499 compatible = "ti,omap4-mcspi";
500 reg = <0x480ba000 0x200>;
501 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
502 #address-cells = <1>;
503 #size-cells = <0>;
504 ti,hwmods = "mcspi4";
505 ti,spi-num-cs = <1>;
506 dmas = <&sdma 70>, <&sdma 71>;
507 dma-names = "tx0", "rx0";
508 };
509
510 uart1: serial@4806a000 {
511 compatible = "ti,omap4-uart";
512 reg = <0x4806a000 0x100>;
513 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
514 ti,hwmods = "uart1";
515 clock-frequency = <48000000>;
516 };
517
518 uart2: serial@4806c000 {
519 compatible = "ti,omap4-uart";
520 reg = <0x4806c000 0x100>;
521 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
522 ti,hwmods = "uart2";
523 clock-frequency = <48000000>;
524 };
525
526 uart3: serial@48020000 {
527 compatible = "ti,omap4-uart";
528 reg = <0x48020000 0x100>;
529 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
530 ti,hwmods = "uart3";
531 clock-frequency = <48000000>;
532 };
533
534 uart4: serial@4806e000 {
535 compatible = "ti,omap4-uart";
536 reg = <0x4806e000 0x100>;
537 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
538 ti,hwmods = "uart4";
539 clock-frequency = <48000000>;
540 };
541
542 uart5: serial@48066000 {
543 compatible = "ti,omap4-uart";
544 reg = <0x48066000 0x100>;
545 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
546 ti,hwmods = "uart5";
547 clock-frequency = <48000000>;
548 };
549
550 uart6: serial@48068000 {
551 compatible = "ti,omap4-uart";
552 reg = <0x48068000 0x100>;
553 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
554 ti,hwmods = "uart6";
555 clock-frequency = <48000000>;
556 };
557
558 mmc1: mmc@4809c000 {
559 compatible = "ti,omap4-hsmmc";
560 reg = <0x4809c000 0x400>;
561 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
562 ti,hwmods = "mmc1";
563 ti,dual-volt;
564 ti,needs-special-reset;
565 dmas = <&sdma 61>, <&sdma 62>;
566 dma-names = "tx", "rx";
567 pbias-supply = <&pbias_mmc_reg>;
568 };
569
570 mmc2: mmc@480b4000 {
571 compatible = "ti,omap4-hsmmc";
572 reg = <0x480b4000 0x400>;
573 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
574 ti,hwmods = "mmc2";
575 ti,needs-special-reset;
576 dmas = <&sdma 47>, <&sdma 48>;
577 dma-names = "tx", "rx";
578 };
579
580 mmc3: mmc@480ad000 {
581 compatible = "ti,omap4-hsmmc";
582 reg = <0x480ad000 0x400>;
583 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
584 ti,hwmods = "mmc3";
585 ti,needs-special-reset;
586 dmas = <&sdma 77>, <&sdma 78>;
587 dma-names = "tx", "rx";
588 };
589
590 mmc4: mmc@480d1000 {
591 compatible = "ti,omap4-hsmmc";
592 reg = <0x480d1000 0x400>;
593 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
594 ti,hwmods = "mmc4";
595 ti,needs-special-reset;
596 dmas = <&sdma 57>, <&sdma 58>;
597 dma-names = "tx", "rx";
598 };
599
600 mmc5: mmc@480d5000 {
601 compatible = "ti,omap4-hsmmc";
602 reg = <0x480d5000 0x400>;
603 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
604 ti,hwmods = "mmc5";
605 ti,needs-special-reset;
606 dmas = <&sdma 59>, <&sdma 60>;
607 dma-names = "tx", "rx";
608 };
609
610 mmu_dsp: mmu@4a066000 {
611 compatible = "ti,omap4-iommu";
612 reg = <0x4a066000 0x100>;
613 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
614 ti,hwmods = "mmu_dsp";
615 };
616
617 mmu_ipu: mmu@55082000 {
618 compatible = "ti,omap4-iommu";
619 reg = <0x55082000 0x100>;
620 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
621 ti,hwmods = "mmu_ipu";
622 ti,iommu-bus-err-back;
623 };
624
625 keypad: keypad@4ae1c000 {
626 compatible = "ti,omap4-keypad";
627 reg = <0x4ae1c000 0x400>;
628 ti,hwmods = "kbd";
629 };
630
631 mcpdm: mcpdm@40132000 {
632 compatible = "ti,omap4-mcpdm";
633 reg = <0x40132000 0x7f>, /* MPU private access */
634 <0x49032000 0x7f>; /* L3 Interconnect */
635 reg-names = "mpu", "dma";
636 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
637 ti,hwmods = "mcpdm";
638 dmas = <&sdma 65>,
639 <&sdma 66>;
640 dma-names = "up_link", "dn_link";
641 status = "disabled";
642 };
643
644 dmic: dmic@4012e000 {
645 compatible = "ti,omap4-dmic";
646 reg = <0x4012e000 0x7f>, /* MPU private access */
647 <0x4902e000 0x7f>; /* L3 Interconnect */
648 reg-names = "mpu", "dma";
649 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
650 ti,hwmods = "dmic";
651 dmas = <&sdma 67>;
652 dma-names = "up_link";
653 status = "disabled";
654 };
655
656 mcbsp1: mcbsp@40122000 {
657 compatible = "ti,omap4-mcbsp";
658 reg = <0x40122000 0xff>, /* MPU private access */
659 <0x49022000 0xff>; /* L3 Interconnect */
660 reg-names = "mpu", "dma";
661 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
662 interrupt-names = "common";
663 ti,buffer-size = <128>;
664 ti,hwmods = "mcbsp1";
665 dmas = <&sdma 33>,
666 <&sdma 34>;
667 dma-names = "tx", "rx";
668 status = "disabled";
669 };
670
671 mcbsp2: mcbsp@40124000 {
672 compatible = "ti,omap4-mcbsp";
673 reg = <0x40124000 0xff>, /* MPU private access */
674 <0x49024000 0xff>; /* L3 Interconnect */
675 reg-names = "mpu", "dma";
676 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
677 interrupt-names = "common";
678 ti,buffer-size = <128>;
679 ti,hwmods = "mcbsp2";
680 dmas = <&sdma 17>,
681 <&sdma 18>;
682 dma-names = "tx", "rx";
683 status = "disabled";
684 };
685
686 mcbsp3: mcbsp@40126000 {
687 compatible = "ti,omap4-mcbsp";
688 reg = <0x40126000 0xff>, /* MPU private access */
689 <0x49026000 0xff>; /* L3 Interconnect */
690 reg-names = "mpu", "dma";
691 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
692 interrupt-names = "common";
693 ti,buffer-size = <128>;
694 ti,hwmods = "mcbsp3";
695 dmas = <&sdma 19>,
696 <&sdma 20>;
697 dma-names = "tx", "rx";
698 status = "disabled";
699 };
700
701 mailbox: mailbox@4a0f4000 {
702 compatible = "ti,omap4-mailbox";
703 reg = <0x4a0f4000 0x200>;
704 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
705 ti,hwmods = "mailbox";
706 #mbox-cells = <1>;
707 ti,mbox-num-users = <3>;
708 ti,mbox-num-fifos = <8>;
709 mbox_ipu: mbox_ipu {
710 ti,mbox-tx = <0 0 0>;
711 ti,mbox-rx = <1 0 0>;
712 };
713 mbox_dsp: mbox_dsp {
714 ti,mbox-tx = <3 0 0>;
715 ti,mbox-rx = <2 0 0>;
716 };
717 };
718
719 timer1: timer@4ae18000 {
720 compatible = "ti,omap5430-timer";
721 reg = <0x4ae18000 0x80>;
722 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
723 ti,hwmods = "timer1";
724 ti,timer-alwon;
725 };
726
727 timer2: timer@48032000 {
728 compatible = "ti,omap5430-timer";
729 reg = <0x48032000 0x80>;
730 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
731 ti,hwmods = "timer2";
732 };
733
734 timer3: timer@48034000 {
735 compatible = "ti,omap5430-timer";
736 reg = <0x48034000 0x80>;
737 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
738 ti,hwmods = "timer3";
739 };
740
741 timer4: timer@48036000 {
742 compatible = "ti,omap5430-timer";
743 reg = <0x48036000 0x80>;
744 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
745 ti,hwmods = "timer4";
746 };
747
748 timer5: timer@40138000 {
749 compatible = "ti,omap5430-timer";
750 reg = <0x40138000 0x80>,
751 <0x49038000 0x80>;
752 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
753 ti,hwmods = "timer5";
754 ti,timer-dsp;
755 ti,timer-pwm;
756 };
757
758 timer6: timer@4013a000 {
759 compatible = "ti,omap5430-timer";
760 reg = <0x4013a000 0x80>,
761 <0x4903a000 0x80>;
762 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
763 ti,hwmods = "timer6";
764 ti,timer-dsp;
765 ti,timer-pwm;
766 };
767
768 timer7: timer@4013c000 {
769 compatible = "ti,omap5430-timer";
770 reg = <0x4013c000 0x80>,
771 <0x4903c000 0x80>;
772 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
773 ti,hwmods = "timer7";
774 ti,timer-dsp;
775 };
776
777 timer8: timer@4013e000 {
778 compatible = "ti,omap5430-timer";
779 reg = <0x4013e000 0x80>,
780 <0x4903e000 0x80>;
781 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
782 ti,hwmods = "timer8";
783 ti,timer-dsp;
784 ti,timer-pwm;
785 };
786
787 timer9: timer@4803e000 {
788 compatible = "ti,omap5430-timer";
789 reg = <0x4803e000 0x80>;
790 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
791 ti,hwmods = "timer9";
792 ti,timer-pwm;
793 };
794
795 timer10: timer@48086000 {
796 compatible = "ti,omap5430-timer";
797 reg = <0x48086000 0x80>;
798 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
799 ti,hwmods = "timer10";
800 ti,timer-pwm;
801 };
802
803 timer11: timer@48088000 {
804 compatible = "ti,omap5430-timer";
805 reg = <0x48088000 0x80>;
806 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
807 ti,hwmods = "timer11";
808 ti,timer-pwm;
809 };
810
811 wdt2: wdt@4ae14000 {
812 compatible = "ti,omap5-wdt", "ti,omap3-wdt";
813 reg = <0x4ae14000 0x80>;
814 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
815 ti,hwmods = "wd_timer2";
816 };
817
818 dmm@4e000000 {
819 compatible = "ti,omap5-dmm";
820 reg = <0x4e000000 0x800>;
821 interrupts = <0 113 0x4>;
822 ti,hwmods = "dmm";
823 };
824
825 emif1: emif@4c000000 {
826 compatible = "ti,emif-4d5";
827 ti,hwmods = "emif1";
828 ti,no-idle-on-init;
829 phy-type = <2>; /* DDR PHY type: Intelli PHY */
830 reg = <0x4c000000 0x400>;
831 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
832 hw-caps-read-idle-ctrl;
833 hw-caps-ll-interface;
834 hw-caps-temp-alert;
835 };
836
837 emif2: emif@4d000000 {
838 compatible = "ti,emif-4d5";
839 ti,hwmods = "emif2";
840 ti,no-idle-on-init;
841 phy-type = <2>; /* DDR PHY type: Intelli PHY */
842 reg = <0x4d000000 0x400>;
843 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
844 hw-caps-read-idle-ctrl;
845 hw-caps-ll-interface;
846 hw-caps-temp-alert;
847 };
848
849 omap_control_usb2phy: control-phy@4a002300 {
850 compatible = "ti,control-phy-usb2";
851 reg = <0x4a002300 0x4>;
852 reg-names = "power";
853 };
854
855 omap_control_usb3phy: control-phy@4a002370 {
856 compatible = "ti,control-phy-pipe3";
857 reg = <0x4a002370 0x4>;
858 reg-names = "power";
859 };
860
861 usb3: omap_dwc3@4a020000 {
862 compatible = "ti,dwc3";
863 ti,hwmods = "usb_otg_ss";
864 reg = <0x4a020000 0x10000>;
865 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
866 #address-cells = <1>;
867 #size-cells = <1>;
868 utmi-mode = <2>;
869 ranges;
870 dwc3@4a030000 {
871 compatible = "snps,dwc3";
872 reg = <0x4a030000 0x10000>;
873 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
874 phys = <&usb2_phy>, <&usb3_phy>;
875 phy-names = "usb2-phy", "usb3-phy";
876 dr_mode = "peripheral";
877 tx-fifo-resize;
878 };
879 };
880
881 ocp2scp@4a080000 {
882 compatible = "ti,omap-ocp2scp";
883 #address-cells = <1>;
884 #size-cells = <1>;
885 reg = <0x4a080000 0x20>;
886 ranges;
887 ti,hwmods = "ocp2scp1";
888 usb2_phy: usb2phy@4a084000 {
889 compatible = "ti,omap-usb2";
890 reg = <0x4a084000 0x7c>;
891 ctrl-module = <&omap_control_usb2phy>;
892 clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
893 clock-names = "wkupclk", "refclk";
894 #phy-cells = <0>;
895 };
896
897 usb3_phy: usb3phy@4a084400 {
898 compatible = "ti,omap-usb3";
899 reg = <0x4a084400 0x80>,
900 <0x4a084800 0x64>,
901 <0x4a084c00 0x40>;
902 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
903 ctrl-module = <&omap_control_usb3phy>;
904 clocks = <&usb_phy_cm_clk32k>,
905 <&sys_clkin>,
906 <&usb_otg_ss_refclk960m>;
907 clock-names = "wkupclk",
908 "sysclk",
909 "refclk";
910 #phy-cells = <0>;
911 };
912 };
913
914 usbhstll: usbhstll@4a062000 {
915 compatible = "ti,usbhs-tll";
916 reg = <0x4a062000 0x1000>;
917 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
918 ti,hwmods = "usb_tll_hs";
919 };
920
921 usbhshost: usbhshost@4a064000 {
922 compatible = "ti,usbhs-host";
923 reg = <0x4a064000 0x800>;
924 ti,hwmods = "usb_host_hs";
925 #address-cells = <1>;
926 #size-cells = <1>;
927 ranges;
928 clocks = <&l3init_60m_fclk>,
929 <&xclk60mhsp1_ck>,
930 <&xclk60mhsp2_ck>;
931 clock-names = "refclk_60m_int",
932 "refclk_60m_ext_p1",
933 "refclk_60m_ext_p2";
934
935 usbhsohci: ohci@4a064800 {
936 compatible = "ti,ohci-omap3";
937 reg = <0x4a064800 0x400>;
938 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
939 };
940
941 usbhsehci: ehci@4a064c00 {
942 compatible = "ti,ehci-omap";
943 reg = <0x4a064c00 0x400>;
944 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
945 };
946 };
947
948 bandgap: bandgap@4a0021e0 {
949 reg = <0x4a0021e0 0xc
950 0x4a00232c 0xc
951 0x4a002380 0x2c
952 0x4a0023C0 0x3c>;
953 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
954 compatible = "ti,omap5430-bandgap";
955
956 #thermal-sensor-cells = <1>;
957 };
958
959 omap_control_sata: control-phy@4a002374 {
960 compatible = "ti,control-phy-pipe3";
961 reg = <0x4a002374 0x4>;
962 reg-names = "power";
963 clocks = <&sys_clkin>;
964 clock-names = "sysclk";
965 };
966
967 /* OCP2SCP3 */
968 ocp2scp@4a090000 {
969 compatible = "ti,omap-ocp2scp";
970 #address-cells = <1>;
971 #size-cells = <1>;
972 reg = <0x4a090000 0x20>;
973 ranges;
974 ti,hwmods = "ocp2scp3";
975 sata_phy: phy@4a096000 {
976 compatible = "ti,phy-pipe3-sata";
977 reg = <0x4A096000 0x80>, /* phy_rx */
978 <0x4A096400 0x64>, /* phy_tx */
979 <0x4A096800 0x40>; /* pll_ctrl */
980 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
981 ctrl-module = <&omap_control_sata>;
982 clocks = <&sys_clkin>, <&sata_ref_clk>;
983 clock-names = "sysclk", "refclk";
984 #phy-cells = <0>;
985 };
986 };
987
988 sata: sata@4a141100 {
989 compatible = "snps,dwc-ahci";
990 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
991 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
992 phys = <&sata_phy>;
993 phy-names = "sata-phy";
994 clocks = <&sata_ref_clk>;
995 ti,hwmods = "sata";
996 };
997
998 dss: dss@58000000 {
999 compatible = "ti,omap5-dss";
1000 reg = <0x58000000 0x80>;
1001 status = "disabled";
1002 ti,hwmods = "dss_core";
1003 clocks = <&dss_dss_clk>;
1004 clock-names = "fck";
1005 #address-cells = <1>;
1006 #size-cells = <1>;
1007 ranges;
1008
1009 dispc@58001000 {
1010 compatible = "ti,omap5-dispc";
1011 reg = <0x58001000 0x1000>;
1012 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1013 ti,hwmods = "dss_dispc";
1014 clocks = <&dss_dss_clk>;
1015 clock-names = "fck";
1016 };
1017
1018 rfbi: encoder@58002000 {
1019 compatible = "ti,omap5-rfbi";
1020 reg = <0x58002000 0x100>;
1021 status = "disabled";
1022 ti,hwmods = "dss_rfbi";
1023 clocks = <&dss_dss_clk>, <&l3_iclk_div>;
1024 clock-names = "fck", "ick";
1025 };
1026
1027 dsi1: encoder@58004000 {
1028 compatible = "ti,omap5-dsi";
1029 reg = <0x58004000 0x200>,
1030 <0x58004200 0x40>,
1031 <0x58004300 0x40>;
1032 reg-names = "proto", "phy", "pll";
1033 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1034 status = "disabled";
1035 ti,hwmods = "dss_dsi1";
1036 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
1037 clock-names = "fck", "sys_clk";
1038 };
1039
1040 dsi2: encoder@58005000 {
1041 compatible = "ti,omap5-dsi";
1042 reg = <0x58009000 0x200>,
1043 <0x58009200 0x40>,
1044 <0x58009300 0x40>;
1045 reg-names = "proto", "phy", "pll";
1046 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1047 status = "disabled";
1048 ti,hwmods = "dss_dsi2";
1049 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
1050 clock-names = "fck", "sys_clk";
1051 };
1052
1053 hdmi: encoder@58060000 {
1054 compatible = "ti,omap5-hdmi";
1055 reg = <0x58040000 0x200>,
1056 <0x58040200 0x80>,
1057 <0x58040300 0x80>,
1058 <0x58060000 0x19000>;
1059 reg-names = "wp", "pll", "phy", "core";
1060 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1061 status = "disabled";
1062 ti,hwmods = "dss_hdmi";
1063 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
1064 clock-names = "fck", "sys_clk";
1065 dmas = <&sdma 76>;
1066 dma-names = "audio_tx";
1067 };
1068 };
1069
1070 abb_mpu: regulator-abb-mpu {
1071 compatible = "ti,abb-v2";
1072 regulator-name = "abb_mpu";
1073 #address-cells = <0>;
1074 #size-cells = <0>;
1075 clocks = <&sys_clkin>;
1076 ti,settling-time = <50>;
1077 ti,clock-cycles = <16>;
1078
1079 reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
1080 <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
1081 reg-names = "base-address", "int-address",
1082 "efuse-address", "ldo-address";
1083 ti,tranxdone-status-mask = <0x80>;
1084 /* LDOVBBMPU_MUX_CTRL */
1085 ti,ldovbb-override-mask = <0x400>;
1086 /* LDOVBBMPU_VSET_OUT */
1087 ti,ldovbb-vset-mask = <0x1F>;
1088
1089 /*
1090 * NOTE: only FBB mode used but actual vset will
1091 * determine final biasing
1092 */
1093 ti,abb_info = <
1094 /*uV ABB efuse rbb_m fbb_m vset_m*/
1095 1060000 0 0x0 0 0x02000000 0x01F00000
1096 1250000 0 0x4 0 0x02000000 0x01F00000
1097 >;
1098 };
1099
1100 abb_mm: regulator-abb-mm {
1101 compatible = "ti,abb-v2";
1102 regulator-name = "abb_mm";
1103 #address-cells = <0>;
1104 #size-cells = <0>;
1105 clocks = <&sys_clkin>;
1106 ti,settling-time = <50>;
1107 ti,clock-cycles = <16>;
1108
1109 reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
1110 <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
1111 reg-names = "base-address", "int-address",
1112 "efuse-address", "ldo-address";
1113 ti,tranxdone-status-mask = <0x80000000>;
1114 /* LDOVBBMM_MUX_CTRL */
1115 ti,ldovbb-override-mask = <0x400>;
1116 /* LDOVBBMM_VSET_OUT */
1117 ti,ldovbb-vset-mask = <0x1F>;
1118
1119 /*
1120 * NOTE: only FBB mode used but actual vset will
1121 * determine final biasing
1122 */
1123 ti,abb_info = <
1124 /*uV ABB efuse rbb_m fbb_m vset_m*/
1125 1025000 0 0x0 0 0x02000000 0x01F00000
1126 1120000 0 0x4 0 0x02000000 0x01F00000
1127 >;
1128 };
1129 };
1130 };
1131
1132 &cpu_thermal {
1133 polling-delay = <500>; /* milliseconds */
1134 };
1135
1136 /include/ "omap54xx-clocks.dtsi"
Linux kernel - Deliverables
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