arch/arm/boot/dts/phy3250.dts

   1 /*
   2  * PHYTEC phyCORE-LPC3250 board
   3  *
   4  * Copyright 2012 Roland Stigge <stigge@antcom.de>
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 /dts-v1/;
  15 /include/ "lpc32xx.dtsi"
  16
  17 / {
  18         model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250";
  19         compatible = "phytec,phy3250", "nxp,lpc3250";
  20         #address-cells = <1>;
  21         #size-cells = <1>;
  22
  23         memory {
  24                 device_type = "memory";
  25                 reg = <0 0x4000000>;
  26         };
  27
  28         ahb {
  29                 mac: ethernet@31060000 {
  30                         phy-mode = "rmii";
  31                         use-iram;
  32                 };
  33
  34                 /* Here, choose exactly one from: ohci, usbd */
  35                 ohci@31020000 {
  36                         transceiver = <&isp1301>;
  37                         status = "okay";
  38                 };
  39
  40 /*
  41                 usbd@31020000 {
  42                         transceiver = <&isp1301>;
  43                         status = "okay";
  44                 };
  45 */
  46
  47                 clcd@31040000 {
  48                         status = "okay";
  49                 };
  50
  51                 /* 64MB Flash via SLC NAND controller */
  52                 slc: flash@20020000 {
  53                         status = "okay";
  54                         #address-cells = <1>;
  55                         #size-cells = <1>;
  56
  57                         mtd0@00000000 {
  58                                 label = "phy3250-boot";
  59                                 reg = <0x00000000 0x00064000>;
  60                                 read-only;
  61                         };
  62
  63                         mtd1@00064000 {
  64                                 label = "phy3250-uboot";
  65                                 reg = <0x00064000 0x00190000>;
  66                                 read-only;
  67                         };
  68
  69                         mtd2@001f4000 {
  70                                 label = "phy3250-ubt-prms";
  71                                 reg = <0x001f4000 0x00010000>;
  72                         };
  73
  74                         mtd3@00204000 {
  75                                 label = "phy3250-kernel";
  76                                 reg = <0x00204000 0x00400000>;
  77                         };
  78
  79                         mtd4@00604000 {
  80                                 label = "phy3250-rootfs";
  81                                 reg = <0x00604000 0x039fc000>;
  82                         };
  83                 };
  84
  85                 apb {
  86                         i2c1: i2c@400A0000 {
  87                                 clock-frequency = <100000>;
  88
  89                                 pcf8563: rtc@51 {
  90                                         compatible = "nxp,pcf8563";
  91                                         reg = <0x51>;
  92                                 };
  93
  94                                 uda1380: uda1380@18 {
  95                                         compatible = "nxp,uda1380";
  96                                         reg = <0x18>;
  97                                         power-gpio = <&gpio 0x59 0>;
  98                                         reset-gpio = <&gpio 0x51 0>;
  99                                         dac-clk = "wspll";
 100                                 };
 101                         };
 102
 103                         i2c2: i2c@400A8000 {
 104                                 clock-frequency = <100000>;
 105                         };
 106
 107                         i2cusb: i2c@31020300 {
 108                                 clock-frequency = <100000>;
 109
 110                                 isp1301: usb-transceiver@2c {
 111                                         compatible = "nxp,isp1301";
 112                                         reg = <0x2c>;
 113                                 };
 114                         };
 115
 116                         ssp0: ssp@20084000 {
 117                                 eeprom: at25@0 {
 118                                         compatible = "atmel,at25";
 119                                 };
 120                         };
 121                 };
 122
 123                 fab {
 124                         tsc@40048000 {
 125                                 status = "okay";
 126                         };
 127                 };
 128         };
 129
 130         leds {
 131                 compatible = "gpio-leds";
 132
 133                 led0 {
 134                         gpios = <&gpio 5 1 1>; /* GPO_P3 1, GPIO 80, active low */
 135                         linux,default-trigger = "heartbeat";
 136                         default-state = "off";
 137                 };
 138
 139                 led1 {
 140                         gpios = <&gpio 5 14 1>; /* GPO_P3 14, GPIO 93, active low */
 141                         linux,default-trigger = "timer";
 142                         default-state = "off";
 143                 };
 144         };
 145 };