3 #include "skeleton.dtsi"
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
6 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
7 #include <dt-bindings/soc/qcom,gsbi.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 model = "Qualcomm APQ8064";
11 compatible = "qcom,apq8064";
12 interrupt-parent = <&intc>;
19 smem_region: smem@80000000 {
20 reg = <0x80000000 0x200000>;
30 compatible = "qcom,krait";
31 enable-method = "qcom,kpss-acc-v1";
34 next-level-cache = <&L2>;
37 cpu-idle-states = <&CPU_SPC>;
41 compatible = "qcom,krait";
42 enable-method = "qcom,kpss-acc-v1";
45 next-level-cache = <&L2>;
48 cpu-idle-states = <&CPU_SPC>;
52 compatible = "qcom,krait";
53 enable-method = "qcom,kpss-acc-v1";
56 next-level-cache = <&L2>;
59 cpu-idle-states = <&CPU_SPC>;
63 compatible = "qcom,krait";
64 enable-method = "qcom,kpss-acc-v1";
67 next-level-cache = <&L2>;
70 cpu-idle-states = <&CPU_SPC>;
80 compatible = "qcom,idle-state-spc",
82 entry-latency-us = <400>;
83 exit-latency-us = <900>;
84 min-residency-us = <3000>;
90 compatible = "qcom,krait-pmu";
91 interrupts = <1 10 0x304>;
96 compatible = "fixed-clock";
98 clock-frequency = <19200000>;
102 compatible = "fixed-clock";
104 clock-frequency = <27000000>;
108 compatible = "fixed-clock";
110 clock-frequency = <32768>;
114 sfpb_mutex: hwmutex {
115 compatible = "qcom,sfpb-mutex";
116 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
121 compatible = "qcom,smem";
122 memory-region = <&smem_region>;
124 hwlocks = <&sfpb_mutex 3>;
128 compatible = "qcom,smd";
131 interrupts = <0 37 IRQ_TYPE_EDGE_RISING>;
133 qcom,ipc = <&l2cc 8 3>;
140 interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;
142 qcom,ipc = <&l2cc 8 15>;
149 interrupts = <0 138 IRQ_TYPE_EDGE_RISING>;
151 qcom,ipc = <&sps_sic_non_secure 0x4080 0>;
158 interrupts = <0 198 IRQ_TYPE_EDGE_RISING>;
160 qcom,ipc = <&l2cc 8 25>;
168 compatible = "qcom,smsm";
170 #address-cells = <1>;
173 qcom,ipc-1 = <&l2cc 8 4>;
174 qcom,ipc-2 = <&l2cc 8 14>;
175 qcom,ipc-3 = <&l2cc 8 23>;
176 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
180 #qcom,smem-state-cells = <1>;
183 modem_smsm: modem@1 {
185 interrupts = <0 38 IRQ_TYPE_EDGE_RISING>;
187 interrupt-controller;
188 #interrupt-cells = <2>;
193 interrupts = <0 89 IRQ_TYPE_EDGE_RISING>;
195 interrupt-controller;
196 #interrupt-cells = <2>;
199 wcnss_smsm: wcnss@3 {
201 interrupts = <0 204 IRQ_TYPE_EDGE_RISING>;
203 interrupt-controller;
204 #interrupt-cells = <2>;
209 interrupts = <0 137 IRQ_TYPE_EDGE_RISING>;
211 interrupt-controller;
212 #interrupt-cells = <2>;
218 compatible = "qcom,scm-apq8064";
223 #address-cells = <1>;
226 compatible = "simple-bus";
228 tlmm_pinmux: pinctrl@800000 {
229 compatible = "qcom,apq8064-pinctrl";
230 reg = <0x800000 0x4000>;
234 interrupt-controller;
235 #interrupt-cells = <2>;
236 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
238 pinctrl-names = "default";
239 pinctrl-0 = <&ps_hold>;
242 sfpb_wrapper_mutex: syscon@1200000 {
243 compatible = "syscon";
244 reg = <0x01200000 0x8000>;
247 intc: interrupt-controller@2000000 {
248 compatible = "qcom,msm-qgic2";
249 interrupt-controller;
250 #interrupt-cells = <3>;
251 reg = <0x02000000 0x1000>,
256 compatible = "qcom,kpss-timer",
257 "qcom,kpss-wdt-apq8064", "qcom,msm-timer";
258 interrupts = <1 1 0x301>,
261 reg = <0x0200a000 0x100>;
262 clock-frequency = <27000000>,
264 cpu-offset = <0x80000>;
267 acc0: clock-controller@2088000 {
268 compatible = "qcom,kpss-acc-v1";
269 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
272 acc1: clock-controller@2098000 {
273 compatible = "qcom,kpss-acc-v1";
274 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
277 acc2: clock-controller@20a8000 {
278 compatible = "qcom,kpss-acc-v1";
279 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
282 acc3: clock-controller@20b8000 {
283 compatible = "qcom,kpss-acc-v1";
284 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
287 saw0: power-controller@2089000 {
288 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
289 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
293 saw1: power-controller@2099000 {
294 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
295 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
299 saw2: power-controller@20a9000 {
300 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
301 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
305 saw3: power-controller@20b9000 {
306 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
307 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
311 sps_sic_non_secure: sps-sic-non-secure@12100000 {
312 compatible = "syscon";
313 reg = <0x12100000 0x10000>;
316 gsbi1: gsbi@12440000 {
318 compatible = "qcom,gsbi-v1.0.0";
320 reg = <0x12440000 0x100>;
321 clocks = <&gcc GSBI1_H_CLK>;
322 clock-names = "iface";
323 #address-cells = <1>;
327 syscon-tcsr = <&tcsr>;
329 gsbi1_serial: serial@12450000 {
330 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
331 reg = <0x12450000 0x100>,
333 interrupts = <0 193 0x0>;
334 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
335 clock-names = "core", "iface";
339 gsbi1_i2c: i2c@12460000 {
340 compatible = "qcom,i2c-qup-v1.1.1";
341 pinctrl-0 = <&i2c1_pins>;
342 pinctrl-1 = <&i2c1_pins_sleep>;
343 pinctrl-names = "default", "sleep";
344 reg = <0x12460000 0x1000>;
345 interrupts = <0 194 IRQ_TYPE_NONE>;
346 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
347 clock-names = "core", "iface";
348 #address-cells = <1>;
354 gsbi2: gsbi@12480000 {
356 compatible = "qcom,gsbi-v1.0.0";
358 reg = <0x12480000 0x100>;
359 clocks = <&gcc GSBI2_H_CLK>;
360 clock-names = "iface";
361 #address-cells = <1>;
365 syscon-tcsr = <&tcsr>;
367 gsbi2_i2c: i2c@124a0000 {
368 compatible = "qcom,i2c-qup-v1.1.1";
369 reg = <0x124a0000 0x1000>;
370 pinctrl-0 = <&i2c2_pins>;
371 pinctrl-1 = <&i2c2_pins_sleep>;
372 pinctrl-names = "default", "sleep";
373 interrupts = <0 196 IRQ_TYPE_NONE>;
374 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
375 clock-names = "core", "iface";
376 #address-cells = <1>;
381 gsbi3: gsbi@16200000 {
383 compatible = "qcom,gsbi-v1.0.0";
385 reg = <0x16200000 0x100>;
386 clocks = <&gcc GSBI3_H_CLK>;
387 clock-names = "iface";
388 #address-cells = <1>;
391 gsbi3_i2c: i2c@16280000 {
392 compatible = "qcom,i2c-qup-v1.1.1";
393 pinctrl-0 = <&i2c3_pins>;
394 pinctrl-1 = <&i2c3_pins_sleep>;
395 pinctrl-names = "default", "sleep";
396 reg = <0x16280000 0x1000>;
397 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
398 clocks = <&gcc GSBI3_QUP_CLK>,
400 clock-names = "core", "iface";
401 #address-cells = <1>;
406 gsbi4: gsbi@16300000 {
408 compatible = "qcom,gsbi-v1.0.0";
410 reg = <0x16300000 0x03>;
411 clocks = <&gcc GSBI4_H_CLK>;
412 clock-names = "iface";
413 #address-cells = <1>;
417 gsbi4_i2c: i2c@16380000 {
418 compatible = "qcom,i2c-qup-v1.1.1";
419 pinctrl-0 = <&i2c4_pins>;
420 pinctrl-1 = <&i2c4_pins_sleep>;
421 pinctrl-names = "default", "sleep";
422 reg = <0x16380000 0x1000>;
423 interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
424 clocks = <&gcc GSBI4_QUP_CLK>,
426 clock-names = "core", "iface";
430 gsbi5: gsbi@1a200000 {
432 compatible = "qcom,gsbi-v1.0.0";
434 reg = <0x1a200000 0x03>;
435 clocks = <&gcc GSBI5_H_CLK>;
436 clock-names = "iface";
437 #address-cells = <1>;
441 gsbi5_serial: serial@1a240000 {
442 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
443 reg = <0x1a240000 0x100>,
445 interrupts = <0 154 0x0>;
446 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
447 clock-names = "core", "iface";
451 gsbi5_spi: spi@1a280000 {
452 compatible = "qcom,spi-qup-v1.1.1";
453 reg = <0x1a280000 0x1000>;
454 interrupts = <0 155 0>;
455 pinctrl-0 = <&spi5_default>;
456 pinctrl-1 = <&spi5_sleep>;
457 pinctrl-names = "default", "sleep";
458 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
459 clock-names = "core", "iface";
461 #address-cells = <1>;
466 gsbi6: gsbi@16500000 {
468 compatible = "qcom,gsbi-v1.0.0";
470 reg = <0x16500000 0x03>;
471 clocks = <&gcc GSBI6_H_CLK>;
472 clock-names = "iface";
473 #address-cells = <1>;
477 gsbi6_serial: serial@16540000 {
478 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
479 reg = <0x16540000 0x100>,
481 interrupts = <0 156 0x0>;
482 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
483 clock-names = "core", "iface";
487 gsbi6_i2c: i2c@16580000 {
488 compatible = "qcom,i2c-qup-v1.1.1";
489 pinctrl-0 = <&i2c6_pins>;
490 pinctrl-1 = <&i2c6_pins_sleep>;
491 pinctrl-names = "default", "sleep";
492 reg = <0x16580000 0x1000>;
493 interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
494 clocks = <&gcc GSBI6_QUP_CLK>,
496 clock-names = "core", "iface";
500 gsbi7: gsbi@16600000 {
502 compatible = "qcom,gsbi-v1.0.0";
504 reg = <0x16600000 0x100>;
505 clocks = <&gcc GSBI7_H_CLK>;
506 clock-names = "iface";
507 #address-cells = <1>;
510 syscon-tcsr = <&tcsr>;
512 gsbi7_serial: serial@16640000 {
513 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
514 reg = <0x16640000 0x1000>,
516 interrupts = <0 158 0x0>;
517 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
518 clock-names = "core", "iface";
522 gsbi7_i2c: i2c@16680000 {
523 compatible = "qcom,i2c-qup-v1.1.1";
524 pinctrl-0 = <&i2c7_pins>;
525 pinctrl-1 = <&i2c7_pins_sleep>;
526 pinctrl-names = "default", "sleep";
527 reg = <0x16680000 0x1000>;
528 interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
529 clocks = <&gcc GSBI7_QUP_CLK>,
531 clock-names = "core", "iface";
537 compatible = "qcom,prng";
538 reg = <0x1a500000 0x200>;
539 clocks = <&gcc PRNG_CLK>;
540 clock-names = "core";
544 compatible = "qcom,ssbi";
545 reg = <0x00500000 0x1000>;
546 qcom,controller-type = "pmic-arbiter";
549 compatible = "qcom,pm8921";
550 interrupt-parent = <&tlmm_pinmux>;
552 #interrupt-cells = <2>;
553 interrupt-controller;
554 #address-cells = <1>;
557 pm8921_gpio: gpio@150 {
559 compatible = "qcom,pm8921-gpio",
562 interrupts = <192 1>, <193 1>, <194 1>,
563 <195 1>, <196 1>, <197 1>,
564 <198 1>, <199 1>, <200 1>,
565 <201 1>, <202 1>, <203 1>,
566 <204 1>, <205 1>, <206 1>,
567 <207 1>, <208 1>, <209 1>,
568 <210 1>, <211 1>, <212 1>,
569 <213 1>, <214 1>, <215 1>,
570 <216 1>, <217 1>, <218 1>,
571 <219 1>, <220 1>, <221 1>,
572 <222 1>, <223 1>, <224 1>,
573 <225 1>, <226 1>, <227 1>,
574 <228 1>, <229 1>, <230 1>,
575 <231 1>, <232 1>, <233 1>,
583 pm8921_mpps: mpps@50 {
584 compatible = "qcom,pm8921-mpp",
590 <128 1>, <129 1>, <130 1>, <131 1>,
591 <132 1>, <133 1>, <134 1>, <135 1>,
592 <136 1>, <137 1>, <138 1>, <139 1>;
596 compatible = "qcom,pm8921-rtc";
597 interrupt-parent = <&pmicintc>;
604 compatible = "qcom,pm8921-pwrkey";
606 interrupt-parent = <&pmicintc>;
607 interrupts = <50 1>, <51 1>;
614 gcc: clock-controller@900000 {
615 compatible = "qcom,gcc-apq8064";
616 reg = <0x00900000 0x4000>;
621 lcc: clock-controller@28000000 {
622 compatible = "qcom,lcc-apq8064";
623 reg = <0x28000000 0x1000>;
628 mmcc: clock-controller@4000000 {
629 compatible = "qcom,mmcc-apq8064";
630 reg = <0x4000000 0x1000>;
635 l2cc: clock-controller@2011000 {
636 compatible = "syscon";
637 reg = <0x2011000 0x1000>;
641 compatible = "qcom,rpm-apq8064";
642 reg = <0x108000 0x1000>;
643 qcom,ipc = <&l2cc 0x8 2>;
645 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
646 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
647 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
648 interrupt-names = "ack", "err", "wakeup";
650 rpmcc: clock-controller {
651 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
656 compatible = "qcom,rpm-pm8921-regulators";
692 pm8921_lvs1: lvs1 {};
693 pm8921_lvs2: lvs2 {};
694 pm8921_lvs3: lvs3 {};
695 pm8921_lvs4: lvs4 {};
696 pm8921_lvs5: lvs5 {};
697 pm8921_lvs6: lvs6 {};
698 pm8921_lvs7: lvs7 {};
700 pm8921_usb_switch: usb-switch {};
702 pm8921_hdmi_switch: hdmi-switch {
710 usb1_phy: phy@12500000 {
711 compatible = "qcom,usb-otg-ci";
712 reg = <0x12500000 0x400>;
713 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
717 clocks = <&gcc USB_HS1_XCVR_CLK>,
718 <&gcc USB_HS1_H_CLK>;
719 clock-names = "core", "iface";
721 resets = <&gcc USB_HS1_RESET>;
722 reset-names = "link";
725 usb3_phy: phy@12520000 {
726 compatible = "qcom,usb-otg-ci";
727 reg = <0x12520000 0x400>;
728 interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
732 clocks = <&gcc USB_HS3_XCVR_CLK>,
733 <&gcc USB_HS3_H_CLK>;
734 clock-names = "core", "iface";
736 resets = <&gcc USB_HS3_RESET>;
737 reset-names = "link";
740 usb4_phy: phy@12530000 {
741 compatible = "qcom,usb-otg-ci";
742 reg = <0x12530000 0x400>;
743 interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
747 clocks = <&gcc USB_HS4_XCVR_CLK>,
748 <&gcc USB_HS4_H_CLK>;
749 clock-names = "core", "iface";
751 resets = <&gcc USB_HS4_RESET>;
752 reset-names = "link";
755 gadget1: gadget@12500000 {
756 compatible = "qcom,ci-hdrc";
757 reg = <0x12500000 0x400>;
759 dr_mode = "peripheral";
760 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
761 usb-phy = <&usb1_phy>;
765 compatible = "qcom,ehci-host";
766 reg = <0x12500000 0x400>;
767 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
769 usb-phy = <&usb1_phy>;
773 compatible = "qcom,ehci-host";
774 reg = <0x12520000 0x400>;
775 interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
777 usb-phy = <&usb3_phy>;
781 compatible = "qcom,ehci-host";
782 reg = <0x12530000 0x400>;
783 interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
785 usb-phy = <&usb4_phy>;
788 sata_phy0: phy@1b400000 {
789 compatible = "qcom,apq8064-sata-phy";
791 reg = <0x1b400000 0x200>;
792 reg-names = "phy_mem";
793 clocks = <&gcc SATA_PHY_CFG_CLK>;
798 sata0: sata@29000000 {
799 compatible = "qcom,apq8064-ahci", "generic-ahci";
801 reg = <0x29000000 0x180>;
802 interrupts = <GIC_SPI 209 IRQ_TYPE_NONE>;
804 clocks = <&gcc SFAB_SATA_S_H_CLK>,
807 <&gcc SATA_RXOOB_CLK>,
808 <&gcc SATA_PMALIVE_CLK>;
809 clock-names = "slave_iface",
815 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
816 <&gcc SATA_PMALIVE_CLK>;
817 assigned-clock-rates = <100000000>, <100000000>;
820 phy-names = "sata-phy";
821 ports-implemented = <0x1>;
824 /* Temporary fixed regulator */
825 sdcc1bam:dma@12402000{
826 compatible = "qcom,bam-v1.3.0";
827 reg = <0x12402000 0x8000>;
828 interrupts = <0 98 0>;
829 clocks = <&gcc SDC1_H_CLK>;
830 clock-names = "bam_clk";
835 sdcc3bam:dma@12182000{
836 compatible = "qcom,bam-v1.3.0";
837 reg = <0x12182000 0x8000>;
838 interrupts = <0 96 0>;
839 clocks = <&gcc SDC3_H_CLK>;
840 clock-names = "bam_clk";
845 sdcc4bam:dma@121c2000{
846 compatible = "qcom,bam-v1.3.0";
847 reg = <0x121c2000 0x8000>;
848 interrupts = <0 95 0>;
849 clocks = <&gcc SDC4_H_CLK>;
850 clock-names = "bam_clk";
856 compatible = "simple-bus";
857 #address-cells = <1>;
860 sdcc1: sdcc@12400000 {
862 compatible = "arm,pl18x", "arm,primecell";
863 pinctrl-names = "default";
864 pinctrl-0 = <&sdcc1_pins>;
865 arm,primecell-periphid = <0x00051180>;
866 reg = <0x12400000 0x2000>;
867 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
868 interrupt-names = "cmd_irq";
869 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
870 clock-names = "mclk", "apb_pclk";
872 max-frequency = <96000000>;
876 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
877 dma-names = "tx", "rx";
880 sdcc3: sdcc@12180000 {
881 compatible = "arm,pl18x", "arm,primecell";
882 arm,primecell-periphid = <0x00051180>;
884 reg = <0x12180000 0x2000>;
885 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
886 interrupt-names = "cmd_irq";
887 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
888 clock-names = "mclk", "apb_pclk";
892 max-frequency = <192000000>;
894 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
895 dma-names = "tx", "rx";
898 sdcc4: sdcc@121c0000 {
899 compatible = "arm,pl18x", "arm,primecell";
900 arm,primecell-periphid = <0x00051180>;
902 reg = <0x121c0000 0x2000>;
903 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
904 interrupt-names = "cmd_irq";
905 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
906 clock-names = "mclk", "apb_pclk";
910 max-frequency = <48000000>;
911 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
912 dma-names = "tx", "rx";
913 pinctrl-names = "default";
914 pinctrl-0 = <&sdc4_gpios>;
918 tcsr: syscon@1a400000 {
919 compatible = "qcom,tcsr-apq8064", "syscon";
920 reg = <0x1a400000 0x100>;
924 compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
925 reg = <0x1b500000 0x1000
928 0x0ff00000 0x100000>;
929 reg-names = "dbi", "elbi", "parf", "config";
931 linux,pci-domain = <0>;
932 bus-range = <0x00 0xff>;
934 #address-cells = <3>;
936 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
937 0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
938 interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
939 interrupt-names = "msi";
940 #interrupt-cells = <1>;
941 interrupt-map-mask = <0 0 0 0x7>;
942 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
943 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
944 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
945 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
946 clocks = <&gcc PCIE_A_CLK>,
948 <&gcc PCIE_PHY_REF_CLK>;
949 clock-names = "core", "iface", "phy";
950 resets = <&gcc PCIE_ACLK_RESET>,
951 <&gcc PCIE_HCLK_RESET>,
952 <&gcc PCIE_POR_RESET>,
953 <&gcc PCIE_PCI_RESET>,
954 <&gcc PCIE_PHY_RESET>;
955 reset-names = "axi", "ahb", "por", "pci", "phy";
960 #include "qcom-apq8064-pins.dtsi"