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ARM: dts: apq8064: fix missing gsbi cell-index
[deliverable/linux.git] / arch / arm / boot / dts / qcom-apq8064.dtsi
1 /dts-v1/;
2
3 #include "skeleton.dtsi"
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
6 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
7 #include <dt-bindings/soc/qcom,gsbi.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 / {
10 model = "Qualcomm APQ8064";
11 compatible = "qcom,apq8064";
12 interrupt-parent = <&intc>;
13
14 cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
17
18 cpu@0 {
19 compatible = "qcom,krait";
20 enable-method = "qcom,kpss-acc-v1";
21 device_type = "cpu";
22 reg = <0>;
23 next-level-cache = <&L2>;
24 qcom,acc = <&acc0>;
25 qcom,saw = <&saw0>;
26 cpu-idle-states = <&CPU_SPC>;
27 };
28
29 cpu@1 {
30 compatible = "qcom,krait";
31 enable-method = "qcom,kpss-acc-v1";
32 device_type = "cpu";
33 reg = <1>;
34 next-level-cache = <&L2>;
35 qcom,acc = <&acc1>;
36 qcom,saw = <&saw1>;
37 cpu-idle-states = <&CPU_SPC>;
38 };
39
40 cpu@2 {
41 compatible = "qcom,krait";
42 enable-method = "qcom,kpss-acc-v1";
43 device_type = "cpu";
44 reg = <2>;
45 next-level-cache = <&L2>;
46 qcom,acc = <&acc2>;
47 qcom,saw = <&saw2>;
48 cpu-idle-states = <&CPU_SPC>;
49 };
50
51 cpu@3 {
52 compatible = "qcom,krait";
53 enable-method = "qcom,kpss-acc-v1";
54 device_type = "cpu";
55 reg = <3>;
56 next-level-cache = <&L2>;
57 qcom,acc = <&acc3>;
58 qcom,saw = <&saw3>;
59 cpu-idle-states = <&CPU_SPC>;
60 };
61
62 L2: l2-cache {
63 compatible = "cache";
64 cache-level = <2>;
65 };
66
67 idle-states {
68 CPU_SPC: spc {
69 compatible = "qcom,idle-state-spc",
70 "arm,idle-state";
71 entry-latency-us = <400>;
72 exit-latency-us = <900>;
73 min-residency-us = <3000>;
74 };
75 };
76 };
77
78 cpu-pmu {
79 compatible = "qcom,krait-pmu";
80 interrupts = <1 10 0x304>;
81 };
82
83 soc: soc {
84 #address-cells = <1>;
85 #size-cells = <1>;
86 ranges;
87 compatible = "simple-bus";
88
89 tlmm_pinmux: pinctrl@800000 {
90 compatible = "qcom,apq8064-pinctrl";
91 reg = <0x800000 0x4000>;
92
93 gpio-controller;
94 #gpio-cells = <2>;
95 interrupt-controller;
96 #interrupt-cells = <2>;
97 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
98
99 pinctrl-names = "default";
100 pinctrl-0 = <&ps_hold>;
101
102 sdc4_gpios: sdc4-gpios {
103 pios {
104 pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
105 function = "sdc4";
106 };
107 };
108
109 ps_hold: ps_hold {
110 mux {
111 pins = "gpio78";
112 function = "ps_hold";
113 };
114 };
115
116 i2c1_pins: i2c1 {
117 mux {
118 pins = "gpio20", "gpio21";
119 function = "gsbi1";
120 };
121 };
122
123 i2c3_pins: i2c3 {
124 mux {
125 pins = "gpio8", "gpio9";
126 function = "gsbi3";
127 };
128 };
129
130 uart_pins: uart_pins {
131 mux {
132 pins = "gpio14", "gpio15", "gpio16", "gpio17";
133 function = "gsbi6";
134 };
135 };
136 };
137
138 intc: interrupt-controller@2000000 {
139 compatible = "qcom,msm-qgic2";
140 interrupt-controller;
141 #interrupt-cells = <3>;
142 reg = <0x02000000 0x1000>,
143 <0x02002000 0x1000>;
144 };
145
146 timer@200a000 {
147 compatible = "qcom,kpss-timer", "qcom,msm-timer";
148 interrupts = <1 1 0x301>,
149 <1 2 0x301>,
150 <1 3 0x301>;
151 reg = <0x0200a000 0x100>;
152 clock-frequency = <27000000>,
153 <32768>;
154 cpu-offset = <0x80000>;
155 };
156
157 acc0: clock-controller@2088000 {
158 compatible = "qcom,kpss-acc-v1";
159 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
160 };
161
162 acc1: clock-controller@2098000 {
163 compatible = "qcom,kpss-acc-v1";
164 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
165 };
166
167 acc2: clock-controller@20a8000 {
168 compatible = "qcom,kpss-acc-v1";
169 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
170 };
171
172 acc3: clock-controller@20b8000 {
173 compatible = "qcom,kpss-acc-v1";
174 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
175 };
176
177 saw0: power-controller@2089000 {
178 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
179 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
180 regulator;
181 };
182
183 saw1: power-controller@2099000 {
184 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
185 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
186 regulator;
187 };
188
189 saw2: power-controller@20a9000 {
190 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
191 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
192 regulator;
193 };
194
195 saw3: power-controller@20b9000 {
196 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
197 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
198 regulator;
199 };
200
201 gsbi1: gsbi@12440000 {
202 status = "disabled";
203 compatible = "qcom,gsbi-v1.0.0";
204 cell-index = <1>;
205 reg = <0x12440000 0x100>;
206 clocks = <&gcc GSBI1_H_CLK>;
207 clock-names = "iface";
208 #address-cells = <1>;
209 #size-cells = <1>;
210 ranges;
211
212 syscon-tcsr = <&tcsr>;
213
214 i2c1: i2c@12460000 {
215 compatible = "qcom,i2c-qup-v1.1.1";
216 reg = <0x12460000 0x1000>;
217 interrupts = <0 194 IRQ_TYPE_NONE>;
218 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
219 clock-names = "core", "iface";
220 #address-cells = <1>;
221 #size-cells = <0>;
222 };
223 };
224
225 gsbi2: gsbi@12480000 {
226 status = "disabled";
227 compatible = "qcom,gsbi-v1.0.0";
228 cell-index = <2>;
229 reg = <0x12480000 0x100>;
230 clocks = <&gcc GSBI2_H_CLK>;
231 clock-names = "iface";
232 #address-cells = <1>;
233 #size-cells = <1>;
234 ranges;
235
236 syscon-tcsr = <&tcsr>;
237
238 i2c2: i2c@124a0000 {
239 compatible = "qcom,i2c-qup-v1.1.1";
240 reg = <0x124a0000 0x1000>;
241 interrupts = <0 196 IRQ_TYPE_NONE>;
242 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
243 clock-names = "core", "iface";
244 #address-cells = <1>;
245 #size-cells = <0>;
246 };
247 };
248
249 gsbi3: gsbi@16200000 {
250 status = "disabled";
251 compatible = "qcom,gsbi-v1.0.0";
252 cell-index = <3>;
253 reg = <0x16200000 0x100>;
254 clocks = <&gcc GSBI3_H_CLK>;
255 clock-names = "iface";
256 #address-cells = <1>;
257 #size-cells = <1>;
258 ranges;
259 i2c3: i2c@16280000 {
260 compatible = "qcom,i2c-qup-v1.1.1";
261 reg = <0x16280000 0x1000>;
262 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
263 clocks = <&gcc GSBI3_QUP_CLK>,
264 <&gcc GSBI3_H_CLK>;
265 clock-names = "core", "iface";
266 };
267 };
268
269 gsbi6: gsbi@16500000 {
270 status = "disabled";
271 compatible = "qcom,gsbi-v1.0.0";
272 cell-index = <6>;
273 reg = <0x16500000 0x03>;
274 clocks = <&gcc GSBI6_H_CLK>;
275 clock-names = "iface";
276 #address-cells = <1>;
277 #size-cells = <1>;
278 ranges;
279
280 gsbi6_serial: serial@16540000 {
281 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
282 reg = <0x16540000 0x100>,
283 <0x16500000 0x03>;
284 interrupts = <0 156 0x0>;
285 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
286 clock-names = "core", "iface";
287 status = "disabled";
288 };
289 };
290
291 gsbi7: gsbi@16600000 {
292 status = "disabled";
293 compatible = "qcom,gsbi-v1.0.0";
294 cell-index = <7>;
295 reg = <0x16600000 0x100>;
296 clocks = <&gcc GSBI7_H_CLK>;
297 clock-names = "iface";
298 #address-cells = <1>;
299 #size-cells = <1>;
300 ranges;
301 syscon-tcsr = <&tcsr>;
302
303 gsbi7_serial: serial@16640000 {
304 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
305 reg = <0x16640000 0x1000>,
306 <0x16600000 0x1000>;
307 interrupts = <0 158 0x0>;
308 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
309 clock-names = "core", "iface";
310 status = "disabled";
311 };
312 };
313
314 qcom,ssbi@500000 {
315 compatible = "qcom,ssbi";
316 reg = <0x00500000 0x1000>;
317 qcom,controller-type = "pmic-arbiter";
318
319 pmicintc: pmic@0 {
320 compatible = "qcom,pm8921";
321 interrupt-parent = <&tlmm_pinmux>;
322 interrupts = <74 8>;
323 #interrupt-cells = <2>;
324 interrupt-controller;
325 #address-cells = <1>;
326 #size-cells = <0>;
327
328 pm8921_gpio: gpio@150 {
329
330 compatible = "qcom,pm8921-gpio";
331 reg = <0x150>;
332 interrupts = <192 1>, <193 1>, <194 1>,
333 <195 1>, <196 1>, <197 1>,
334 <198 1>, <199 1>, <200 1>,
335 <201 1>, <202 1>, <203 1>,
336 <204 1>, <205 1>, <206 1>,
337 <207 1>, <208 1>, <209 1>,
338 <210 1>, <211 1>, <212 1>,
339 <213 1>, <214 1>, <215 1>,
340 <216 1>, <217 1>, <218 1>,
341 <219 1>, <220 1>, <221 1>,
342 <222 1>, <223 1>, <224 1>,
343 <225 1>, <226 1>, <227 1>,
344 <228 1>, <229 1>, <230 1>,
345 <231 1>, <232 1>, <233 1>,
346 <234 1>, <235 1>;
347
348 gpio-controller;
349 #gpio-cells = <2>;
350
351 };
352
353 pm8921_mpps: mpps@50 {
354 compatible = "qcom,pm8921-mpp";
355 reg = <0x50>;
356 gpio-controller;
357 #gpio-cells = <2>;
358 interrupts =
359 <128 1>, <129 1>, <130 1>, <131 1>,
360 <132 1>, <133 1>, <134 1>, <135 1>,
361 <136 1>, <137 1>, <138 1>, <139 1>;
362 };
363
364 };
365 };
366
367 gcc: clock-controller@900000 {
368 compatible = "qcom,gcc-apq8064";
369 reg = <0x00900000 0x4000>;
370 #clock-cells = <1>;
371 #reset-cells = <1>;
372 };
373
374 lcc: clock-controller@28000000 {
375 compatible = "qcom,lcc-apq8064";
376 reg = <0x28000000 0x1000>;
377 #clock-cells = <1>;
378 #reset-cells = <1>;
379 };
380
381 mmcc: clock-controller@4000000 {
382 compatible = "qcom,mmcc-apq8064";
383 reg = <0x4000000 0x1000>;
384 #clock-cells = <1>;
385 #reset-cells = <1>;
386 };
387
388 l2cc: clock-controller@2011000 {
389 compatible = "syscon";
390 reg = <0x2011000 0x1000>;
391 };
392
393 rpm@108000 {
394 compatible = "qcom,rpm-apq8064";
395 reg = <0x108000 0x1000>;
396 qcom,ipc = <&l2cc 0x8 2>;
397
398 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
399 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
400 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
401 interrupt-names = "ack", "err", "wakeup";
402
403 regulators {
404 compatible = "qcom,rpm-pm8921-regulators";
405
406 pm8921_hdmi_switch: hdmi-switch {
407 bias-pull-down;
408 };
409 };
410 };
411
412 usb1_phy: phy@12500000 {
413 compatible = "qcom,usb-otg-ci";
414 reg = <0x12500000 0x400>;
415 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
416 status = "disabled";
417 dr_mode = "host";
418
419 clocks = <&gcc USB_HS1_XCVR_CLK>,
420 <&gcc USB_HS1_H_CLK>;
421 clock-names = "core", "iface";
422
423 resets = <&gcc USB_HS1_RESET>;
424 reset-names = "link";
425 };
426
427 usb3_phy: phy@12520000 {
428 compatible = "qcom,usb-otg-ci";
429 reg = <0x12520000 0x400>;
430 interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
431 status = "disabled";
432 dr_mode = "host";
433
434 clocks = <&gcc USB_HS3_XCVR_CLK>,
435 <&gcc USB_HS3_H_CLK>;
436 clock-names = "core", "iface";
437
438 resets = <&gcc USB_HS3_RESET>;
439 reset-names = "link";
440 };
441
442 usb4_phy: phy@12530000 {
443 compatible = "qcom,usb-otg-ci";
444 reg = <0x12530000 0x400>;
445 interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
446 status = "disabled";
447 dr_mode = "host";
448
449 clocks = <&gcc USB_HS4_XCVR_CLK>,
450 <&gcc USB_HS4_H_CLK>;
451 clock-names = "core", "iface";
452
453 resets = <&gcc USB_HS4_RESET>;
454 reset-names = "link";
455 };
456
457 gadget1: gadget@12500000 {
458 compatible = "qcom,ci-hdrc";
459 reg = <0x12500000 0x400>;
460 status = "disabled";
461 dr_mode = "peripheral";
462 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
463 usb-phy = <&usb1_phy>;
464 };
465
466 usb1: usb@12500000 {
467 compatible = "qcom,ehci-host";
468 reg = <0x12500000 0x400>;
469 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
470 status = "disabled";
471 usb-phy = <&usb1_phy>;
472 };
473
474 usb3: usb@12520000 {
475 compatible = "qcom,ehci-host";
476 reg = <0x12520000 0x400>;
477 interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
478 status = "disabled";
479 usb-phy = <&usb3_phy>;
480 };
481
482 usb4: usb@12530000 {
483 compatible = "qcom,ehci-host";
484 reg = <0x12530000 0x400>;
485 interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
486 status = "disabled";
487 usb-phy = <&usb4_phy>;
488 };
489
490 sata_phy0: phy@1b400000 {
491 compatible = "qcom,apq8064-sata-phy";
492 status = "disabled";
493 reg = <0x1b400000 0x200>;
494 reg-names = "phy_mem";
495 clocks = <&gcc SATA_PHY_CFG_CLK>;
496 clock-names = "cfg";
497 #phy-cells = <0>;
498 };
499
500 sata0: sata@29000000 {
501 compatible = "generic-ahci";
502 status = "disabled";
503 reg = <0x29000000 0x180>;
504 interrupts = <GIC_SPI 209 IRQ_TYPE_NONE>;
505
506 clocks = <&gcc SFAB_SATA_S_H_CLK>,
507 <&gcc SATA_H_CLK>,
508 <&gcc SATA_A_CLK>,
509 <&gcc SATA_RXOOB_CLK>,
510 <&gcc SATA_PMALIVE_CLK>;
511 clock-names = "slave_iface",
512 "iface",
513 "bus",
514 "rxoob",
515 "core_pmalive";
516
517 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
518 <&gcc SATA_PMALIVE_CLK>;
519 assigned-clock-rates = <100000000>, <100000000>;
520
521 phys = <&sata_phy0>;
522 phy-names = "sata-phy";
523 };
524
525 /* Temporary fixed regulator */
526 vsdcc_fixed: vsdcc-regulator {
527 compatible = "regulator-fixed";
528 regulator-name = "SDCC Power";
529 regulator-min-microvolt = <2700000>;
530 regulator-max-microvolt = <2700000>;
531 regulator-always-on;
532 };
533
534 sdcc1bam:dma@12402000{
535 compatible = "qcom,bam-v1.3.0";
536 reg = <0x12402000 0x8000>;
537 interrupts = <0 98 0>;
538 clocks = <&gcc SDC1_H_CLK>;
539 clock-names = "bam_clk";
540 #dma-cells = <1>;
541 qcom,ee = <0>;
542 };
543
544 sdcc3bam:dma@12182000{
545 compatible = "qcom,bam-v1.3.0";
546 reg = <0x12182000 0x8000>;
547 interrupts = <0 96 0>;
548 clocks = <&gcc SDC3_H_CLK>;
549 clock-names = "bam_clk";
550 #dma-cells = <1>;
551 qcom,ee = <0>;
552 };
553
554 sdcc4bam:dma@121c2000{
555 compatible = "qcom,bam-v1.3.0";
556 reg = <0x121c2000 0x8000>;
557 interrupts = <0 95 0>;
558 clocks = <&gcc SDC4_H_CLK>;
559 clock-names = "bam_clk";
560 #dma-cells = <1>;
561 qcom,ee = <0>;
562 };
563
564 amba {
565 compatible = "arm,amba-bus";
566 #address-cells = <1>;
567 #size-cells = <1>;
568 ranges;
569 sdcc1: sdcc@12400000 {
570 status = "disabled";
571 compatible = "arm,pl18x", "arm,primecell";
572 arm,primecell-periphid = <0x00051180>;
573 reg = <0x12400000 0x2000>;
574 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
575 interrupt-names = "cmd_irq";
576 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
577 clock-names = "mclk", "apb_pclk";
578 bus-width = <8>;
579 max-frequency = <96000000>;
580 non-removable;
581 cap-sd-highspeed;
582 cap-mmc-highspeed;
583 vmmc-supply = <&vsdcc_fixed>;
584 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
585 dma-names = "tx", "rx";
586 };
587
588 sdcc3: sdcc@12180000 {
589 compatible = "arm,pl18x", "arm,primecell";
590 arm,primecell-periphid = <0x00051180>;
591 status = "disabled";
592 reg = <0x12180000 0x2000>;
593 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
594 interrupt-names = "cmd_irq";
595 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
596 clock-names = "mclk", "apb_pclk";
597 bus-width = <4>;
598 cap-sd-highspeed;
599 cap-mmc-highspeed;
600 max-frequency = <192000000>;
601 no-1-8-v;
602 vmmc-supply = <&vsdcc_fixed>;
603 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
604 dma-names = "tx", "rx";
605 };
606
607 sdcc4: sdcc@121c0000 {
608 compatible = "arm,pl18x", "arm,primecell";
609 arm,primecell-periphid = <0x00051180>;
610 status = "disabled";
611 reg = <0x121c0000 0x2000>;
612 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
613 interrupt-names = "cmd_irq";
614 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
615 clock-names = "mclk", "apb_pclk";
616 bus-width = <4>;
617 cap-sd-highspeed;
618 cap-mmc-highspeed;
619 max-frequency = <48000000>;
620 vmmc-supply = <&vsdcc_fixed>;
621 vqmmc-supply = <&vsdcc_fixed>;
622 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
623 dma-names = "tx", "rx";
624 pinctrl-names = "default";
625 pinctrl-0 = <&sdc4_gpios>;
626 };
627 };
628
629 tcsr: syscon@1a400000 {
630 compatible = "qcom,tcsr-apq8064", "syscon";
631 reg = <0x1a400000 0x100>;
632 };
633 };
634 };
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