3 #include "skeleton.dtsi"
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
6 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
7 #include <dt-bindings/soc/qcom,gsbi.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 model = "Qualcomm APQ8064";
12 compatible = "qcom,apq8064";
13 interrupt-parent = <&intc>;
20 smem_region: smem@80000000 {
21 reg = <0x80000000 0x200000>;
31 compatible = "qcom,krait";
32 enable-method = "qcom,kpss-acc-v1";
35 next-level-cache = <&L2>;
38 cpu-idle-states = <&CPU_SPC>;
42 compatible = "qcom,krait";
43 enable-method = "qcom,kpss-acc-v1";
46 next-level-cache = <&L2>;
49 cpu-idle-states = <&CPU_SPC>;
53 compatible = "qcom,krait";
54 enable-method = "qcom,kpss-acc-v1";
57 next-level-cache = <&L2>;
60 cpu-idle-states = <&CPU_SPC>;
64 compatible = "qcom,krait";
65 enable-method = "qcom,kpss-acc-v1";
68 next-level-cache = <&L2>;
71 cpu-idle-states = <&CPU_SPC>;
81 compatible = "qcom,idle-state-spc",
83 entry-latency-us = <400>;
84 exit-latency-us = <900>;
85 min-residency-us = <3000>;
92 polling-delay-passive = <250>;
93 polling-delay = <1000>;
95 thermal-sensors = <&gcc 7>;
96 coefficients = <1199 0>;
100 temperature = <75000>;
105 temperature = <110000>;
113 polling-delay-passive = <250>;
114 polling-delay = <1000>;
116 thermal-sensors = <&gcc 8>;
117 coefficients = <1132 0>;
121 temperature = <75000>;
126 temperature = <110000>;
134 polling-delay-passive = <250>;
135 polling-delay = <1000>;
137 thermal-sensors = <&gcc 9>;
138 coefficients = <1199 0>;
142 temperature = <75000>;
147 temperature = <110000>;
155 polling-delay-passive = <250>;
156 polling-delay = <1000>;
158 thermal-sensors = <&gcc 10>;
159 coefficients = <1132 0>;
163 temperature = <75000>;
168 temperature = <110000>;
177 compatible = "qcom,krait-pmu";
178 interrupts = <1 10 0x304>;
183 compatible = "fixed-clock";
185 clock-frequency = <19200000>;
189 compatible = "fixed-clock";
191 clock-frequency = <27000000>;
195 compatible = "fixed-clock";
197 clock-frequency = <32768>;
201 sfpb_mutex: hwmutex {
202 compatible = "qcom,sfpb-mutex";
203 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
208 compatible = "qcom,smem";
209 memory-region = <&smem_region>;
211 hwlocks = <&sfpb_mutex 3>;
215 compatible = "qcom,smd";
218 interrupts = <0 37 IRQ_TYPE_EDGE_RISING>;
220 qcom,ipc = <&l2cc 8 3>;
227 interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;
229 qcom,ipc = <&l2cc 8 15>;
236 interrupts = <0 138 IRQ_TYPE_EDGE_RISING>;
238 qcom,ipc = <&sps_sic_non_secure 0x4080 0>;
245 interrupts = <0 198 IRQ_TYPE_EDGE_RISING>;
247 qcom,ipc = <&l2cc 8 25>;
255 compatible = "qcom,smsm";
257 #address-cells = <1>;
260 qcom,ipc-1 = <&l2cc 8 4>;
261 qcom,ipc-2 = <&l2cc 8 14>;
262 qcom,ipc-3 = <&l2cc 8 23>;
263 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
267 #qcom,smem-state-cells = <1>;
270 modem_smsm: modem@1 {
272 interrupts = <0 38 IRQ_TYPE_EDGE_RISING>;
274 interrupt-controller;
275 #interrupt-cells = <2>;
280 interrupts = <0 89 IRQ_TYPE_EDGE_RISING>;
282 interrupt-controller;
283 #interrupt-cells = <2>;
286 wcnss_smsm: wcnss@3 {
288 interrupts = <0 204 IRQ_TYPE_EDGE_RISING>;
290 interrupt-controller;
291 #interrupt-cells = <2>;
296 interrupts = <0 137 IRQ_TYPE_EDGE_RISING>;
298 interrupt-controller;
299 #interrupt-cells = <2>;
305 compatible = "qcom,scm-apq8064";
310 #address-cells = <1>;
313 compatible = "simple-bus";
315 tlmm_pinmux: pinctrl@800000 {
316 compatible = "qcom,apq8064-pinctrl";
317 reg = <0x800000 0x4000>;
321 interrupt-controller;
322 #interrupt-cells = <2>;
323 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
325 pinctrl-names = "default";
326 pinctrl-0 = <&ps_hold>;
329 sfpb_wrapper_mutex: syscon@1200000 {
330 compatible = "syscon";
331 reg = <0x01200000 0x8000>;
334 intc: interrupt-controller@2000000 {
335 compatible = "qcom,msm-qgic2";
336 interrupt-controller;
337 #interrupt-cells = <3>;
338 reg = <0x02000000 0x1000>,
343 compatible = "qcom,kpss-timer",
344 "qcom,kpss-wdt-apq8064", "qcom,msm-timer";
345 interrupts = <1 1 0x301>,
348 reg = <0x0200a000 0x100>;
349 clock-frequency = <27000000>,
351 cpu-offset = <0x80000>;
354 acc0: clock-controller@2088000 {
355 compatible = "qcom,kpss-acc-v1";
356 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
359 acc1: clock-controller@2098000 {
360 compatible = "qcom,kpss-acc-v1";
361 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
364 acc2: clock-controller@20a8000 {
365 compatible = "qcom,kpss-acc-v1";
366 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
369 acc3: clock-controller@20b8000 {
370 compatible = "qcom,kpss-acc-v1";
371 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
374 saw0: power-controller@2089000 {
375 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
376 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
380 saw1: power-controller@2099000 {
381 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
382 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
386 saw2: power-controller@20a9000 {
387 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
388 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
392 saw3: power-controller@20b9000 {
393 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
394 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
398 sps_sic_non_secure: sps-sic-non-secure@12100000 {
399 compatible = "syscon";
400 reg = <0x12100000 0x10000>;
403 gsbi1: gsbi@12440000 {
405 compatible = "qcom,gsbi-v1.0.0";
407 reg = <0x12440000 0x100>;
408 clocks = <&gcc GSBI1_H_CLK>;
409 clock-names = "iface";
410 #address-cells = <1>;
414 syscon-tcsr = <&tcsr>;
416 gsbi1_serial: serial@12450000 {
417 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
418 reg = <0x12450000 0x100>,
420 interrupts = <0 193 0x0>;
421 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
422 clock-names = "core", "iface";
426 gsbi1_i2c: i2c@12460000 {
427 compatible = "qcom,i2c-qup-v1.1.1";
428 pinctrl-0 = <&i2c1_pins>;
429 pinctrl-1 = <&i2c1_pins_sleep>;
430 pinctrl-names = "default", "sleep";
431 reg = <0x12460000 0x1000>;
432 interrupts = <0 194 IRQ_TYPE_NONE>;
433 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
434 clock-names = "core", "iface";
435 #address-cells = <1>;
441 gsbi2: gsbi@12480000 {
443 compatible = "qcom,gsbi-v1.0.0";
445 reg = <0x12480000 0x100>;
446 clocks = <&gcc GSBI2_H_CLK>;
447 clock-names = "iface";
448 #address-cells = <1>;
452 syscon-tcsr = <&tcsr>;
454 gsbi2_i2c: i2c@124a0000 {
455 compatible = "qcom,i2c-qup-v1.1.1";
456 reg = <0x124a0000 0x1000>;
457 pinctrl-0 = <&i2c2_pins>;
458 pinctrl-1 = <&i2c2_pins_sleep>;
459 pinctrl-names = "default", "sleep";
460 interrupts = <0 196 IRQ_TYPE_NONE>;
461 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
462 clock-names = "core", "iface";
463 #address-cells = <1>;
468 gsbi3: gsbi@16200000 {
470 compatible = "qcom,gsbi-v1.0.0";
472 reg = <0x16200000 0x100>;
473 clocks = <&gcc GSBI3_H_CLK>;
474 clock-names = "iface";
475 #address-cells = <1>;
478 gsbi3_i2c: i2c@16280000 {
479 compatible = "qcom,i2c-qup-v1.1.1";
480 pinctrl-0 = <&i2c3_pins>;
481 pinctrl-1 = <&i2c3_pins_sleep>;
482 pinctrl-names = "default", "sleep";
483 reg = <0x16280000 0x1000>;
484 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
485 clocks = <&gcc GSBI3_QUP_CLK>,
487 clock-names = "core", "iface";
488 #address-cells = <1>;
493 gsbi4: gsbi@16300000 {
495 compatible = "qcom,gsbi-v1.0.0";
497 reg = <0x16300000 0x03>;
498 clocks = <&gcc GSBI4_H_CLK>;
499 clock-names = "iface";
500 #address-cells = <1>;
504 gsbi4_i2c: i2c@16380000 {
505 compatible = "qcom,i2c-qup-v1.1.1";
506 pinctrl-0 = <&i2c4_pins>;
507 pinctrl-1 = <&i2c4_pins_sleep>;
508 pinctrl-names = "default", "sleep";
509 reg = <0x16380000 0x1000>;
510 interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
511 clocks = <&gcc GSBI4_QUP_CLK>,
513 clock-names = "core", "iface";
517 gsbi5: gsbi@1a200000 {
519 compatible = "qcom,gsbi-v1.0.0";
521 reg = <0x1a200000 0x03>;
522 clocks = <&gcc GSBI5_H_CLK>;
523 clock-names = "iface";
524 #address-cells = <1>;
528 gsbi5_serial: serial@1a240000 {
529 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
530 reg = <0x1a240000 0x100>,
532 interrupts = <0 154 0x0>;
533 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
534 clock-names = "core", "iface";
538 gsbi5_spi: spi@1a280000 {
539 compatible = "qcom,spi-qup-v1.1.1";
540 reg = <0x1a280000 0x1000>;
541 interrupts = <0 155 0>;
542 pinctrl-0 = <&spi5_default>;
543 pinctrl-1 = <&spi5_sleep>;
544 pinctrl-names = "default", "sleep";
545 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
546 clock-names = "core", "iface";
548 #address-cells = <1>;
553 gsbi6: gsbi@16500000 {
555 compatible = "qcom,gsbi-v1.0.0";
557 reg = <0x16500000 0x03>;
558 clocks = <&gcc GSBI6_H_CLK>;
559 clock-names = "iface";
560 #address-cells = <1>;
564 gsbi6_serial: serial@16540000 {
565 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
566 reg = <0x16540000 0x100>,
568 interrupts = <0 156 0x0>;
569 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
570 clock-names = "core", "iface";
574 gsbi6_i2c: i2c@16580000 {
575 compatible = "qcom,i2c-qup-v1.1.1";
576 pinctrl-0 = <&i2c6_pins>;
577 pinctrl-1 = <&i2c6_pins_sleep>;
578 pinctrl-names = "default", "sleep";
579 reg = <0x16580000 0x1000>;
580 interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
581 clocks = <&gcc GSBI6_QUP_CLK>,
583 clock-names = "core", "iface";
587 gsbi7: gsbi@16600000 {
589 compatible = "qcom,gsbi-v1.0.0";
591 reg = <0x16600000 0x100>;
592 clocks = <&gcc GSBI7_H_CLK>;
593 clock-names = "iface";
594 #address-cells = <1>;
597 syscon-tcsr = <&tcsr>;
599 gsbi7_serial: serial@16640000 {
600 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
601 reg = <0x16640000 0x1000>,
603 interrupts = <0 158 0x0>;
604 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
605 clock-names = "core", "iface";
609 gsbi7_i2c: i2c@16680000 {
610 compatible = "qcom,i2c-qup-v1.1.1";
611 pinctrl-0 = <&i2c7_pins>;
612 pinctrl-1 = <&i2c7_pins_sleep>;
613 pinctrl-names = "default", "sleep";
614 reg = <0x16680000 0x1000>;
615 interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
616 clocks = <&gcc GSBI7_QUP_CLK>,
618 clock-names = "core", "iface";
624 compatible = "qcom,prng";
625 reg = <0x1a500000 0x200>;
626 clocks = <&gcc PRNG_CLK>;
627 clock-names = "core";
631 compatible = "qcom,ssbi";
632 reg = <0x00500000 0x1000>;
633 qcom,controller-type = "pmic-arbiter";
636 compatible = "qcom,pm8921";
637 interrupt-parent = <&tlmm_pinmux>;
639 #interrupt-cells = <2>;
640 interrupt-controller;
641 #address-cells = <1>;
644 pm8921_gpio: gpio@150 {
646 compatible = "qcom,pm8921-gpio",
649 interrupts = <192 IRQ_TYPE_NONE>,
698 pm8921_mpps: mpps@50 {
699 compatible = "qcom,pm8921-mpp",
720 compatible = "qcom,pm8921-rtc";
721 interrupt-parent = <&pmicintc>;
728 compatible = "qcom,pm8921-pwrkey";
730 interrupt-parent = <&pmicintc>;
731 interrupts = <50 1>, <51 1>;
738 qfprom: qfprom@700000 {
739 compatible = "qcom,qfprom";
740 reg = <0x00700000 0x1000>;
741 #address-cells = <1>;
747 tsens_backup: backup_calib {
752 gcc: clock-controller@900000 {
753 compatible = "qcom,gcc-apq8064";
754 reg = <0x00900000 0x4000>;
755 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
756 nvmem-cell-names = "calib", "calib_backup";
759 #thermal-sensor-cells = <1>;
762 lcc: clock-controller@28000000 {
763 compatible = "qcom,lcc-apq8064";
764 reg = <0x28000000 0x1000>;
769 mmcc: clock-controller@4000000 {
770 compatible = "qcom,mmcc-apq8064";
771 reg = <0x4000000 0x1000>;
776 l2cc: clock-controller@2011000 {
777 compatible = "syscon";
778 reg = <0x2011000 0x1000>;
782 compatible = "qcom,rpm-apq8064";
783 reg = <0x108000 0x1000>;
784 qcom,ipc = <&l2cc 0x8 2>;
786 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
787 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
788 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
789 interrupt-names = "ack", "err", "wakeup";
791 rpmcc: clock-controller {
792 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
797 compatible = "qcom,rpm-pm8921-regulators";
833 pm8921_lvs1: lvs1 {};
834 pm8921_lvs2: lvs2 {};
835 pm8921_lvs3: lvs3 {};
836 pm8921_lvs4: lvs4 {};
837 pm8921_lvs5: lvs5 {};
838 pm8921_lvs6: lvs6 {};
839 pm8921_lvs7: lvs7 {};
841 pm8921_usb_switch: usb-switch {};
843 pm8921_hdmi_switch: hdmi-switch {
851 usb1_phy: phy@12500000 {
852 compatible = "qcom,usb-otg-ci";
853 reg = <0x12500000 0x400>;
854 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
857 clocks = <&gcc USB_HS1_XCVR_CLK>,
858 <&gcc USB_HS1_H_CLK>;
859 clock-names = "core", "iface";
861 resets = <&gcc USB_HS1_RESET>;
862 reset-names = "link";
865 usb3_phy: phy@12520000 {
866 compatible = "qcom,usb-otg-ci";
867 reg = <0x12520000 0x400>;
868 interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
872 clocks = <&gcc USB_HS3_XCVR_CLK>,
873 <&gcc USB_HS3_H_CLK>;
874 clock-names = "core", "iface";
876 resets = <&gcc USB_HS3_RESET>;
877 reset-names = "link";
880 usb4_phy: phy@12530000 {
881 compatible = "qcom,usb-otg-ci";
882 reg = <0x12530000 0x400>;
883 interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
887 clocks = <&gcc USB_HS4_XCVR_CLK>,
888 <&gcc USB_HS4_H_CLK>;
889 clock-names = "core", "iface";
891 resets = <&gcc USB_HS4_RESET>;
892 reset-names = "link";
895 gadget1: gadget@12500000 {
896 compatible = "qcom,ci-hdrc";
897 reg = <0x12500000 0x400>;
899 dr_mode = "peripheral";
900 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
901 usb-phy = <&usb1_phy>;
905 compatible = "qcom,ehci-host";
906 reg = <0x12500000 0x400>;
907 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
909 usb-phy = <&usb1_phy>;
913 compatible = "qcom,ehci-host";
914 reg = <0x12520000 0x400>;
915 interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
917 usb-phy = <&usb3_phy>;
921 compatible = "qcom,ehci-host";
922 reg = <0x12530000 0x400>;
923 interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
925 usb-phy = <&usb4_phy>;
928 sata_phy0: phy@1b400000 {
929 compatible = "qcom,apq8064-sata-phy";
931 reg = <0x1b400000 0x200>;
932 reg-names = "phy_mem";
933 clocks = <&gcc SATA_PHY_CFG_CLK>;
938 sata0: sata@29000000 {
939 compatible = "qcom,apq8064-ahci", "generic-ahci";
941 reg = <0x29000000 0x180>;
942 interrupts = <GIC_SPI 209 IRQ_TYPE_NONE>;
944 clocks = <&gcc SFAB_SATA_S_H_CLK>,
947 <&gcc SATA_RXOOB_CLK>,
948 <&gcc SATA_PMALIVE_CLK>;
949 clock-names = "slave_iface",
955 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
956 <&gcc SATA_PMALIVE_CLK>;
957 assigned-clock-rates = <100000000>, <100000000>;
960 phy-names = "sata-phy";
961 ports-implemented = <0x1>;
964 /* Temporary fixed regulator */
965 sdcc1bam:dma@12402000{
966 compatible = "qcom,bam-v1.3.0";
967 reg = <0x12402000 0x8000>;
968 interrupts = <0 98 0>;
969 clocks = <&gcc SDC1_H_CLK>;
970 clock-names = "bam_clk";
975 sdcc3bam:dma@12182000{
976 compatible = "qcom,bam-v1.3.0";
977 reg = <0x12182000 0x8000>;
978 interrupts = <0 96 0>;
979 clocks = <&gcc SDC3_H_CLK>;
980 clock-names = "bam_clk";
985 sdcc4bam:dma@121c2000{
986 compatible = "qcom,bam-v1.3.0";
987 reg = <0x121c2000 0x8000>;
988 interrupts = <0 95 0>;
989 clocks = <&gcc SDC4_H_CLK>;
990 clock-names = "bam_clk";
996 compatible = "simple-bus";
997 #address-cells = <1>;
1000 sdcc1: sdcc@12400000 {
1001 status = "disabled";
1002 compatible = "arm,pl18x", "arm,primecell";
1003 pinctrl-names = "default";
1004 pinctrl-0 = <&sdcc1_pins>;
1005 arm,primecell-periphid = <0x00051180>;
1006 reg = <0x12400000 0x2000>;
1007 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1008 interrupt-names = "cmd_irq";
1009 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1010 clock-names = "mclk", "apb_pclk";
1012 max-frequency = <96000000>;
1016 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1017 dma-names = "tx", "rx";
1020 sdcc3: sdcc@12180000 {
1021 compatible = "arm,pl18x", "arm,primecell";
1022 arm,primecell-periphid = <0x00051180>;
1023 status = "disabled";
1024 reg = <0x12180000 0x2000>;
1025 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1026 interrupt-names = "cmd_irq";
1027 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1028 clock-names = "mclk", "apb_pclk";
1032 max-frequency = <192000000>;
1034 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1035 dma-names = "tx", "rx";
1038 sdcc4: sdcc@121c0000 {
1039 compatible = "arm,pl18x", "arm,primecell";
1040 arm,primecell-periphid = <0x00051180>;
1041 status = "disabled";
1042 reg = <0x121c0000 0x2000>;
1043 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1044 interrupt-names = "cmd_irq";
1045 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
1046 clock-names = "mclk", "apb_pclk";
1050 max-frequency = <48000000>;
1051 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
1052 dma-names = "tx", "rx";
1053 pinctrl-names = "default";
1054 pinctrl-0 = <&sdc4_gpios>;
1058 tcsr: syscon@1a400000 {
1059 compatible = "qcom,tcsr-apq8064", "syscon";
1060 reg = <0x1a400000 0x100>;
1063 pcie: pci@1b500000 {
1064 compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
1065 reg = <0x1b500000 0x1000
1068 0x0ff00000 0x100000>;
1069 reg-names = "dbi", "elbi", "parf", "config";
1070 device_type = "pci";
1071 linux,pci-domain = <0>;
1072 bus-range = <0x00 0xff>;
1074 #address-cells = <3>;
1076 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
1077 0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
1078 interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
1079 interrupt-names = "msi";
1080 #interrupt-cells = <1>;
1081 interrupt-map-mask = <0 0 0 0x7>;
1082 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1083 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1084 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1085 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1086 clocks = <&gcc PCIE_A_CLK>,
1088 <&gcc PCIE_PHY_REF_CLK>;
1089 clock-names = "core", "iface", "phy";
1090 resets = <&gcc PCIE_ACLK_RESET>,
1091 <&gcc PCIE_HCLK_RESET>,
1092 <&gcc PCIE_POR_RESET>,
1093 <&gcc PCIE_PCI_RESET>,
1094 <&gcc PCIE_PHY_RESET>;
1095 reset-names = "axi", "ahb", "por", "pci", "phy";
1096 status = "disabled";
1100 #include "qcom-apq8064-pins.dtsi"