3 #include "skeleton.dtsi"
5 #include <dt-bindings/clock/qcom,gcc-apq8084.h>
6 #include <dt-bindings/gpio/gpio.h>
9 model = "Qualcomm APQ 8084";
10 compatible = "qcom,apq8084";
11 interrupt-parent = <&intc>;
18 smem_mem: smem_region@fa00000 {
19 reg = <0xfa00000 0x200000>;
30 compatible = "qcom,krait";
32 enable-method = "qcom,kpss-acc-v2";
33 next-level-cache = <&L2>;
36 cpu-idle-states = <&CPU_SPC>;
41 compatible = "qcom,krait";
43 enable-method = "qcom,kpss-acc-v2";
44 next-level-cache = <&L2>;
47 cpu-idle-states = <&CPU_SPC>;
52 compatible = "qcom,krait";
54 enable-method = "qcom,kpss-acc-v2";
55 next-level-cache = <&L2>;
58 cpu-idle-states = <&CPU_SPC>;
63 compatible = "qcom,krait";
65 enable-method = "qcom,kpss-acc-v2";
66 next-level-cache = <&L2>;
69 cpu-idle-states = <&CPU_SPC>;
73 compatible = "qcom,arch-cache";
80 compatible = "qcom,idle-state-spc",
82 entry-latency-us = <150>;
83 exit-latency-us = <200>;
84 min-residency-us = <2000>;
91 compatible = "qcom,scm";
92 clocks = <&gcc GCC_CE1_CLK> , <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
93 clock-names = "core", "bus", "iface";
98 compatible = "qcom,krait-pmu";
99 interrupts = <1 7 0xf04>;
104 compatible = "fixed-clock";
106 clock-frequency = <19200000>;
110 compatible = "fixed-clock";
112 clock-frequency = <32768>;
117 compatible = "arm,armv7-timer";
118 interrupts = <1 2 0xf08>,
122 clock-frequency = <19200000>;
126 compatible = "qcom,smem";
128 qcom,rpm-msg-ram = <&rpm_msg_ram>;
129 memory-region = <&smem_mem>;
131 hwlocks = <&tcsr_mutex 3>;
135 #address-cells = <1>;
138 compatible = "simple-bus";
140 intc: interrupt-controller@f9000000 {
141 compatible = "qcom,msm-qgic2";
142 interrupt-controller;
143 #interrupt-cells = <3>;
144 reg = <0xf9000000 0x1000>,
148 apcs: syscon@f9011000 {
149 compatible = "syscon";
150 reg = <0xf9011000 0x1000>;
154 #address-cells = <1>;
157 compatible = "arm,armv7-timer-mem";
158 reg = <0xf9020000 0x1000>;
159 clock-frequency = <19200000>;
163 interrupts = <0 8 0x4>,
165 reg = <0xf9021000 0x1000>,
171 interrupts = <0 9 0x4>;
172 reg = <0xf9023000 0x1000>;
178 interrupts = <0 10 0x4>;
179 reg = <0xf9024000 0x1000>;
185 interrupts = <0 11 0x4>;
186 reg = <0xf9025000 0x1000>;
192 interrupts = <0 12 0x4>;
193 reg = <0xf9026000 0x1000>;
199 interrupts = <0 13 0x4>;
200 reg = <0xf9027000 0x1000>;
206 interrupts = <0 14 0x4>;
207 reg = <0xf9028000 0x1000>;
212 saw0: power-controller@f9089000 {
213 compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
214 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
217 saw1: power-controller@f9099000 {
218 compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
219 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
222 saw2: power-controller@f90a9000 {
223 compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
224 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
227 saw3: power-controller@f90b9000 {
228 compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
229 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
232 saw_l2: power-controller@f9012000 {
233 compatible = "qcom,saw2";
234 reg = <0xf9012000 0x1000>;
238 acc0: clock-controller@f9088000 {
239 compatible = "qcom,kpss-acc-v2";
240 reg = <0xf9088000 0x1000>,
244 acc1: clock-controller@f9098000 {
245 compatible = "qcom,kpss-acc-v2";
246 reg = <0xf9098000 0x1000>,
250 acc2: clock-controller@f90a8000 {
251 compatible = "qcom,kpss-acc-v2";
252 reg = <0xf90a8000 0x1000>,
256 acc3: clock-controller@f90b8000 {
257 compatible = "qcom,kpss-acc-v2";
258 reg = <0xf90b8000 0x1000>,
263 compatible = "qcom,pshold";
264 reg = <0xfc4ab000 0x4>;
267 gcc: clock-controller@fc400000 {
268 compatible = "qcom,gcc-apq8084";
271 #power-domain-cells = <1>;
272 reg = <0xfc400000 0x4000>;
275 tcsr_mutex_regs: syscon@fd484000 {
276 compatible = "syscon";
277 reg = <0xfd484000 0x2000>;
281 compatible = "qcom,tcsr-mutex";
282 syscon = <&tcsr_mutex_regs 0 0x80>;
286 rpm_msg_ram: memory@fc428000 {
287 compatible = "qcom,rpm-msg-ram";
288 reg = <0xfc428000 0x4000>;
291 tlmm: pinctrl@fd510000 {
292 compatible = "qcom,apq8084-pinctrl";
293 reg = <0xfd510000 0x4000>;
296 interrupt-controller;
297 #interrupt-cells = <2>;
298 interrupts = <0 208 0>;
301 blsp2_uart2: serial@f995e000 {
302 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
303 reg = <0xf995e000 0x1000>;
304 interrupts = <0 114 0x0>;
305 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
306 clock-names = "core", "iface";
311 compatible = "qcom,sdhci-msm-v4";
312 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
313 reg-names = "hc_mem", "core_mem";
314 interrupts = <0 123 0>, <0 138 0>;
315 interrupt-names = "hc_irq", "pwr_irq";
316 clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
317 clock-names = "core", "iface";
322 compatible = "qcom,sdhci-msm-v4";
323 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
324 reg-names = "hc_mem", "core_mem";
325 interrupts = <0 125 0>, <0 221 0>;
326 interrupt-names = "hc_irq", "pwr_irq";
327 clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
328 clock-names = "core", "iface";
332 spmi_bus: spmi@fc4cf000 {
333 compatible = "qcom,spmi-pmic-arb";
334 reg-names = "core", "intr", "cnfg";
335 reg = <0xfc4cf000 0x1000>,
338 interrupt-names = "periph_irq";
339 interrupts = <0 190 0>;
342 #address-cells = <2>;
344 interrupt-controller;
345 #interrupt-cells = <4>;
350 compatible = "qcom,smd";
353 interrupts = <0 168 1>;
354 qcom,ipc = <&apcs 8 0>;
355 qcom,smd-edge = <15>;
358 compatible = "qcom,rpm-apq8084";
359 qcom,smd-channels = "rpm_requests";
362 compatible = "qcom,rpm-pma8084-regulators";
405 pma8084_lvs1: lvs1 {};
406 pma8084_lvs2: lvs2 {};
407 pma8084_lvs3: lvs3 {};
408 pma8084_lvs4: lvs4 {};
410 pma8084_5vs1: 5vs1 {};