2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
16 #include "skeleton.dtsi"
17 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
20 model = "Qualcomm Technologies, Inc. IPQ4019";
21 compatible = "qcom,ipq4019";
22 interrupt-parent = <&intc>;
29 compatible = "arm,cortex-a7";
30 enable-method = "qcom,kpss-acc-v1";
34 clocks = <&gcc GCC_APPS_CLK_SRC>;
35 clock-frequency = <0>;
40 compatible = "arm,cortex-a7";
41 enable-method = "qcom,kpss-acc-v1";
45 clocks = <&gcc GCC_APPS_CLK_SRC>;
46 clock-frequency = <0>;
51 compatible = "arm,cortex-a7";
52 enable-method = "qcom,kpss-acc-v1";
56 clocks = <&gcc GCC_APPS_CLK_SRC>;
57 clock-frequency = <0>;
62 compatible = "arm,cortex-a7";
63 enable-method = "qcom,kpss-acc-v1";
67 clocks = <&gcc GCC_APPS_CLK_SRC>;
68 clock-frequency = <0>;
73 sleep_clk: sleep_clk {
74 compatible = "fixed-clock";
75 clock-frequency = <32768>;
84 compatible = "simple-bus";
86 intc: interrupt-controller@b000000 {
87 compatible = "qcom,msm-qgic2";
89 #interrupt-cells = <3>;
90 reg = <0x0b000000 0x1000>,
94 gcc: clock-controller@1800000 {
95 compatible = "qcom,gcc-ipq4019";
98 reg = <0x1800000 0x60000>;
101 tlmm: pinctrl@0x01000000 {
102 compatible = "qcom,ipq4019-pinctrl";
103 reg = <0x01000000 0x300000>;
106 interrupt-controller;
107 #interrupt-cells = <2>;
108 interrupts = <0 208 0>;
111 acc0: clock-controller@b088000 {
112 compatible = "qcom,kpss-acc-v1";
113 reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
116 acc1: clock-controller@b098000 {
117 compatible = "qcom,kpss-acc-v1";
118 reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
121 acc2: clock-controller@b0a8000 {
122 compatible = "qcom,kpss-acc-v1";
123 reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
126 acc3: clock-controller@b0b8000 {
127 compatible = "qcom,kpss-acc-v1";
128 reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
131 saw0: regulator@b089000 {
132 compatible = "qcom,saw2";
133 reg = <0x02089000 0x1000>, <0x0b009000 0x1000>;
137 saw1: regulator@b099000 {
138 compatible = "qcom,saw2";
139 reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
143 saw2: regulator@b0a9000 {
144 compatible = "qcom,saw2";
145 reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
149 saw3: regulator@b0b9000 {
150 compatible = "qcom,saw2";
151 reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
156 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
157 reg = <0x78af000 0x200>;
158 interrupts = <0 107 0>;
160 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
161 <&gcc GCC_BLSP1_AHB_CLK>;
162 clock-names = "core", "iface";
166 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
167 reg = <0x78b0000 0x200>;
168 interrupts = <0 108 0>;
170 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
171 <&gcc GCC_BLSP1_AHB_CLK>;
172 clock-names = "core", "iface";
176 compatible = "qcom,kpss-standalone";
177 reg = <0xb017000 0x40>;
178 clocks = <&sleep_clk>;