2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
16 #include "skeleton.dtsi"
17 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
18 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 #include <dt-bindings/interrupt-controller/irq.h>
22 model = "Qualcomm Technologies, Inc. IPQ4019";
23 compatible = "qcom,ipq4019";
24 interrupt-parent = <&intc>;
36 compatible = "arm,cortex-a7";
37 enable-method = "qcom,kpss-acc-v1";
41 clocks = <&gcc GCC_APPS_CLK_SRC>;
42 clock-frequency = <0>;
50 clock-latency = <256000>;
55 compatible = "arm,cortex-a7";
56 enable-method = "qcom,kpss-acc-v1";
60 clocks = <&gcc GCC_APPS_CLK_SRC>;
61 clock-frequency = <0>;
66 compatible = "arm,cortex-a7";
67 enable-method = "qcom,kpss-acc-v1";
71 clocks = <&gcc GCC_APPS_CLK_SRC>;
72 clock-frequency = <0>;
77 compatible = "arm,cortex-a7";
78 enable-method = "qcom,kpss-acc-v1";
82 clocks = <&gcc GCC_APPS_CLK_SRC>;
83 clock-frequency = <0>;
88 sleep_clk: sleep_clk {
89 compatible = "fixed-clock";
90 clock-frequency = <32768>;
99 compatible = "simple-bus";
101 intc: interrupt-controller@b000000 {
102 compatible = "qcom,msm-qgic2";
103 interrupt-controller;
104 #interrupt-cells = <3>;
105 reg = <0x0b000000 0x1000>,
109 gcc: clock-controller@1800000 {
110 compatible = "qcom,gcc-ipq4019";
113 reg = <0x1800000 0x60000>;
116 tlmm: pinctrl@0x01000000 {
117 compatible = "qcom,ipq4019-pinctrl";
118 reg = <0x01000000 0x300000>;
121 interrupt-controller;
122 #interrupt-cells = <2>;
123 interrupts = <0 208 0>;
126 blsp_dma: dma@7884000 {
127 compatible = "qcom,bam-v1.7.0";
128 reg = <0x07884000 0x23000>;
129 interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
130 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
131 clock-names = "bam_clk";
138 compatible = "qcom,spi-qup-v2.2.1";
139 reg = <0x78b5000 0x600>;
140 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
141 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
142 <&gcc GCC_BLSP1_AHB_CLK>;
143 clock-names = "core", "iface";
144 #address-cells = <1>;
150 compatible = "qcom,i2c-qup-v2.2.1";
151 reg = <0x78b7000 0x6000>;
152 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
153 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
154 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
155 clock-names = "iface", "core";
156 #address-cells = <1>;
162 cryptobam: dma@8e04000 {
163 compatible = "qcom,bam-v1.7.0";
164 reg = <0x08e04000 0x20000>;
165 interrupts = <GIC_SPI 207 0>;
166 clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
167 clock-names = "bam_clk";
170 qcom,controlled-remotely;
175 compatible = "qcom,crypto-v5.1";
176 reg = <0x08e3a000 0x6000>;
177 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
178 <&gcc GCC_CRYPTO_AXI_CLK>,
179 <&gcc GCC_CRYPTO_CLK>;
180 clock-names = "iface", "bus", "core";
181 dmas = <&cryptobam 2>, <&cryptobam 3>;
182 dma-names = "rx", "tx";
186 acc0: clock-controller@b088000 {
187 compatible = "qcom,kpss-acc-v1";
188 reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
191 acc1: clock-controller@b098000 {
192 compatible = "qcom,kpss-acc-v1";
193 reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
196 acc2: clock-controller@b0a8000 {
197 compatible = "qcom,kpss-acc-v1";
198 reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
201 acc3: clock-controller@b0b8000 {
202 compatible = "qcom,kpss-acc-v1";
203 reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
206 saw0: regulator@b089000 {
207 compatible = "qcom,saw2";
208 reg = <0x02089000 0x1000>, <0x0b009000 0x1000>;
212 saw1: regulator@b099000 {
213 compatible = "qcom,saw2";
214 reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
218 saw2: regulator@b0a9000 {
219 compatible = "qcom,saw2";
220 reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
224 saw3: regulator@b0b9000 {
225 compatible = "qcom,saw2";
226 reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
231 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
232 reg = <0x78af000 0x200>;
233 interrupts = <0 107 0>;
235 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
236 <&gcc GCC_BLSP1_AHB_CLK>;
237 clock-names = "core", "iface";
238 dmas = <&blsp_dma 1>, <&blsp_dma 0>;
239 dma-names = "rx", "tx";
243 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
244 reg = <0x78b0000 0x200>;
245 interrupts = <0 108 0>;
247 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
248 <&gcc GCC_BLSP1_AHB_CLK>;
249 clock-names = "core", "iface";
250 dmas = <&blsp_dma 3>, <&blsp_dma 2>;
251 dma-names = "rx", "tx";
255 compatible = "qcom,kpss-standalone";
256 reg = <0xb017000 0x40>;
257 clocks = <&sleep_clk>;
263 compatible = "qcom,pshold";
264 reg = <0x4ab000 0x4>;