arch/arm/boot/dts/r8a73a4.dtsi

   1 /*
   2  * Device Tree Source for the r8a73a4 SoC
   3  *
   4  * Copyright (C) 2013 Renesas Solutions Corp.
   5  * Copyright (C) 2013 Magnus Damm
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 / {
  13         compatible = "renesas,r8a73a4";
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21
  22                 cpu0: cpu@0 {
  23                         device_type = "cpu";
  24                         compatible = "arm,cortex-a15";
  25                         reg = <0>;
  26                         clock-frequency = <1500000000>;
  27                 };
  28         };
  29
  30         gic: interrupt-controller@f1001000 {
  31                 compatible = "arm,cortex-a15-gic";
  32                 #interrupt-cells = <3>;
  33                 #address-cells = <0>;
  34                 interrupt-controller;
  35                 reg = <0 0xf1001000 0 0x1000>,
  36                         <0 0xf1002000 0 0x1000>,
  37                         <0 0xf1004000 0 0x2000>,
  38                         <0 0xf1006000 0 0x2000>;
  39                 interrupts = <1 9 0xf04>;
  40         };
  41
  42         timer {
  43                 compatible = "arm,armv7-timer";
  44                 interrupts = <1 13 0xf08>,
  45                                 <1 14 0xf08>,
  46                                 <1 11 0xf08>,
  47                                 <1 10 0xf08>;
  48         };
  49
  50         irqc0: interrupt-controller@e61c0000 {
  51                 compatible = "renesas,irqc";
  52                 #interrupt-cells = <2>;
  53                 interrupt-controller;
  54                 reg = <0 0xe61c0000 0 0x200>;
  55                 interrupt-parent = <&gic>;
  56                 interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>,
  57                                 <0 4 4>, <0 5 4>, <0 6 4>, <0 7 4>,
  58                                 <0 8 4>, <0 9 4>, <0 10 4>, <0 11 4>,
  59                                 <0 12 4>, <0 13 4>, <0 14 4>, <0 15 4>,
  60                                 <0 16 4>, <0 17 4>, <0 18 4>, <0 19 4>,
  61                                 <0 20 4>, <0 21 4>, <0 22 4>, <0 23 4>,
  62                                 <0 24 4>, <0 25 4>, <0 26 4>, <0 27 4>,
  63                                 <0 28 4>, <0 29 4>, <0 30 4>, <0 31 4>;
  64         };
  65
  66         irqc1: interrupt-controller@e61c0200 {
  67                 compatible = "renesas,irqc";
  68                 #interrupt-cells = <2>;
  69                 interrupt-controller;
  70                 reg = <0 0xe61c0200 0 0x200>;
  71                 interrupt-parent = <&gic>;
  72                 interrupts = <0 32 4>, <0 33 4>, <0 34 4>, <0 35 4>,
  73                                 <0 36 4>, <0 37 4>, <0 38 4>, <0 39 4>,
  74                                 <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>,
  75                                 <0 44 4>, <0 45 4>, <0 46 4>, <0 47 4>,
  76                                 <0 48 4>, <0 49 4>, <0 50 4>, <0 51 4>,
  77                                 <0 52 4>, <0 53 4>, <0 54 4>, <0 55 4>,
  78                                 <0 56 4>, <0 57 4>;
  79         };
  80
  81         thermal@e61f0000 {
  82                 compatible = "renesas,rcar-thermal";
  83                 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
  84                          <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>;
  85                 interrupt-parent = <&gic>;
  86                 interrupts = <0 69 4>;
  87         };
  88 };