arch/arm/boot/dts/r8a7740.dtsi

   1 /*
   2  * Device Tree Source for the r8a7740 SoC
   3  *
   4  * Copyright (C) 2012 Renesas Solutions Corp.
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 /include/ "skeleton.dtsi"
  12
  13 #include <dt-bindings/clock/r8a7740-clock.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15
  16 / {
  17         compatible = "renesas,r8a7740";
  18         interrupt-parent = <&gic>;
  19
  20         cpus {
  21                 #address-cells = <1>;
  22                 #size-cells = <0>;
  23                 cpu@0 {
  24                         compatible = "arm,cortex-a9";
  25                         device_type = "cpu";
  26                         reg = <0x0>;
  27                         clock-frequency = <800000000>;
  28                         power-domains = <&pd_a3sm>;
  29                         next-level-cache = <&L2>;
  30                 };
  31         };
  32
  33         gic: interrupt-controller@c2800000 {
  34                 compatible = "arm,pl390";
  35                 #interrupt-cells = <3>;
  36                 interrupt-controller;
  37                 reg = <0xc2800000 0x1000>,
  38                       <0xc2000000 0x1000>;
  39         };
  40
  41         L2: cache-controller {
  42                 compatible = "arm,pl310-cache";
  43                 reg = <0xf0100000 0x1000>;
  44                 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
  45                 power-domains = <&pd_a3sm>;
  46                 arm,data-latency = <3 3 3>;
  47                 arm,tag-latency = <2 2 2>;
  48                 arm,shared-override;
  49                 cache-unified;
  50                 cache-level = <2>;
  51         };
  52
  53         dbsc3: memory-controller@fe400000 {
  54                 compatible = "renesas,dbsc3-r8a7740";
  55                 reg = <0xfe400000 0x400>;
  56                 power-domains = <&pd_a4s>;
  57         };
  58
  59         pmu {
  60                 compatible = "arm,cortex-a9-pmu";
  61                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
  62         };
  63
  64         ptm {
  65                 compatible = "arm,coresight-etm3x";
  66                 power-domains = <&pd_d4>;
  67         };
  68
  69         cmt1: timer@e6138000 {
  70                 compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48";
  71                 reg = <0xe6138000 0x170>;
  72                 interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
  73                 clocks = <&mstp3_clks R8A7740_CLK_CMT1>;
  74                 clock-names = "fck";
  75                 power-domains = <&pd_c5>;
  76
  77                 renesas,channels-mask = <0x3f>;
  78
  79                 status = "disabled";
  80         };
  81
  82         /* irqpin0: IRQ0 - IRQ7 */
  83         irqpin0: interrupt-controller@e6900000 {
  84                 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
  85                 #interrupt-cells = <2>;
  86                 interrupt-controller;
  87                 reg = <0xe6900000 4>,
  88                         <0xe6900010 4>,
  89                         <0xe6900020 1>,
  90                         <0xe6900040 1>,
  91                         <0xe6900060 1>;
  92                 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
  93                               0 149 IRQ_TYPE_LEVEL_HIGH
  94                               0 149 IRQ_TYPE_LEVEL_HIGH
  95                               0 149 IRQ_TYPE_LEVEL_HIGH
  96                               0 149 IRQ_TYPE_LEVEL_HIGH
  97                               0 149 IRQ_TYPE_LEVEL_HIGH
  98                               0 149 IRQ_TYPE_LEVEL_HIGH
  99                               0 149 IRQ_TYPE_LEVEL_HIGH>;
 100                 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
 101                 power-domains = <&pd_a4s>;
 102         };
 103
 104         /* irqpin1: IRQ8 - IRQ15 */
 105         irqpin1: interrupt-controller@e6900004 {
 106                 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
 107                 #interrupt-cells = <2>;
 108                 interrupt-controller;
 109                 reg = <0xe6900004 4>,
 110                         <0xe6900014 4>,
 111                         <0xe6900024 1>,
 112                         <0xe6900044 1>,
 113                         <0xe6900064 1>;
 114                 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
 115                               0 149 IRQ_TYPE_LEVEL_HIGH
 116                               0 149 IRQ_TYPE_LEVEL_HIGH
 117                               0 149 IRQ_TYPE_LEVEL_HIGH
 118                               0 149 IRQ_TYPE_LEVEL_HIGH
 119                               0 149 IRQ_TYPE_LEVEL_HIGH
 120                               0 149 IRQ_TYPE_LEVEL_HIGH
 121                               0 149 IRQ_TYPE_LEVEL_HIGH>;
 122                 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
 123                 power-domains = <&pd_a4s>;
 124         };
 125
 126         /* irqpin2: IRQ16 - IRQ23 */
 127         irqpin2: interrupt-controller@e6900008 {
 128                 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
 129                 #interrupt-cells = <2>;
 130                 interrupt-controller;
 131                 reg = <0xe6900008 4>,
 132                         <0xe6900018 4>,
 133                         <0xe6900028 1>,
 134                         <0xe6900048 1>,
 135                         <0xe6900068 1>;
 136                 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
 137                               0 149 IRQ_TYPE_LEVEL_HIGH
 138                               0 149 IRQ_TYPE_LEVEL_HIGH
 139                               0 149 IRQ_TYPE_LEVEL_HIGH
 140                               0 149 IRQ_TYPE_LEVEL_HIGH
 141                               0 149 IRQ_TYPE_LEVEL_HIGH
 142                               0 149 IRQ_TYPE_LEVEL_HIGH
 143                               0 149 IRQ_TYPE_LEVEL_HIGH>;
 144                 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
 145                 power-domains = <&pd_a4s>;
 146         };
 147
 148         /* irqpin3: IRQ24 - IRQ31 */
 149         irqpin3: interrupt-controller@e690000c {
 150                 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
 151                 #interrupt-cells = <2>;
 152                 interrupt-controller;
 153                 reg = <0xe690000c 4>,
 154                         <0xe690001c 4>,
 155                         <0xe690002c 1>,
 156                         <0xe690004c 1>,
 157                         <0xe690006c 1>;
 158                 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
 159                               0 149 IRQ_TYPE_LEVEL_HIGH
 160                               0 149 IRQ_TYPE_LEVEL_HIGH
 161                               0 149 IRQ_TYPE_LEVEL_HIGH
 162                               0 149 IRQ_TYPE_LEVEL_HIGH
 163                               0 149 IRQ_TYPE_LEVEL_HIGH
 164                               0 149 IRQ_TYPE_LEVEL_HIGH
 165                               0 149 IRQ_TYPE_LEVEL_HIGH>;
 166                 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
 167                 power-domains = <&pd_a4s>;
 168         };
 169
 170         ether: ethernet@e9a00000 {
 171                 compatible = "renesas,gether-r8a7740";
 172                 reg = <0xe9a00000 0x800>,
 173                       <0xe9a01800 0x800>;
 174                 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
 175                 clocks = <&mstp3_clks R8A7740_CLK_GETHER>;
 176                 power-domains = <&pd_a4s>;
 177                 phy-mode = "mii";
 178                 #address-cells = <1>;
 179                 #size-cells = <0>;
 180                 status = "disabled";
 181         };
 182
 183         i2c0: i2c@fff20000 {
 184                 #address-cells = <1>;
 185                 #size-cells = <0>;
 186                 compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
 187                 reg = <0xfff20000 0x425>;
 188                 interrupts = <0 201 IRQ_TYPE_LEVEL_HIGH
 189                               0 202 IRQ_TYPE_LEVEL_HIGH
 190                               0 203 IRQ_TYPE_LEVEL_HIGH
 191                               0 204 IRQ_TYPE_LEVEL_HIGH>;
 192                 clocks = <&mstp1_clks R8A7740_CLK_IIC0>;
 193                 power-domains = <&pd_a4r>;
 194                 status = "disabled";
 195         };
 196
 197         i2c1: i2c@e6c20000 {
 198                 #address-cells = <1>;
 199                 #size-cells = <0>;
 200                 compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
 201                 reg = <0xe6c20000 0x425>;
 202                 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH
 203                               0 71 IRQ_TYPE_LEVEL_HIGH
 204                               0 72 IRQ_TYPE_LEVEL_HIGH
 205                               0 73 IRQ_TYPE_LEVEL_HIGH>;
 206                 clocks = <&mstp3_clks R8A7740_CLK_IIC1>;
 207                 power-domains = <&pd_a3sp>;
 208                 status = "disabled";
 209         };
 210
 211         scifa0: serial@e6c40000 {
 212                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 213                 reg = <0xe6c40000 0x100>;
 214                 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
 215                 clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;
 216                 clock-names = "sci_ick";
 217                 power-domains = <&pd_a3sp>;
 218                 status = "disabled";
 219         };
 220
 221         scifa1: serial@e6c50000 {
 222                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 223                 reg = <0xe6c50000 0x100>;
 224                 interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
 225                 clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>;
 226                 clock-names = "sci_ick";
 227                 power-domains = <&pd_a3sp>;
 228                 status = "disabled";
 229         };
 230
 231         scifa2: serial@e6c60000 {
 232                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 233                 reg = <0xe6c60000 0x100>;
 234                 interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
 235                 clocks = <&mstp2_clks R8A7740_CLK_SCIFA2>;
 236                 clock-names = "sci_ick";
 237                 power-domains = <&pd_a3sp>;
 238                 status = "disabled";
 239         };
 240
 241         scifa3: serial@e6c70000 {
 242                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 243                 reg = <0xe6c70000 0x100>;
 244                 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
 245                 clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>;
 246                 clock-names = "sci_ick";
 247                 power-domains = <&pd_a3sp>;
 248                 status = "disabled";
 249         };
 250
 251         scifa4: serial@e6c80000 {
 252                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 253                 reg = <0xe6c80000 0x100>;
 254                 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
 255                 clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>;
 256                 clock-names = "sci_ick";
 257                 power-domains = <&pd_a3sp>;
 258                 status = "disabled";
 259         };
 260
 261         scifa5: serial@e6cb0000 {
 262                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 263                 reg = <0xe6cb0000 0x100>;
 264                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
 265                 clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>;
 266                 clock-names = "sci_ick";
 267                 power-domains = <&pd_a3sp>;
 268                 status = "disabled";
 269         };
 270
 271         scifa6: serial@e6cc0000 {
 272                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 273                 reg = <0xe6cc0000 0x100>;
 274                 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 275                 clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>;
 276                 clock-names = "sci_ick";
 277                 power-domains = <&pd_a3sp>;
 278                 status = "disabled";
 279         };
 280
 281         scifa7: serial@e6cd0000 {
 282                 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 283                 reg = <0xe6cd0000 0x100>;
 284                 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
 285                 clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>;
 286                 clock-names = "sci_ick";
 287                 power-domains = <&pd_a3sp>;
 288                 status = "disabled";
 289         };
 290
 291         scifb: serial@e6c30000 {
 292                 compatible = "renesas,scifb-r8a7740", "renesas,scifb";
 293                 reg = <0xe6c30000 0x100>;
 294                 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
 295                 clocks = <&mstp2_clks R8A7740_CLK_SCIFB>;
 296                 clock-names = "sci_ick";
 297                 power-domains = <&pd_a3sp>;
 298                 status = "disabled";
 299         };
 300
 301         pfc: pfc@e6050000 {
 302                 compatible = "renesas,pfc-r8a7740";
 303                 reg = <0xe6050000 0x8000>,
 304                       <0xe605800c 0x20>;
 305                 gpio-controller;
 306                 #gpio-cells = <2>;
 307                 gpio-ranges = <&pfc 0 0 212>;
 308                 interrupts-extended =
 309                         <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
 310                         <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
 311                         <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
 312                         <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
 313                         <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
 314                         <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
 315                         <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
 316                         <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
 317                 power-domains = <&pd_c5>;
 318         };
 319
 320         tpu: pwm@e6600000 {
 321                 compatible = "renesas,tpu-r8a7740", "renesas,tpu";
 322                 reg = <0xe6600000 0x100>;
 323                 clocks = <&mstp3_clks R8A7740_CLK_TPU0>;
 324                 power-domains = <&pd_a3sp>;
 325                 status = "disabled";
 326                 #pwm-cells = <3>;
 327         };
 328
 329         mmcif0: mmc@e6bd0000 {
 330                 compatible = "renesas,mmcif-r8a7740", "renesas,sh-mmcif";
 331                 reg = <0xe6bd0000 0x100>;
 332                 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH
 333                               0 57 IRQ_TYPE_LEVEL_HIGH>;
 334                 clocks = <&mstp3_clks R8A7740_CLK_MMC>;
 335                 power-domains = <&pd_a3sp>;
 336                 status = "disabled";
 337         };
 338
 339         sdhi0: sd@e6850000 {
 340                 compatible = "renesas,sdhi-r8a7740";
 341                 reg = <0xe6850000 0x100>;
 342                 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH
 343                               0 118 IRQ_TYPE_LEVEL_HIGH
 344                               0 119 IRQ_TYPE_LEVEL_HIGH>;
 345                 clocks = <&mstp3_clks R8A7740_CLK_SDHI0>;
 346                 power-domains = <&pd_a3sp>;
 347                 cap-sd-highspeed;
 348                 cap-sdio-irq;
 349                 status = "disabled";
 350         };
 351
 352         sdhi1: sd@e6860000 {
 353                 compatible = "renesas,sdhi-r8a7740";
 354                 reg = <0xe6860000 0x100>;
 355                 interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH
 356                               0 122 IRQ_TYPE_LEVEL_HIGH
 357                               0 123 IRQ_TYPE_LEVEL_HIGH>;
 358                 clocks = <&mstp3_clks R8A7740_CLK_SDHI1>;
 359                 power-domains = <&pd_a3sp>;
 360                 cap-sd-highspeed;
 361                 cap-sdio-irq;
 362                 status = "disabled";
 363         };
 364
 365         sdhi2: sd@e6870000 {
 366                 compatible = "renesas,sdhi-r8a7740";
 367                 reg = <0xe6870000 0x100>;
 368                 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH
 369                               0 126 IRQ_TYPE_LEVEL_HIGH
 370                               0 127 IRQ_TYPE_LEVEL_HIGH>;
 371                 clocks = <&mstp4_clks R8A7740_CLK_SDHI2>;
 372                 power-domains = <&pd_a3sp>;
 373                 cap-sd-highspeed;
 374                 cap-sdio-irq;
 375                 status = "disabled";
 376         };
 377
 378         sh_fsi2: sound@fe1f0000 {
 379                 #sound-dai-cells = <1>;
 380                 compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2";
 381                 reg = <0xfe1f0000 0x400>;
 382                 interrupts = <0 9 0x4>;
 383                 clocks = <&mstp3_clks R8A7740_CLK_FSI>;
 384                 power-domains = <&pd_a4mp>;
 385                 status = "disabled";
 386         };
 387
 388         tmu0: timer@fff80000 {
 389                 compatible = "renesas,tmu-r8a7740", "renesas,tmu";
 390                 reg = <0xfff80000 0x2c>;
 391                 interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
 392                              <0 199 IRQ_TYPE_LEVEL_HIGH>,
 393                              <0 200 IRQ_TYPE_LEVEL_HIGH>;
 394                 clocks = <&mstp1_clks R8A7740_CLK_TMU0>;
 395                 clock-names = "fck";
 396                 power-domains = <&pd_a4r>;
 397
 398                 #renesas,channels = <3>;
 399
 400                 status = "disabled";
 401         };
 402
 403         tmu1: timer@fff90000 {
 404                 compatible = "renesas,tmu-r8a7740", "renesas,tmu";
 405                 reg = <0xfff90000 0x2c>;
 406                 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>,
 407                              <0 171 IRQ_TYPE_LEVEL_HIGH>,
 408                              <0 172 IRQ_TYPE_LEVEL_HIGH>;
 409                 clocks = <&mstp1_clks R8A7740_CLK_TMU1>;
 410                 clock-names = "fck";
 411                 power-domains = <&pd_a4r>;
 412
 413                 #renesas,channels = <3>;
 414
 415                 status = "disabled";
 416         };
 417
 418         clocks {
 419                 #address-cells = <1>;
 420                 #size-cells = <1>;
 421                 ranges;
 422
 423                 /* External root clock */
 424                 extalr_clk: extalr_clk {
 425                         compatible = "fixed-clock";
 426                         #clock-cells = <0>;
 427                         clock-frequency = <32768>;
 428                         clock-output-names = "extalr";
 429                 };
 430                 extal1_clk: extal1_clk {
 431                         compatible = "fixed-clock";
 432                         #clock-cells = <0>;
 433                         clock-frequency = <0>;
 434                         clock-output-names = "extal1";
 435                 };
 436                 extal2_clk: extal2_clk {
 437                         compatible = "fixed-clock";
 438                         #clock-cells = <0>;
 439                         clock-frequency = <0>;
 440                         clock-output-names = "extal2";
 441                 };
 442                 dv_clk: dv_clk {
 443                         compatible = "fixed-clock";
 444                         #clock-cells = <0>;
 445                         clock-frequency = <27000000>;
 446                         clock-output-names = "dv";
 447                 };
 448                 fmsick_clk: fmsick_clk {
 449                         compatible = "fixed-clock";
 450                         #clock-cells = <0>;
 451                         clock-frequency = <0>;
 452                         clock-output-names = "fmsick";
 453                 };
 454                 fmsock_clk: fmsock_clk {
 455                         compatible = "fixed-clock";
 456                         #clock-cells = <0>;
 457                         clock-frequency = <0>;
 458                         clock-output-names = "fmsock";
 459                 };
 460                 fsiack_clk: fsiack_clk {
 461                         compatible = "fixed-clock";
 462                         #clock-cells = <0>;
 463                         clock-frequency = <0>;
 464                         clock-output-names = "fsiack";
 465                 };
 466                 fsibck_clk: fsibck_clk {
 467                         compatible = "fixed-clock";
 468                         #clock-cells = <0>;
 469                         clock-frequency = <0>;
 470                         clock-output-names = "fsibck";
 471                 };
 472
 473                 /* Special CPG clocks */
 474                 cpg_clocks: cpg_clocks@e6150000 {
 475                         compatible = "renesas,r8a7740-cpg-clocks";
 476                         reg = <0xe6150000 0x10000>;
 477                         clocks = <&extal1_clk>, <&extalr_clk>;
 478                         #clock-cells = <1>;
 479                         clock-output-names = "system", "pllc0", "pllc1",
 480                                              "pllc2", "r",
 481                                              "usb24s",
 482                                              "i", "zg", "b", "m1", "hp",
 483                                              "hpp", "usbp", "s", "zb", "m3",
 484                                              "cp";
 485                 };
 486
 487                 /* Variable factor clocks (DIV6) */
 488                 vclk1_clk: vclk1_clk@e6150008 {
 489                         compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
 490                         reg = <0xe6150008 4>;
 491                         clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,
 492                                  <&cpg_clocks R8A7740_CLK_USB24S>,
 493                                  <&extal1_div2_clk>, <&extalr_clk>, <0>,
 494                                  <0>;
 495                         #clock-cells = <0>;
 496                         clock-output-names = "vclk1";
 497                 };
 498                 vclk2_clk: vclk2_clk@e615000c {
 499                         compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
 500                         reg = <0xe615000c 4>;
 501                         clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,
 502                                  <&cpg_clocks R8A7740_CLK_USB24S>,
 503                                  <&extal1_div2_clk>, <&extalr_clk>, <0>,
 504                                  <0>;
 505                         #clock-cells = <0>;
 506                         clock-output-names = "vclk2";
 507                 };
 508                 fmsi_clk: fmsi_clk@e6150010 {
 509                         compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
 510                         reg = <0xe6150010 4>;
 511                         clocks = <&pllc1_div2_clk>, <&fmsick_clk>, <0>, <0>;
 512                         #clock-cells = <0>;
 513                         clock-output-names = "fmsi";
 514                 };
 515                 fmso_clk: fmso_clk@e6150014 {
 516                         compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
 517                         reg = <0xe6150014 4>;
 518                         clocks = <&pllc1_div2_clk>, <&fmsock_clk>, <0>, <0>;
 519                         #clock-cells = <0>;
 520                         clock-output-names = "fmso";
 521                 };
 522                 fsia_clk: fsia_clk@e6150018 {
 523                         compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
 524                         reg = <0xe6150018 4>;
 525                         clocks = <&pllc1_div2_clk>, <&fsiack_clk>, <0>, <0>;
 526                         #clock-cells = <0>;
 527                         clock-output-names = "fsia";
 528                 };
 529                 sub_clk: sub_clk@e6150080 {
 530                         compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
 531                         reg = <0xe6150080 4>;
 532                         clocks = <&pllc1_div2_clk>,
 533                                  <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>;
 534                         #clock-cells = <0>;
 535                         clock-output-names = "sub";
 536                 };
 537                 spu_clk: spu_clk@e6150084 {
 538                         compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
 539                         reg = <0xe6150084 4>;
 540                         clocks = <&pllc1_div2_clk>,
 541                                  <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>;
 542                         #clock-cells = <0>;
 543                         clock-output-names = "spu";
 544                 };
 545                 vou_clk: vou_clk@e6150088 {
 546                         compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
 547                         reg = <0xe6150088 4>;
 548                         clocks = <&pllc1_div2_clk>, <&extal1_clk>, <&dv_clk>,
 549                                  <0>;
 550                         #clock-cells = <0>;
 551                         clock-output-names = "vou";
 552                 };
 553                 stpro_clk: stpro_clk@e615009c {
 554                         compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
 555                         reg = <0xe615009c 4>;
 556                         clocks = <&cpg_clocks R8A7740_CLK_PLLC0>;
 557                         #clock-cells = <0>;
 558                         clock-output-names = "stpro";
 559                 };
 560
 561                 /* Fixed factor clocks */
 562                 pllc1_div2_clk: pllc1_div2_clk {
 563                         compatible = "fixed-factor-clock";
 564                         clocks = <&cpg_clocks R8A7740_CLK_PLLC1>;
 565                         #clock-cells = <0>;
 566                         clock-div = <2>;
 567                         clock-mult = <1>;
 568                         clock-output-names = "pllc1_div2";
 569                 };
 570                 extal1_div2_clk: extal1_div2_clk {
 571                         compatible = "fixed-factor-clock";
 572                         clocks = <&extal1_clk>;
 573                         #clock-cells = <0>;
 574                         clock-div = <2>;
 575                         clock-mult = <1>;
 576                         clock-output-names = "extal1_div2";
 577                 };
 578
 579                 /* Gate clocks */
 580                 subck_clks: subck_clks@e6150080 {
 581                         compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
 582                         reg = <0xe6150080 4>;
 583                         clocks = <&sub_clk>, <&sub_clk>;
 584                         #clock-cells = <1>;
 585                         clock-indices = <
 586                                 R8A7740_CLK_SUBCK R8A7740_CLK_SUBCK2
 587                         >;
 588                         clock-output-names =
 589                                 "subck", "subck2";
 590                 };
 591                 mstp1_clks: mstp1_clks@e6150134 {
 592                         compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
 593                         reg = <0xe6150134 4>, <0xe6150038 4>;
 594                         clocks = <&cpg_clocks R8A7740_CLK_S>,
 595                                  <&cpg_clocks R8A7740_CLK_S>, <&sub_clk>,
 596                                  <&cpg_clocks R8A7740_CLK_B>,
 597                                  <&cpg_clocks R8A7740_CLK_HPP>, <&sub_clk>,
 598                                  <&cpg_clocks R8A7740_CLK_B>;
 599                         #clock-cells = <1>;
 600                         clock-indices = <
 601                                 R8A7740_CLK_CEU21 R8A7740_CLK_CEU20 R8A7740_CLK_TMU0
 602                                 R8A7740_CLK_LCDC1 R8A7740_CLK_IIC0 R8A7740_CLK_TMU1
 603                                 R8A7740_CLK_LCDC0
 604                         >;
 605                         clock-output-names =
 606                                 "ceu21", "ceu20", "tmu0", "lcdc1", "iic0",
 607                                 "tmu1", "lcdc0";
 608                 };
 609                 mstp2_clks: mstp2_clks@e6150138 {
 610                         compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
 611                         reg = <0xe6150138 4>, <0xe6150040 4>;
 612                         clocks = <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>,
 613                                  <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>,
 614                                  <&cpg_clocks R8A7740_CLK_HP>,
 615                                  <&cpg_clocks R8A7740_CLK_HP>,
 616                                  <&cpg_clocks R8A7740_CLK_HP>,
 617                                  <&sub_clk>, <&sub_clk>, <&sub_clk>,
 618                                  <&sub_clk>, <&sub_clk>, <&sub_clk>,
 619                                  <&sub_clk>;
 620                         #clock-cells = <1>;
 621                         clock-indices = <
 622                                 R8A7740_CLK_SCIFA6 R8A7740_CLK_INTCA
 623                                 R8A7740_CLK_SCIFA7
 624                                 R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2
 625                                 R8A7740_CLK_DMAC3 R8A7740_CLK_USBDMAC
 626                                 R8A7740_CLK_SCIFA5 R8A7740_CLK_SCIFB
 627                                 R8A7740_CLK_SCIFA0 R8A7740_CLK_SCIFA1
 628                                 R8A7740_CLK_SCIFA2 R8A7740_CLK_SCIFA3
 629                                 R8A7740_CLK_SCIFA4
 630                         >;
 631                         clock-output-names =
 632                                 "scifa6", "intca",
 633                                 "scifa7", "dmac1", "dmac2", "dmac3",
 634                                 "usbdmac", "scifa5", "scifb", "scifa0", "scifa1",
 635                                 "scifa2", "scifa3", "scifa4";
 636                 };
 637                 mstp3_clks: mstp3_clks@e615013c {
 638                         compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
 639                         reg = <0xe615013c 4>, <0xe6150048 4>;
 640                         clocks = <&cpg_clocks R8A7740_CLK_R>,
 641                                  <&cpg_clocks R8A7740_CLK_HP>,
 642                                  <&sub_clk>,
 643                                  <&cpg_clocks R8A7740_CLK_HP>,
 644                                  <&cpg_clocks R8A7740_CLK_HP>,
 645                                  <&cpg_clocks R8A7740_CLK_HP>,
 646                                  <&cpg_clocks R8A7740_CLK_HP>,
 647                                  <&cpg_clocks R8A7740_CLK_HP>,
 648                                  <&cpg_clocks R8A7740_CLK_HP>;
 649                         #clock-cells = <1>;
 650                         clock-indices = <
 651                                 R8A7740_CLK_CMT1 R8A7740_CLK_FSI R8A7740_CLK_IIC1
 652                                 R8A7740_CLK_USBF R8A7740_CLK_SDHI0 R8A7740_CLK_SDHI1
 653                                 R8A7740_CLK_MMC R8A7740_CLK_GETHER R8A7740_CLK_TPU0
 654                         >;
 655                         clock-output-names =
 656                                 "cmt1", "fsi", "iic1", "usbf", "sdhi0", "sdhi1",
 657                                 "mmc", "gether", "tpu0";
 658                 };
 659                 mstp4_clks: mstp4_clks@e6150140 {
 660                         compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
 661                         reg = <0xe6150140 4>, <0xe615004c 4>;
 662                         clocks = <&cpg_clocks R8A7740_CLK_HP>,
 663                                  <&cpg_clocks R8A7740_CLK_HP>,
 664                                  <&cpg_clocks R8A7740_CLK_HP>,
 665                                  <&cpg_clocks R8A7740_CLK_HP>;
 666                         #clock-cells = <1>;
 667                         clock-indices = <
 668                                 R8A7740_CLK_USBH R8A7740_CLK_SDHI2
 669                                 R8A7740_CLK_USBFUNC R8A7740_CLK_USBPHY
 670                         >;
 671                         clock-output-names =
 672                                 "usbhost", "sdhi2", "usbfunc", "usphy";
 673                 };
 674         };
 675
 676         sysc: system-controller@e6180000 {
 677                 compatible = "renesas,sysc-r8a7740", "renesas,sysc-rmobile";
 678                 reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
 679
 680                 pm-domains {
 681                         pd_c5: c5 {
 682                                 #address-cells = <1>;
 683                                 #size-cells = <0>;
 684                                 #power-domain-cells = <0>;
 685
 686                                 pd_a4lc: a4lc@1 {
 687                                         reg = <1>;
 688                                         #power-domain-cells = <0>;
 689                                 };
 690
 691                                 pd_a4mp: a4mp@2 {
 692                                         reg = <2>;
 693                                         #power-domain-cells = <0>;
 694                                 };
 695
 696                                 pd_d4: d4@3 {
 697                                         reg = <3>;
 698                                         #power-domain-cells = <0>;
 699                                 };
 700
 701                                 pd_a4r: a4r@5 {
 702                                         reg = <5>;
 703                                         #address-cells = <1>;
 704                                         #size-cells = <0>;
 705                                         #power-domain-cells = <0>;
 706
 707                                         pd_a3rv: a3rv@6 {
 708                                                 reg = <6>;
 709                                                 #power-domain-cells = <0>;
 710                                         };
 711                                 };
 712
 713                                 pd_a4s: a4s@10 {
 714                                         reg = <10>;
 715                                         #address-cells = <1>;
 716                                         #size-cells = <0>;
 717                                         #power-domain-cells = <0>;
 718
 719                                         pd_a3sp: a3sp@11 {
 720                                                 reg = <11>;
 721                                                 #power-domain-cells = <0>;
 722                                         };
 723
 724                                         pd_a3sm: a3sm@12 {
 725                                                 reg = <12>;
 726                                                 #power-domain-cells = <0>;
 727                                         };
 728
 729                                         pd_a3sg: a3sg@13 {
 730                                                 reg = <13>;
 731                                                 #power-domain-cells = <0>;
 732                                         };
 733                                 };
 734
 735                                 pd_a4su: a4su@20 {
 736                                         reg = <20>;
 737                                         #power-domain-cells = <0>;
 738                                 };
 739                         };
 740                 };
 741         };
 742 };