2 * Device Tree Source for Renesas r8a7779
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Simon Horman
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
12 /include/ "skeleton.dtsi"
14 #include <dt-bindings/clock/r8a7779-clock.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
18 compatible = "renesas,r8a7779";
19 interrupt-parent = <&gic>;
27 compatible = "arm,cortex-a9";
29 clock-frequency = <1000000000>;
33 compatible = "arm,cortex-a9";
35 clock-frequency = <1000000000>;
39 compatible = "arm,cortex-a9";
41 clock-frequency = <1000000000>;
45 compatible = "arm,cortex-a9";
47 clock-frequency = <1000000000>;
57 gic: interrupt-controller@f0001000 {
58 compatible = "arm,cortex-a9-gic";
59 #interrupt-cells = <3>;
61 reg = <0xf0001000 0x1000>,
65 gpio0: gpio@ffc40000 {
66 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
67 reg = <0xffc40000 0x2c>;
68 interrupts = <0 141 IRQ_TYPE_LEVEL_HIGH>;
71 gpio-ranges = <&pfc 0 0 32>;
72 #interrupt-cells = <2>;
76 gpio1: gpio@ffc41000 {
77 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
78 reg = <0xffc41000 0x2c>;
79 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>;
82 gpio-ranges = <&pfc 0 32 32>;
83 #interrupt-cells = <2>;
87 gpio2: gpio@ffc42000 {
88 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
89 reg = <0xffc42000 0x2c>;
90 interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
93 gpio-ranges = <&pfc 0 64 32>;
94 #interrupt-cells = <2>;
98 gpio3: gpio@ffc43000 {
99 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
100 reg = <0xffc43000 0x2c>;
101 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
104 gpio-ranges = <&pfc 0 96 32>;
105 #interrupt-cells = <2>;
106 interrupt-controller;
109 gpio4: gpio@ffc44000 {
110 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
111 reg = <0xffc44000 0x2c>;
112 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
115 gpio-ranges = <&pfc 0 128 32>;
116 #interrupt-cells = <2>;
117 interrupt-controller;
120 gpio5: gpio@ffc45000 {
121 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
122 reg = <0xffc45000 0x2c>;
123 interrupts = <0 146 IRQ_TYPE_LEVEL_HIGH>;
126 gpio-ranges = <&pfc 0 160 32>;
127 #interrupt-cells = <2>;
128 interrupt-controller;
131 gpio6: gpio@ffc46000 {
132 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
133 reg = <0xffc46000 0x2c>;
134 interrupts = <0 147 IRQ_TYPE_LEVEL_HIGH>;
137 gpio-ranges = <&pfc 0 192 9>;
138 #interrupt-cells = <2>;
139 interrupt-controller;
142 irqpin0: irqpin@fe780010 {
143 compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin";
144 #interrupt-cells = <2>;
146 interrupt-controller;
147 reg = <0xfe78001c 4>,
152 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH
153 0 28 IRQ_TYPE_LEVEL_HIGH
154 0 29 IRQ_TYPE_LEVEL_HIGH
155 0 30 IRQ_TYPE_LEVEL_HIGH>;
156 sense-bitfield-width = <2>;
160 #address-cells = <1>;
162 compatible = "renesas,i2c-r8a7779";
163 reg = <0xffc70000 0x1000>;
164 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
165 clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
170 #address-cells = <1>;
172 compatible = "renesas,i2c-r8a7779";
173 reg = <0xffc71000 0x1000>;
174 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
175 clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
180 #address-cells = <1>;
182 compatible = "renesas,i2c-r8a7779";
183 reg = <0xffc72000 0x1000>;
184 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
185 clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
190 #address-cells = <1>;
192 compatible = "renesas,i2c-r8a7779";
193 reg = <0xffc73000 0x1000>;
194 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
195 clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
199 scif0: serial@ffe40000 {
200 compatible = "renesas,scif-r8a7779", "renesas,scif";
201 reg = <0xffe40000 0x100>;
202 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
203 clocks = <&cpg_clocks R8A7779_CLK_P>;
204 clock-names = "sci_ick";
208 scif1: serial@ffe41000 {
209 compatible = "renesas,scif-r8a7779", "renesas,scif";
210 reg = <0xffe41000 0x100>;
211 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
212 clocks = <&cpg_clocks R8A7779_CLK_P>;
213 clock-names = "sci_ick";
217 scif2: serial@ffe42000 {
218 compatible = "renesas,scif-r8a7779", "renesas,scif";
219 reg = <0xffe42000 0x100>;
220 interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>;
221 clocks = <&cpg_clocks R8A7779_CLK_P>;
222 clock-names = "sci_ick";
226 scif3: serial@ffe43000 {
227 compatible = "renesas,scif-r8a7779", "renesas,scif";
228 reg = <0xffe43000 0x100>;
229 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>;
230 clocks = <&cpg_clocks R8A7779_CLK_P>;
231 clock-names = "sci_ick";
235 scif4: serial@ffe44000 {
236 compatible = "renesas,scif-r8a7779", "renesas,scif";
237 reg = <0xffe44000 0x100>;
238 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
239 clocks = <&cpg_clocks R8A7779_CLK_P>;
240 clock-names = "sci_ick";
244 scif5: serial@ffe45000 {
245 compatible = "renesas,scif-r8a7779", "renesas,scif";
246 reg = <0xffe45000 0x100>;
247 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
248 clocks = <&cpg_clocks R8A7779_CLK_P>;
249 clock-names = "sci_ick";
254 compatible = "renesas,pfc-r8a7779";
255 reg = <0xfffc0000 0x23c>;
259 compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal";
260 reg = <0xffc48000 0x38>;
263 sata: sata@fc600000 {
264 compatible = "renesas,rcar-sata";
265 reg = <0xfc600000 0x2000>;
266 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
267 clocks = <&mstp1_clks R8A7779_CLK_SATA>;
271 compatible = "renesas,sdhi-r8a7779";
272 reg = <0xffe4c000 0x100>;
273 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
274 clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
281 compatible = "renesas,sdhi-r8a7779";
282 reg = <0xffe4d000 0x100>;
283 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
284 clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
291 compatible = "renesas,sdhi-r8a7779";
292 reg = <0xffe4e000 0x100>;
293 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
294 clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
301 compatible = "renesas,sdhi-r8a7779";
302 reg = <0xffe4f000 0x100>;
303 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
310 hspi0: spi@fffc7000 {
311 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
312 reg = <0xfffc7000 0x18>;
313 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
314 #address-cells = <1>;
316 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
320 hspi1: spi@fffc8000 {
321 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
322 reg = <0xfffc8000 0x18>;
323 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
324 #address-cells = <1>;
326 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
330 hspi2: spi@fffc6000 {
331 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
332 reg = <0xfffc6000 0x18>;
333 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
334 #address-cells = <1>;
336 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
341 #address-cells = <1>;
345 /* External root clock */
346 extal_clk: extal_clk {
347 compatible = "fixed-clock";
349 /* This value must be overriden by the board. */
350 clock-frequency = <0>;
351 clock-output-names = "extal";
354 /* Special CPG clocks */
355 cpg_clocks: clocks@ffc80000 {
356 compatible = "renesas,r8a7779-cpg-clocks";
357 reg = <0xffc80000 0x30>;
358 clocks = <&extal_clk>;
360 clock-output-names = "plla", "z", "zs", "s",
361 "s1", "p", "b", "out";
364 /* Fixed factor clocks */
366 compatible = "fixed-factor-clock";
367 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
371 clock-output-names = "i";
374 compatible = "fixed-factor-clock";
375 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
379 clock-output-names = "s3";
382 compatible = "fixed-factor-clock";
383 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
387 clock-output-names = "s4";
390 compatible = "fixed-factor-clock";
391 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
395 clock-output-names = "g";
399 mstp0_clks: clocks@ffc80030 {
400 compatible = "renesas,r8a7779-mstp-clocks",
401 "renesas,cpg-mstp-clocks";
402 reg = <0xffc80030 4>;
403 clocks = <&cpg_clocks R8A7779_CLK_S>,
404 <&cpg_clocks R8A7779_CLK_P>,
405 <&cpg_clocks R8A7779_CLK_P>,
406 <&cpg_clocks R8A7779_CLK_P>,
407 <&cpg_clocks R8A7779_CLK_S>,
408 <&cpg_clocks R8A7779_CLK_S>,
409 <&cpg_clocks R8A7779_CLK_S1>,
410 <&cpg_clocks R8A7779_CLK_S1>,
411 <&cpg_clocks R8A7779_CLK_S1>,
412 <&cpg_clocks R8A7779_CLK_S1>,
413 <&cpg_clocks R8A7779_CLK_S1>,
414 <&cpg_clocks R8A7779_CLK_S1>,
415 <&cpg_clocks R8A7779_CLK_P>,
416 <&cpg_clocks R8A7779_CLK_P>,
417 <&cpg_clocks R8A7779_CLK_P>,
418 <&cpg_clocks R8A7779_CLK_P>;
420 renesas,clock-indices = <
421 R8A7779_CLK_HSPI R8A7779_CLK_TMU2
422 R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
423 R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
424 R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
425 R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
426 R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
427 R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
428 R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
431 "hspi", "tmu2", "tmu1", "tmu0", "hscif1",
432 "hscif0", "scif5", "scif4", "scif3", "scif2",
433 "scif1", "scif0", "i2c3", "i2c2", "i2c1",
436 mstp1_clks: clocks@ffc80034 {
437 compatible = "renesas,r8a7779-mstp-clocks",
438 "renesas,cpg-mstp-clocks";
439 reg = <0xffc80034 4>, <0xffc80044 4>;
440 clocks = <&cpg_clocks R8A7779_CLK_P>,
441 <&cpg_clocks R8A7779_CLK_P>,
442 <&cpg_clocks R8A7779_CLK_S>,
443 <&cpg_clocks R8A7779_CLK_S>,
444 <&cpg_clocks R8A7779_CLK_S>,
445 <&cpg_clocks R8A7779_CLK_S>,
446 <&cpg_clocks R8A7779_CLK_P>,
447 <&cpg_clocks R8A7779_CLK_P>,
448 <&cpg_clocks R8A7779_CLK_P>,
449 <&cpg_clocks R8A7779_CLK_S>;
451 renesas,clock-indices = <
452 R8A7779_CLK_USB01 R8A7779_CLK_USB2
453 R8A7779_CLK_DU R8A7779_CLK_VIN2
454 R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
455 R8A7779_CLK_ETHER R8A7779_CLK_SATA
456 R8A7779_CLK_PCIE R8A7779_CLK_VIN3
465 mstp3_clks: clocks@ffc8003c {
466 compatible = "renesas,r8a7779-mstp-clocks",
467 "renesas,cpg-mstp-clocks";
468 reg = <0xffc8003c 4>;
469 clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
470 <&s4_clk>, <&s4_clk>;
472 renesas,clock-indices = <
473 R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
474 R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
475 R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
478 "sdhi3", "sdhi2", "sdhi1", "sdhi0",