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ARM: dts: armadillo800eva: Fix W=1 dtc warnings
[deliverable/linux.git] / arch / arm / boot / dts / r8a7790.dtsi
1 /*
2 * Device Tree Source for the r8a7790 SoC
3 *
4 * Copyright (C) 2015 Renesas Electronics Corporation
5 * Copyright (C) 2013-2014 Renesas Solutions Corp.
6 * Copyright (C) 2014 Cogent Embedded Inc.
7 *
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
11 */
12
13 #include <dt-bindings/clock/r8a7790-clock.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/power/r8a7790-sysc.h>
17
18 / {
19 compatible = "renesas,r8a7790";
20 interrupt-parent = <&gic>;
21 #address-cells = <2>;
22 #size-cells = <2>;
23
24 aliases {
25 i2c0 = &i2c0;
26 i2c1 = &i2c1;
27 i2c2 = &i2c2;
28 i2c3 = &i2c3;
29 i2c4 = &iic0;
30 i2c5 = &iic1;
31 i2c6 = &iic2;
32 i2c7 = &iic3;
33 spi0 = &qspi;
34 spi1 = &msiof0;
35 spi2 = &msiof1;
36 spi3 = &msiof2;
37 spi4 = &msiof3;
38 vin0 = &vin0;
39 vin1 = &vin1;
40 vin2 = &vin2;
41 vin3 = &vin3;
42 };
43
44 cpus {
45 #address-cells = <1>;
46 #size-cells = <0>;
47
48 cpu0: cpu@0 {
49 device_type = "cpu";
50 compatible = "arm,cortex-a15";
51 reg = <0>;
52 clock-frequency = <1300000000>;
53 voltage-tolerance = <1>; /* 1% */
54 clocks = <&cpg_clocks R8A7790_CLK_Z>;
55 clock-latency = <300000>; /* 300 us */
56 power-domains = <&sysc R8A7790_PD_CA15_CPU0>;
57 next-level-cache = <&L2_CA15>;
58
59 /* kHz - uV - OPPs unknown yet */
60 operating-points = <1400000 1000000>,
61 <1225000 1000000>,
62 <1050000 1000000>,
63 < 875000 1000000>,
64 < 700000 1000000>,
65 < 350000 1000000>;
66 };
67
68 cpu1: cpu@1 {
69 device_type = "cpu";
70 compatible = "arm,cortex-a15";
71 reg = <1>;
72 clock-frequency = <1300000000>;
73 power-domains = <&sysc R8A7790_PD_CA15_CPU1>;
74 next-level-cache = <&L2_CA15>;
75 };
76
77 cpu2: cpu@2 {
78 device_type = "cpu";
79 compatible = "arm,cortex-a15";
80 reg = <2>;
81 clock-frequency = <1300000000>;
82 power-domains = <&sysc R8A7790_PD_CA15_CPU2>;
83 next-level-cache = <&L2_CA15>;
84 };
85
86 cpu3: cpu@3 {
87 device_type = "cpu";
88 compatible = "arm,cortex-a15";
89 reg = <3>;
90 clock-frequency = <1300000000>;
91 power-domains = <&sysc R8A7790_PD_CA15_CPU3>;
92 next-level-cache = <&L2_CA15>;
93 };
94
95 cpu4: cpu@100 {
96 device_type = "cpu";
97 compatible = "arm,cortex-a7";
98 reg = <0x100>;
99 clock-frequency = <780000000>;
100 power-domains = <&sysc R8A7790_PD_CA7_CPU0>;
101 next-level-cache = <&L2_CA7>;
102 };
103
104 cpu5: cpu@101 {
105 device_type = "cpu";
106 compatible = "arm,cortex-a7";
107 reg = <0x101>;
108 clock-frequency = <780000000>;
109 power-domains = <&sysc R8A7790_PD_CA7_CPU1>;
110 next-level-cache = <&L2_CA7>;
111 };
112
113 cpu6: cpu@102 {
114 device_type = "cpu";
115 compatible = "arm,cortex-a7";
116 reg = <0x102>;
117 clock-frequency = <780000000>;
118 power-domains = <&sysc R8A7790_PD_CA7_CPU2>;
119 next-level-cache = <&L2_CA7>;
120 };
121
122 cpu7: cpu@103 {
123 device_type = "cpu";
124 compatible = "arm,cortex-a7";
125 reg = <0x103>;
126 clock-frequency = <780000000>;
127 power-domains = <&sysc R8A7790_PD_CA7_CPU3>;
128 next-level-cache = <&L2_CA7>;
129 };
130
131 L2_CA15: cache-controller@0 {
132 compatible = "cache";
133 reg = <0>;
134 power-domains = <&sysc R8A7790_PD_CA15_SCU>;
135 cache-unified;
136 cache-level = <2>;
137 };
138
139 L2_CA7: cache-controller@100 {
140 compatible = "cache";
141 reg = <0x100>;
142 power-domains = <&sysc R8A7790_PD_CA7_SCU>;
143 cache-unified;
144 cache-level = <2>;
145 };
146 };
147
148 thermal-zones {
149 cpu_thermal: cpu-thermal {
150 polling-delay-passive = <0>;
151 polling-delay = <0>;
152
153 thermal-sensors = <&thermal>;
154
155 trips {
156 cpu-crit {
157 temperature = <115000>;
158 hysteresis = <0>;
159 type = "critical";
160 };
161 };
162 cooling-maps {
163 };
164 };
165 };
166
167 gic: interrupt-controller@f1001000 {
168 compatible = "arm,gic-400";
169 #interrupt-cells = <3>;
170 #address-cells = <0>;
171 interrupt-controller;
172 reg = <0 0xf1001000 0 0x1000>,
173 <0 0xf1002000 0 0x1000>,
174 <0 0xf1004000 0 0x2000>,
175 <0 0xf1006000 0 0x2000>;
176 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
177 };
178
179 gpio0: gpio@e6050000 {
180 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
181 reg = <0 0xe6050000 0 0x50>;
182 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
183 #gpio-cells = <2>;
184 gpio-controller;
185 gpio-ranges = <&pfc 0 0 32>;
186 #interrupt-cells = <2>;
187 interrupt-controller;
188 clocks = <&mstp9_clks R8A7790_CLK_GPIO0>;
189 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
190 };
191
192 gpio1: gpio@e6051000 {
193 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
194 reg = <0 0xe6051000 0 0x50>;
195 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
196 #gpio-cells = <2>;
197 gpio-controller;
198 gpio-ranges = <&pfc 0 32 30>;
199 #interrupt-cells = <2>;
200 interrupt-controller;
201 clocks = <&mstp9_clks R8A7790_CLK_GPIO1>;
202 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
203 };
204
205 gpio2: gpio@e6052000 {
206 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
207 reg = <0 0xe6052000 0 0x50>;
208 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
209 #gpio-cells = <2>;
210 gpio-controller;
211 gpio-ranges = <&pfc 0 64 30>;
212 #interrupt-cells = <2>;
213 interrupt-controller;
214 clocks = <&mstp9_clks R8A7790_CLK_GPIO2>;
215 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
216 };
217
218 gpio3: gpio@e6053000 {
219 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
220 reg = <0 0xe6053000 0 0x50>;
221 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
222 #gpio-cells = <2>;
223 gpio-controller;
224 gpio-ranges = <&pfc 0 96 32>;
225 #interrupt-cells = <2>;
226 interrupt-controller;
227 clocks = <&mstp9_clks R8A7790_CLK_GPIO3>;
228 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
229 };
230
231 gpio4: gpio@e6054000 {
232 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
233 reg = <0 0xe6054000 0 0x50>;
234 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
235 #gpio-cells = <2>;
236 gpio-controller;
237 gpio-ranges = <&pfc 0 128 32>;
238 #interrupt-cells = <2>;
239 interrupt-controller;
240 clocks = <&mstp9_clks R8A7790_CLK_GPIO4>;
241 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
242 };
243
244 gpio5: gpio@e6055000 {
245 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
246 reg = <0 0xe6055000 0 0x50>;
247 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
248 #gpio-cells = <2>;
249 gpio-controller;
250 gpio-ranges = <&pfc 0 160 32>;
251 #interrupt-cells = <2>;
252 interrupt-controller;
253 clocks = <&mstp9_clks R8A7790_CLK_GPIO5>;
254 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
255 };
256
257 thermal: thermal@e61f0000 {
258 compatible = "renesas,thermal-r8a7790",
259 "renesas,rcar-gen2-thermal",
260 "renesas,rcar-thermal";
261 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
262 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
263 clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
264 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
265 #thermal-sensor-cells = <0>;
266 };
267
268 timer {
269 compatible = "arm,armv7-timer";
270 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
271 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
272 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
273 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
274 };
275
276 cmt0: timer@ffca0000 {
277 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
278 reg = <0 0xffca0000 0 0x1004>;
279 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
281 clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
282 clock-names = "fck";
283 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
284
285 renesas,channels-mask = <0x60>;
286
287 status = "disabled";
288 };
289
290 cmt1: timer@e6130000 {
291 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
292 reg = <0 0xe6130000 0 0x1004>;
293 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
297 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
301 clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
302 clock-names = "fck";
303 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
304
305 renesas,channels-mask = <0xff>;
306
307 status = "disabled";
308 };
309
310 irqc0: interrupt-controller@e61c0000 {
311 compatible = "renesas,irqc-r8a7790", "renesas,irqc";
312 #interrupt-cells = <2>;
313 interrupt-controller;
314 reg = <0 0xe61c0000 0 0x200>;
315 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
316 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
317 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
318 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
319 clocks = <&mstp4_clks R8A7790_CLK_IRQC>;
320 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
321 };
322
323 dmac0: dma-controller@e6700000 {
324 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
325 reg = <0 0xe6700000 0 0x20000>;
326 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
327 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
328 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
329 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
330 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
331 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
332 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
333 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
334 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
335 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
336 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
337 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
338 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
339 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
340 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
341 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
342 interrupt-names = "error",
343 "ch0", "ch1", "ch2", "ch3",
344 "ch4", "ch5", "ch6", "ch7",
345 "ch8", "ch9", "ch10", "ch11",
346 "ch12", "ch13", "ch14";
347 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
348 clock-names = "fck";
349 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
350 #dma-cells = <1>;
351 dma-channels = <15>;
352 };
353
354 dmac1: dma-controller@e6720000 {
355 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
356 reg = <0 0xe6720000 0 0x20000>;
357 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
358 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
359 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
360 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
361 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
362 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
363 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
364 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
365 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
366 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
367 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
368 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
369 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
370 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
371 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
372 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
373 interrupt-names = "error",
374 "ch0", "ch1", "ch2", "ch3",
375 "ch4", "ch5", "ch6", "ch7",
376 "ch8", "ch9", "ch10", "ch11",
377 "ch12", "ch13", "ch14";
378 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
379 clock-names = "fck";
380 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
381 #dma-cells = <1>;
382 dma-channels = <15>;
383 };
384
385 audma0: dma-controller@ec700000 {
386 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
387 reg = <0 0xec700000 0 0x10000>;
388 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
389 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
390 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
391 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
392 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
393 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
394 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
395 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
396 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
397 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
398 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
399 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
400 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
401 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
402 interrupt-names = "error",
403 "ch0", "ch1", "ch2", "ch3",
404 "ch4", "ch5", "ch6", "ch7",
405 "ch8", "ch9", "ch10", "ch11",
406 "ch12";
407 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>;
408 clock-names = "fck";
409 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
410 #dma-cells = <1>;
411 dma-channels = <13>;
412 };
413
414 audma1: dma-controller@ec720000 {
415 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
416 reg = <0 0xec720000 0 0x10000>;
417 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
418 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
419 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
420 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
421 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
422 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
423 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
424 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
425 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
426 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
427 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
428 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
429 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
430 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
431 interrupt-names = "error",
432 "ch0", "ch1", "ch2", "ch3",
433 "ch4", "ch5", "ch6", "ch7",
434 "ch8", "ch9", "ch10", "ch11",
435 "ch12";
436 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>;
437 clock-names = "fck";
438 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
439 #dma-cells = <1>;
440 dma-channels = <13>;
441 };
442
443 usb_dmac0: dma-controller@e65a0000 {
444 compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac";
445 reg = <0 0xe65a0000 0 0x100>;
446 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
447 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
448 interrupt-names = "ch0", "ch1";
449 clocks = <&mstp3_clks R8A7790_CLK_USBDMAC0>;
450 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
451 #dma-cells = <1>;
452 dma-channels = <2>;
453 };
454
455 usb_dmac1: dma-controller@e65b0000 {
456 compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac";
457 reg = <0 0xe65b0000 0 0x100>;
458 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
459 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
460 interrupt-names = "ch0", "ch1";
461 clocks = <&mstp3_clks R8A7790_CLK_USBDMAC1>;
462 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
463 #dma-cells = <1>;
464 dma-channels = <2>;
465 };
466
467 i2c0: i2c@e6508000 {
468 #address-cells = <1>;
469 #size-cells = <0>;
470 compatible = "renesas,i2c-r8a7790";
471 reg = <0 0xe6508000 0 0x40>;
472 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
473 clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
474 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
475 i2c-scl-internal-delay-ns = <110>;
476 status = "disabled";
477 };
478
479 i2c1: i2c@e6518000 {
480 #address-cells = <1>;
481 #size-cells = <0>;
482 compatible = "renesas,i2c-r8a7790";
483 reg = <0 0xe6518000 0 0x40>;
484 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
485 clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
486 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
487 i2c-scl-internal-delay-ns = <6>;
488 status = "disabled";
489 };
490
491 i2c2: i2c@e6530000 {
492 #address-cells = <1>;
493 #size-cells = <0>;
494 compatible = "renesas,i2c-r8a7790";
495 reg = <0 0xe6530000 0 0x40>;
496 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
497 clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
498 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
499 i2c-scl-internal-delay-ns = <6>;
500 status = "disabled";
501 };
502
503 i2c3: i2c@e6540000 {
504 #address-cells = <1>;
505 #size-cells = <0>;
506 compatible = "renesas,i2c-r8a7790";
507 reg = <0 0xe6540000 0 0x40>;
508 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
509 clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
510 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
511 i2c-scl-internal-delay-ns = <110>;
512 status = "disabled";
513 };
514
515 iic0: i2c@e6500000 {
516 #address-cells = <1>;
517 #size-cells = <0>;
518 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
519 reg = <0 0xe6500000 0 0x425>;
520 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
522 dmas = <&dmac0 0x61>, <&dmac0 0x62>,
523 <&dmac1 0x61>, <&dmac1 0x62>;
524 dma-names = "tx", "rx", "tx", "rx";
525 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
526 status = "disabled";
527 };
528
529 iic1: i2c@e6510000 {
530 #address-cells = <1>;
531 #size-cells = <0>;
532 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
533 reg = <0 0xe6510000 0 0x425>;
534 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
535 clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
536 dmas = <&dmac0 0x65>, <&dmac0 0x66>,
537 <&dmac1 0x65>, <&dmac1 0x66>;
538 dma-names = "tx", "rx", "tx", "rx";
539 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
540 status = "disabled";
541 };
542
543 iic2: i2c@e6520000 {
544 #address-cells = <1>;
545 #size-cells = <0>;
546 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
547 reg = <0 0xe6520000 0 0x425>;
548 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
549 clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
550 dmas = <&dmac0 0x69>, <&dmac0 0x6a>,
551 <&dmac1 0x69>, <&dmac1 0x6a>;
552 dma-names = "tx", "rx", "tx", "rx";
553 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
554 status = "disabled";
555 };
556
557 iic3: i2c@e60b0000 {
558 #address-cells = <1>;
559 #size-cells = <0>;
560 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
561 reg = <0 0xe60b0000 0 0x425>;
562 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
563 clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
564 dmas = <&dmac0 0x77>, <&dmac0 0x78>,
565 <&dmac1 0x77>, <&dmac1 0x78>;
566 dma-names = "tx", "rx", "tx", "rx";
567 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
568 status = "disabled";
569 };
570
571 mmcif0: mmc@ee200000 {
572 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
573 reg = <0 0xee200000 0 0x80>;
574 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
575 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
576 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
577 <&dmac1 0xd1>, <&dmac1 0xd2>;
578 dma-names = "tx", "rx", "tx", "rx";
579 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
580 reg-io-width = <4>;
581 status = "disabled";
582 max-frequency = <97500000>;
583 };
584
585 mmcif1: mmc@ee220000 {
586 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
587 reg = <0 0xee220000 0 0x80>;
588 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
589 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
590 dmas = <&dmac0 0xe1>, <&dmac0 0xe2>,
591 <&dmac1 0xe1>, <&dmac1 0xe2>;
592 dma-names = "tx", "rx", "tx", "rx";
593 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
594 reg-io-width = <4>;
595 status = "disabled";
596 max-frequency = <97500000>;
597 };
598
599 pfc: pfc@e6060000 {
600 compatible = "renesas,pfc-r8a7790";
601 reg = <0 0xe6060000 0 0x250>;
602 };
603
604 sdhi0: sd@ee100000 {
605 compatible = "renesas,sdhi-r8a7790";
606 reg = <0 0xee100000 0 0x328>;
607 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
608 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
609 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
610 <&dmac1 0xcd>, <&dmac1 0xce>;
611 dma-names = "tx", "rx", "tx", "rx";
612 max-frequency = <195000000>;
613 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
614 status = "disabled";
615 };
616
617 sdhi1: sd@ee120000 {
618 compatible = "renesas,sdhi-r8a7790";
619 reg = <0 0xee120000 0 0x328>;
620 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
621 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
622 dmas = <&dmac0 0xc9>, <&dmac0 0xca>,
623 <&dmac1 0xc9>, <&dmac1 0xca>;
624 dma-names = "tx", "rx", "tx", "rx";
625 max-frequency = <195000000>;
626 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
627 status = "disabled";
628 };
629
630 sdhi2: sd@ee140000 {
631 compatible = "renesas,sdhi-r8a7790";
632 reg = <0 0xee140000 0 0x100>;
633 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
634 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
635 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
636 <&dmac1 0xc1>, <&dmac1 0xc2>;
637 dma-names = "tx", "rx", "tx", "rx";
638 max-frequency = <97500000>;
639 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
640 status = "disabled";
641 };
642
643 sdhi3: sd@ee160000 {
644 compatible = "renesas,sdhi-r8a7790";
645 reg = <0 0xee160000 0 0x100>;
646 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
647 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
648 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
649 <&dmac1 0xd3>, <&dmac1 0xd4>;
650 dma-names = "tx", "rx", "tx", "rx";
651 max-frequency = <97500000>;
652 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
653 status = "disabled";
654 };
655
656 scifa0: serial@e6c40000 {
657 compatible = "renesas,scifa-r8a7790",
658 "renesas,rcar-gen2-scifa", "renesas,scifa";
659 reg = <0 0xe6c40000 0 64>;
660 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
661 clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
662 clock-names = "fck";
663 dmas = <&dmac0 0x21>, <&dmac0 0x22>,
664 <&dmac1 0x21>, <&dmac1 0x22>;
665 dma-names = "tx", "rx", "tx", "rx";
666 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
667 status = "disabled";
668 };
669
670 scifa1: serial@e6c50000 {
671 compatible = "renesas,scifa-r8a7790",
672 "renesas,rcar-gen2-scifa", "renesas,scifa";
673 reg = <0 0xe6c50000 0 64>;
674 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
675 clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>;
676 clock-names = "fck";
677 dmas = <&dmac0 0x25>, <&dmac0 0x26>,
678 <&dmac1 0x25>, <&dmac1 0x26>;
679 dma-names = "tx", "rx", "tx", "rx";
680 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
681 status = "disabled";
682 };
683
684 scifa2: serial@e6c60000 {
685 compatible = "renesas,scifa-r8a7790",
686 "renesas,rcar-gen2-scifa", "renesas,scifa";
687 reg = <0 0xe6c60000 0 64>;
688 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
689 clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>;
690 clock-names = "fck";
691 dmas = <&dmac0 0x27>, <&dmac0 0x28>,
692 <&dmac1 0x27>, <&dmac1 0x28>;
693 dma-names = "tx", "rx", "tx", "rx";
694 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
695 status = "disabled";
696 };
697
698 scifb0: serial@e6c20000 {
699 compatible = "renesas,scifb-r8a7790",
700 "renesas,rcar-gen2-scifb", "renesas,scifb";
701 reg = <0 0xe6c20000 0 64>;
702 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
703 clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>;
704 clock-names = "fck";
705 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
706 <&dmac1 0x3d>, <&dmac1 0x3e>;
707 dma-names = "tx", "rx", "tx", "rx";
708 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
709 status = "disabled";
710 };
711
712 scifb1: serial@e6c30000 {
713 compatible = "renesas,scifb-r8a7790",
714 "renesas,rcar-gen2-scifb", "renesas,scifb";
715 reg = <0 0xe6c30000 0 64>;
716 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
717 clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>;
718 clock-names = "fck";
719 dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
720 <&dmac1 0x19>, <&dmac1 0x1a>;
721 dma-names = "tx", "rx", "tx", "rx";
722 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
723 status = "disabled";
724 };
725
726 scifb2: serial@e6ce0000 {
727 compatible = "renesas,scifb-r8a7790",
728 "renesas,rcar-gen2-scifb", "renesas,scifb";
729 reg = <0 0xe6ce0000 0 64>;
730 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
731 clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>;
732 clock-names = "fck";
733 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
734 <&dmac1 0x1d>, <&dmac1 0x1e>;
735 dma-names = "tx", "rx", "tx", "rx";
736 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
737 status = "disabled";
738 };
739
740 scif0: serial@e6e60000 {
741 compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
742 "renesas,scif";
743 reg = <0 0xe6e60000 0 64>;
744 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
745 clocks = <&mstp7_clks R8A7790_CLK_SCIF0>, <&zs_clk>,
746 <&scif_clk>;
747 clock-names = "fck", "brg_int", "scif_clk";
748 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
749 <&dmac1 0x29>, <&dmac1 0x2a>;
750 dma-names = "tx", "rx", "tx", "rx";
751 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
752 status = "disabled";
753 };
754
755 scif1: serial@e6e68000 {
756 compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
757 "renesas,scif";
758 reg = <0 0xe6e68000 0 64>;
759 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
760 clocks = <&mstp7_clks R8A7790_CLK_SCIF1>, <&zs_clk>,
761 <&scif_clk>;
762 clock-names = "fck", "brg_int", "scif_clk";
763 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
764 <&dmac1 0x2d>, <&dmac1 0x2e>;
765 dma-names = "tx", "rx", "tx", "rx";
766 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
767 status = "disabled";
768 };
769
770 scif2: serial@e6e56000 {
771 compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
772 "renesas,scif";
773 reg = <0 0xe6e56000 0 64>;
774 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
775 clocks = <&mstp3_clks R8A7790_CLK_SCIF2>, <&zs_clk>,
776 <&scif_clk>;
777 clock-names = "fck", "brg_int", "scif_clk";
778 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
779 <&dmac1 0x2b>, <&dmac1 0x2c>;
780 dma-names = "tx", "rx", "tx", "rx";
781 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
782 status = "disabled";
783 };
784
785 hscif0: serial@e62c0000 {
786 compatible = "renesas,hscif-r8a7790",
787 "renesas,rcar-gen2-hscif", "renesas,hscif";
788 reg = <0 0xe62c0000 0 96>;
789 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
790 clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>, <&zs_clk>,
791 <&scif_clk>;
792 clock-names = "fck", "brg_int", "scif_clk";
793 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
794 <&dmac1 0x39>, <&dmac1 0x3a>;
795 dma-names = "tx", "rx", "tx", "rx";
796 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
797 status = "disabled";
798 };
799
800 hscif1: serial@e62c8000 {
801 compatible = "renesas,hscif-r8a7790",
802 "renesas,rcar-gen2-hscif", "renesas,hscif";
803 reg = <0 0xe62c8000 0 96>;
804 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
805 clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>, <&zs_clk>,
806 <&scif_clk>;
807 clock-names = "fck", "brg_int", "scif_clk";
808 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
809 <&dmac1 0x4d>, <&dmac1 0x4e>;
810 dma-names = "tx", "rx", "tx", "rx";
811 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
812 status = "disabled";
813 };
814
815 ether: ethernet@ee700000 {
816 compatible = "renesas,ether-r8a7790";
817 reg = <0 0xee700000 0 0x400>;
818 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
819 clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
820 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
821 phy-mode = "rmii";
822 #address-cells = <1>;
823 #size-cells = <0>;
824 status = "disabled";
825 };
826
827 avb: ethernet@e6800000 {
828 compatible = "renesas,etheravb-r8a7790",
829 "renesas,etheravb-rcar-gen2";
830 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
831 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
832 clocks = <&mstp8_clks R8A7790_CLK_ETHERAVB>;
833 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
834 #address-cells = <1>;
835 #size-cells = <0>;
836 status = "disabled";
837 };
838
839 sata0: sata@ee300000 {
840 compatible = "renesas,sata-r8a7790";
841 reg = <0 0xee300000 0 0x2000>;
842 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
843 clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
844 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
845 status = "disabled";
846 };
847
848 sata1: sata@ee500000 {
849 compatible = "renesas,sata-r8a7790";
850 reg = <0 0xee500000 0 0x2000>;
851 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
852 clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
853 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
854 status = "disabled";
855 };
856
857 hsusb: usb@e6590000 {
858 compatible = "renesas,usbhs-r8a7790", "renesas,rcar-gen2-usbhs";
859 reg = <0 0xe6590000 0 0x100>;
860 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
861 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
862 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
863 <&usb_dmac1 0>, <&usb_dmac1 1>;
864 dma-names = "ch0", "ch1", "ch2", "ch3";
865 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
866 renesas,buswait = <4>;
867 phys = <&usb0 1>;
868 phy-names = "usb";
869 status = "disabled";
870 };
871
872 usbphy: usb-phy@e6590100 {
873 compatible = "renesas,usb-phy-r8a7790";
874 reg = <0 0xe6590100 0 0x100>;
875 #address-cells = <1>;
876 #size-cells = <0>;
877 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
878 clock-names = "usbhs";
879 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
880 status = "disabled";
881
882 usb0: usb-channel@0 {
883 reg = <0>;
884 #phy-cells = <1>;
885 };
886 usb2: usb-channel@2 {
887 reg = <2>;
888 #phy-cells = <1>;
889 };
890 };
891
892 vin0: video@e6ef0000 {
893 compatible = "renesas,vin-r8a7790";
894 reg = <0 0xe6ef0000 0 0x1000>;
895 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
896 clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
897 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
898 status = "disabled";
899 };
900
901 vin1: video@e6ef1000 {
902 compatible = "renesas,vin-r8a7790";
903 reg = <0 0xe6ef1000 0 0x1000>;
904 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
905 clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
906 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
907 status = "disabled";
908 };
909
910 vin2: video@e6ef2000 {
911 compatible = "renesas,vin-r8a7790";
912 reg = <0 0xe6ef2000 0 0x1000>;
913 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
914 clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
915 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
916 status = "disabled";
917 };
918
919 vin3: video@e6ef3000 {
920 compatible = "renesas,vin-r8a7790";
921 reg = <0 0xe6ef3000 0 0x1000>;
922 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
923 clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
924 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
925 status = "disabled";
926 };
927
928 vsp1@fe920000 {
929 compatible = "renesas,vsp1";
930 reg = <0 0xfe920000 0 0x8000>;
931 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
932 clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>;
933 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
934
935 renesas,has-sru;
936 renesas,#rpf = <5>;
937 renesas,#uds = <1>;
938 renesas,#wpf = <4>;
939 };
940
941 vsp1@fe928000 {
942 compatible = "renesas,vsp1";
943 reg = <0 0xfe928000 0 0x8000>;
944 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
945 clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>;
946 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
947
948 renesas,has-lut;
949 renesas,has-sru;
950 renesas,#rpf = <5>;
951 renesas,#uds = <3>;
952 renesas,#wpf = <4>;
953 };
954
955 vsp1@fe930000 {
956 compatible = "renesas,vsp1";
957 reg = <0 0xfe930000 0 0x8000>;
958 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
959 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>;
960 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
961
962 renesas,has-lif;
963 renesas,has-lut;
964 renesas,#rpf = <4>;
965 renesas,#uds = <1>;
966 renesas,#wpf = <4>;
967 };
968
969 vsp1@fe938000 {
970 compatible = "renesas,vsp1";
971 reg = <0 0xfe938000 0 0x8000>;
972 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
973 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>;
974 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
975
976 renesas,has-lif;
977 renesas,has-lut;
978 renesas,#rpf = <4>;
979 renesas,#uds = <1>;
980 renesas,#wpf = <4>;
981 };
982
983 du: display@feb00000 {
984 compatible = "renesas,du-r8a7790";
985 reg = <0 0xfeb00000 0 0x70000>,
986 <0 0xfeb90000 0 0x1c>,
987 <0 0xfeb94000 0 0x1c>;
988 reg-names = "du", "lvds.0", "lvds.1";
989 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
990 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
991 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
992 clocks = <&mstp7_clks R8A7790_CLK_DU0>,
993 <&mstp7_clks R8A7790_CLK_DU1>,
994 <&mstp7_clks R8A7790_CLK_DU2>,
995 <&mstp7_clks R8A7790_CLK_LVDS0>,
996 <&mstp7_clks R8A7790_CLK_LVDS1>;
997 clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
998 status = "disabled";
999
1000 ports {
1001 #address-cells = <1>;
1002 #size-cells = <0>;
1003
1004 port@0 {
1005 reg = <0>;
1006 du_out_rgb: endpoint {
1007 };
1008 };
1009 port@1 {
1010 reg = <1>;
1011 du_out_lvds0: endpoint {
1012 };
1013 };
1014 port@2 {
1015 reg = <2>;
1016 du_out_lvds1: endpoint {
1017 };
1018 };
1019 };
1020 };
1021
1022 can0: can@e6e80000 {
1023 compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can";
1024 reg = <0 0xe6e80000 0 0x1000>;
1025 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1026 clocks = <&mstp9_clks R8A7790_CLK_RCAN0>,
1027 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
1028 clock-names = "clkp1", "clkp2", "can_clk";
1029 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1030 status = "disabled";
1031 };
1032
1033 can1: can@e6e88000 {
1034 compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can";
1035 reg = <0 0xe6e88000 0 0x1000>;
1036 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1037 clocks = <&mstp9_clks R8A7790_CLK_RCAN1>,
1038 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
1039 clock-names = "clkp1", "clkp2", "can_clk";
1040 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1041 status = "disabled";
1042 };
1043
1044 jpu: jpeg-codec@fe980000 {
1045 compatible = "renesas,jpu-r8a7790", "renesas,rcar-gen2-jpu";
1046 reg = <0 0xfe980000 0 0x10300>;
1047 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
1048 clocks = <&mstp1_clks R8A7790_CLK_JPU>;
1049 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1050 };
1051
1052 clocks {
1053 #address-cells = <2>;
1054 #size-cells = <2>;
1055 ranges;
1056
1057 /* External root clock */
1058 extal_clk: extal {
1059 compatible = "fixed-clock";
1060 #clock-cells = <0>;
1061 /* This value must be overriden by the board. */
1062 clock-frequency = <0>;
1063 };
1064
1065 /* External PCIe clock - can be overridden by the board */
1066 pcie_bus_clk: pcie_bus {
1067 compatible = "fixed-clock";
1068 #clock-cells = <0>;
1069 clock-frequency = <0>;
1070 };
1071
1072 /*
1073 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
1074 * default. Boards that provide audio clocks should override them.
1075 */
1076 audio_clk_a: audio_clk_a {
1077 compatible = "fixed-clock";
1078 #clock-cells = <0>;
1079 clock-frequency = <0>;
1080 };
1081 audio_clk_b: audio_clk_b {
1082 compatible = "fixed-clock";
1083 #clock-cells = <0>;
1084 clock-frequency = <0>;
1085 };
1086 audio_clk_c: audio_clk_c {
1087 compatible = "fixed-clock";
1088 #clock-cells = <0>;
1089 clock-frequency = <0>;
1090 };
1091
1092 /* External SCIF clock */
1093 scif_clk: scif {
1094 compatible = "fixed-clock";
1095 #clock-cells = <0>;
1096 /* This value must be overridden by the board. */
1097 clock-frequency = <0>;
1098 };
1099
1100 /* External USB clock - can be overridden by the board */
1101 usb_extal_clk: usb_extal {
1102 compatible = "fixed-clock";
1103 #clock-cells = <0>;
1104 clock-frequency = <48000000>;
1105 };
1106
1107 /* External CAN clock */
1108 can_clk: can_clk {
1109 compatible = "fixed-clock";
1110 #clock-cells = <0>;
1111 /* This value must be overridden by the board. */
1112 clock-frequency = <0>;
1113 };
1114
1115 /* Special CPG clocks */
1116 cpg_clocks: cpg_clocks@e6150000 {
1117 compatible = "renesas,r8a7790-cpg-clocks",
1118 "renesas,rcar-gen2-cpg-clocks";
1119 reg = <0 0xe6150000 0 0x1000>;
1120 clocks = <&extal_clk &usb_extal_clk>;
1121 #clock-cells = <1>;
1122 clock-output-names = "main", "pll0", "pll1", "pll3",
1123 "lb", "qspi", "sdh", "sd0", "sd1",
1124 "z", "rcan", "adsp";
1125 #power-domain-cells = <0>;
1126 };
1127
1128 /* Variable factor clocks */
1129 sd2_clk: sd2@e6150078 {
1130 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1131 reg = <0 0xe6150078 0 4>;
1132 clocks = <&pll1_div2_clk>;
1133 #clock-cells = <0>;
1134 };
1135 sd3_clk: sd3@e615026c {
1136 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1137 reg = <0 0xe615026c 0 4>;
1138 clocks = <&pll1_div2_clk>;
1139 #clock-cells = <0>;
1140 };
1141 mmc0_clk: mmc0@e6150240 {
1142 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1143 reg = <0 0xe6150240 0 4>;
1144 clocks = <&pll1_div2_clk>;
1145 #clock-cells = <0>;
1146 };
1147 mmc1_clk: mmc1@e6150244 {
1148 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1149 reg = <0 0xe6150244 0 4>;
1150 clocks = <&pll1_div2_clk>;
1151 #clock-cells = <0>;
1152 };
1153 ssp_clk: ssp@e6150248 {
1154 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1155 reg = <0 0xe6150248 0 4>;
1156 clocks = <&pll1_div2_clk>;
1157 #clock-cells = <0>;
1158 };
1159 ssprs_clk: ssprs@e615024c {
1160 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1161 reg = <0 0xe615024c 0 4>;
1162 clocks = <&pll1_div2_clk>;
1163 #clock-cells = <0>;
1164 };
1165
1166 /* Fixed factor clocks */
1167 pll1_div2_clk: pll1_div2 {
1168 compatible = "fixed-factor-clock";
1169 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1170 #clock-cells = <0>;
1171 clock-div = <2>;
1172 clock-mult = <1>;
1173 };
1174 z2_clk: z2 {
1175 compatible = "fixed-factor-clock";
1176 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1177 #clock-cells = <0>;
1178 clock-div = <2>;
1179 clock-mult = <1>;
1180 };
1181 zg_clk: zg {
1182 compatible = "fixed-factor-clock";
1183 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1184 #clock-cells = <0>;
1185 clock-div = <3>;
1186 clock-mult = <1>;
1187 };
1188 zx_clk: zx {
1189 compatible = "fixed-factor-clock";
1190 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1191 #clock-cells = <0>;
1192 clock-div = <3>;
1193 clock-mult = <1>;
1194 };
1195 zs_clk: zs {
1196 compatible = "fixed-factor-clock";
1197 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1198 #clock-cells = <0>;
1199 clock-div = <6>;
1200 clock-mult = <1>;
1201 };
1202 hp_clk: hp {
1203 compatible = "fixed-factor-clock";
1204 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1205 #clock-cells = <0>;
1206 clock-div = <12>;
1207 clock-mult = <1>;
1208 };
1209 i_clk: i {
1210 compatible = "fixed-factor-clock";
1211 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1212 #clock-cells = <0>;
1213 clock-div = <2>;
1214 clock-mult = <1>;
1215 };
1216 b_clk: b {
1217 compatible = "fixed-factor-clock";
1218 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1219 #clock-cells = <0>;
1220 clock-div = <12>;
1221 clock-mult = <1>;
1222 };
1223 p_clk: p {
1224 compatible = "fixed-factor-clock";
1225 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1226 #clock-cells = <0>;
1227 clock-div = <24>;
1228 clock-mult = <1>;
1229 };
1230 cl_clk: cl {
1231 compatible = "fixed-factor-clock";
1232 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1233 #clock-cells = <0>;
1234 clock-div = <48>;
1235 clock-mult = <1>;
1236 };
1237 m2_clk: m2 {
1238 compatible = "fixed-factor-clock";
1239 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1240 #clock-cells = <0>;
1241 clock-div = <8>;
1242 clock-mult = <1>;
1243 };
1244 imp_clk: imp {
1245 compatible = "fixed-factor-clock";
1246 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1247 #clock-cells = <0>;
1248 clock-div = <4>;
1249 clock-mult = <1>;
1250 };
1251 rclk_clk: rclk {
1252 compatible = "fixed-factor-clock";
1253 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1254 #clock-cells = <0>;
1255 clock-div = <(48 * 1024)>;
1256 clock-mult = <1>;
1257 };
1258 oscclk_clk: oscclk {
1259 compatible = "fixed-factor-clock";
1260 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1261 #clock-cells = <0>;
1262 clock-div = <(12 * 1024)>;
1263 clock-mult = <1>;
1264 };
1265 zb3_clk: zb3 {
1266 compatible = "fixed-factor-clock";
1267 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1268 #clock-cells = <0>;
1269 clock-div = <4>;
1270 clock-mult = <1>;
1271 };
1272 zb3d2_clk: zb3d2 {
1273 compatible = "fixed-factor-clock";
1274 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1275 #clock-cells = <0>;
1276 clock-div = <8>;
1277 clock-mult = <1>;
1278 };
1279 ddr_clk: ddr {
1280 compatible = "fixed-factor-clock";
1281 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1282 #clock-cells = <0>;
1283 clock-div = <8>;
1284 clock-mult = <1>;
1285 };
1286 mp_clk: mp {
1287 compatible = "fixed-factor-clock";
1288 clocks = <&pll1_div2_clk>;
1289 #clock-cells = <0>;
1290 clock-div = <15>;
1291 clock-mult = <1>;
1292 };
1293 cp_clk: cp {
1294 compatible = "fixed-factor-clock";
1295 clocks = <&extal_clk>;
1296 #clock-cells = <0>;
1297 clock-div = <2>;
1298 clock-mult = <1>;
1299 };
1300
1301 /* Gate clocks */
1302 mstp0_clks: mstp0_clks@e6150130 {
1303 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1304 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1305 clocks = <&mp_clk>;
1306 #clock-cells = <1>;
1307 clock-indices = <R8A7790_CLK_MSIOF0>;
1308 clock-output-names = "msiof0";
1309 };
1310 mstp1_clks: mstp1_clks@e6150134 {
1311 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1312 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1313 clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&m2_clk>,
1314 <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, <&zs_clk>,
1315 <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
1316 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
1317 #clock-cells = <1>;
1318 clock-indices = <
1319 R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1
1320 R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1
1321 R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC
1322 R8A7790_CLK_FDP1_2 R8A7790_CLK_FDP1_1 R8A7790_CLK_FDP1_0
1323 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 R8A7790_CLK_CMT0
1324 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 R8A7790_CLK_VSP1_DU0
1325 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
1326 >;
1327 clock-output-names =
1328 "vcp1", "vcp0", "vpc1", "vpc0", "jpu", "ssp1",
1329 "tmu1", "3dg", "2ddmac", "fdp1-2", "fdp1-1",
1330 "fdp1-0", "tmu3", "tmu2", "cmt0", "tmu0",
1331 "vsp1-du1", "vsp1-du0", "vsp1-rt", "vsp1-sy";
1332 };
1333 mstp2_clks: mstp2_clks@e6150138 {
1334 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1335 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1336 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1337 <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>,
1338 <&zs_clk>;
1339 #clock-cells = <1>;
1340 clock-indices = <
1341 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
1342 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
1343 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
1344 R8A7790_CLK_SYS_DMAC1 R8A7790_CLK_SYS_DMAC0
1345 >;
1346 clock-output-names =
1347 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
1348 "scifb1", "msiof1", "msiof3", "scifb2",
1349 "sys-dmac1", "sys-dmac0";
1350 };
1351 mstp3_clks: mstp3_clks@e615013c {
1352 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1353 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1354 clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&p_clk>, <&sd3_clk>,
1355 <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
1356 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1357 <&hp_clk>, <&hp_clk>;
1358 #clock-cells = <1>;
1359 clock-indices = <
1360 R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SCIF2 R8A7790_CLK_SDHI3
1361 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
1362 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
1363 R8A7790_CLK_USBDMAC0 R8A7790_CLK_USBDMAC1
1364 >;
1365 clock-output-names =
1366 "iic2", "tpu0", "mmcif1", "scif2", "sdhi3",
1367 "sdhi2", "sdhi1", "sdhi0", "mmcif0",
1368 "iic0", "pciec", "iic1", "ssusb", "cmt1",
1369 "usbdmac0", "usbdmac1";
1370 };
1371 mstp4_clks: mstp4_clks@e6150140 {
1372 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1373 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1374 clocks = <&cp_clk>;
1375 #clock-cells = <1>;
1376 clock-indices = <R8A7790_CLK_IRQC>;
1377 clock-output-names = "irqc";
1378 };
1379 mstp5_clks: mstp5_clks@e6150144 {
1380 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1381 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1382 clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7790_CLK_ADSP>,
1383 <&extal_clk>, <&p_clk>;
1384 #clock-cells = <1>;
1385 clock-indices = <
1386 R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1
1387 R8A7790_CLK_ADSP_MOD R8A7790_CLK_THERMAL
1388 R8A7790_CLK_PWM
1389 >;
1390 clock-output-names = "audmac0", "audmac1", "adsp_mod",
1391 "thermal", "pwm";
1392 };
1393 mstp7_clks: mstp7_clks@e615014c {
1394 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1395 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1396 clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1397 <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
1398 <&zx_clk>;
1399 #clock-cells = <1>;
1400 clock-indices = <
1401 R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
1402 R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
1403 R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
1404 R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0
1405 >;
1406 clock-output-names =
1407 "ehci", "hsusb", "hscif1", "hscif0", "scif1",
1408 "scif0", "du2", "du1", "du0", "lvds1", "lvds0";
1409 };
1410 mstp8_clks: mstp8_clks@e6150990 {
1411 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1412 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1413 clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
1414 <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>,
1415 <&zs_clk>;
1416 #clock-cells = <1>;
1417 clock-indices = <
1418 R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2
1419 R8A7790_CLK_VIN1 R8A7790_CLK_VIN0
1420 R8A7790_CLK_ETHERAVB R8A7790_CLK_ETHER
1421 R8A7790_CLK_SATA1 R8A7790_CLK_SATA0
1422 >;
1423 clock-output-names =
1424 "mlb", "vin3", "vin2", "vin1", "vin0",
1425 "etheravb", "ether", "sata1", "sata0";
1426 };
1427 mstp9_clks: mstp9_clks@e6150994 {
1428 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1429 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1430 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>,
1431 <&cp_clk>, <&cp_clk>, <&cp_clk>,
1432 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>,
1433 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
1434 #clock-cells = <1>;
1435 clock-indices = <
1436 R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3
1437 R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0
1438 R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS
1439 R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0
1440 >;
1441 clock-output-names =
1442 "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
1443 "rcan1", "rcan0", "qspi_mod", "iic3",
1444 "i2c3", "i2c2", "i2c1", "i2c0";
1445 };
1446 mstp10_clks: mstp10_clks@e6150998 {
1447 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1448 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1449 clocks = <&p_clk>,
1450 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1451 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1452 <&p_clk>,
1453 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1454 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1455 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1456 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1457 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1458 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1459 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>;
1460
1461 #clock-cells = <1>;
1462 clock-indices = <
1463 R8A7790_CLK_SSI_ALL
1464 R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5
1465 R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0
1466 R8A7790_CLK_SCU_ALL
1467 R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0
1468 R8A7790_CLK_SCU_CTU1_MIX1 R8A7790_CLK_SCU_CTU0_MIX0
1469 R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5
1470 R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0
1471 >;
1472 clock-output-names =
1473 "ssi-all",
1474 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1475 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1476 "scu-all",
1477 "scu-dvc1", "scu-dvc0",
1478 "scu-ctu1-mix1", "scu-ctu0-mix0",
1479 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1480 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1481 };
1482 };
1483
1484 sysc: system-controller@e6180000 {
1485 compatible = "renesas,r8a7790-sysc";
1486 reg = <0 0xe6180000 0 0x0200>;
1487 #power-domain-cells = <1>;
1488 };
1489
1490 qspi: spi@e6b10000 {
1491 compatible = "renesas,qspi-r8a7790", "renesas,qspi";
1492 reg = <0 0xe6b10000 0 0x2c>;
1493 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
1494 clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
1495 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
1496 <&dmac1 0x17>, <&dmac1 0x18>;
1497 dma-names = "tx", "rx", "tx", "rx";
1498 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1499 num-cs = <1>;
1500 #address-cells = <1>;
1501 #size-cells = <0>;
1502 status = "disabled";
1503 };
1504
1505 msiof0: spi@e6e20000 {
1506 compatible = "renesas,msiof-r8a7790";
1507 reg = <0 0xe6e20000 0 0x0064>;
1508 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1509 clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
1510 dmas = <&dmac0 0x51>, <&dmac0 0x52>,
1511 <&dmac1 0x51>, <&dmac1 0x52>;
1512 dma-names = "tx", "rx", "tx", "rx";
1513 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1514 #address-cells = <1>;
1515 #size-cells = <0>;
1516 status = "disabled";
1517 };
1518
1519 msiof1: spi@e6e10000 {
1520 compatible = "renesas,msiof-r8a7790";
1521 reg = <0 0xe6e10000 0 0x0064>;
1522 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1523 clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
1524 dmas = <&dmac0 0x55>, <&dmac0 0x56>,
1525 <&dmac1 0x55>, <&dmac1 0x56>;
1526 dma-names = "tx", "rx", "tx", "rx";
1527 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1528 #address-cells = <1>;
1529 #size-cells = <0>;
1530 status = "disabled";
1531 };
1532
1533 msiof2: spi@e6e00000 {
1534 compatible = "renesas,msiof-r8a7790";
1535 reg = <0 0xe6e00000 0 0x0064>;
1536 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1537 clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
1538 dmas = <&dmac0 0x41>, <&dmac0 0x42>,
1539 <&dmac1 0x41>, <&dmac1 0x42>;
1540 dma-names = "tx", "rx", "tx", "rx";
1541 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1542 #address-cells = <1>;
1543 #size-cells = <0>;
1544 status = "disabled";
1545 };
1546
1547 msiof3: spi@e6c90000 {
1548 compatible = "renesas,msiof-r8a7790";
1549 reg = <0 0xe6c90000 0 0x0064>;
1550 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1551 clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
1552 dmas = <&dmac0 0x45>, <&dmac0 0x46>,
1553 <&dmac1 0x45>, <&dmac1 0x46>;
1554 dma-names = "tx", "rx", "tx", "rx";
1555 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1556 #address-cells = <1>;
1557 #size-cells = <0>;
1558 status = "disabled";
1559 };
1560
1561 xhci: usb@ee000000 {
1562 compatible = "renesas,xhci-r8a7790", "renesas,rcar-gen2-xhci";
1563 reg = <0 0xee000000 0 0xc00>;
1564 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1565 clocks = <&mstp3_clks R8A7790_CLK_SSUSB>;
1566 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1567 phys = <&usb2 1>;
1568 phy-names = "usb";
1569 status = "disabled";
1570 };
1571
1572 pci0: pci@ee090000 {
1573 compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
1574 device_type = "pci";
1575 reg = <0 0xee090000 0 0xc00>,
1576 <0 0xee080000 0 0x1100>;
1577 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1578 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1579 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1580 status = "disabled";
1581
1582 bus-range = <0 0>;
1583 #address-cells = <3>;
1584 #size-cells = <2>;
1585 #interrupt-cells = <1>;
1586 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1587 interrupt-map-mask = <0xff00 0 0 0x7>;
1588 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1589 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1590 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1591
1592 usb@0,1 {
1593 reg = <0x800 0 0 0 0>;
1594 device_type = "pci";
1595 phys = <&usb0 0>;
1596 phy-names = "usb";
1597 };
1598
1599 usb@0,2 {
1600 reg = <0x1000 0 0 0 0>;
1601 device_type = "pci";
1602 phys = <&usb0 0>;
1603 phy-names = "usb";
1604 };
1605 };
1606
1607 pci1: pci@ee0b0000 {
1608 compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
1609 device_type = "pci";
1610 reg = <0 0xee0b0000 0 0xc00>,
1611 <0 0xee0a0000 0 0x1100>;
1612 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1613 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1614 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1615 status = "disabled";
1616
1617 bus-range = <1 1>;
1618 #address-cells = <3>;
1619 #size-cells = <2>;
1620 #interrupt-cells = <1>;
1621 ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
1622 interrupt-map-mask = <0xff00 0 0 0x7>;
1623 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
1624 0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
1625 0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1626 };
1627
1628 pci2: pci@ee0d0000 {
1629 compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
1630 device_type = "pci";
1631 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1632 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1633 reg = <0 0xee0d0000 0 0xc00>,
1634 <0 0xee0c0000 0 0x1100>;
1635 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1636 status = "disabled";
1637
1638 bus-range = <2 2>;
1639 #address-cells = <3>;
1640 #size-cells = <2>;
1641 #interrupt-cells = <1>;
1642 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1643 interrupt-map-mask = <0xff00 0 0 0x7>;
1644 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1645 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1646 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1647
1648 usb@0,1 {
1649 reg = <0x800 0 0 0 0>;
1650 device_type = "pci";
1651 phys = <&usb2 0>;
1652 phy-names = "usb";
1653 };
1654
1655 usb@0,2 {
1656 reg = <0x1000 0 0 0 0>;
1657 device_type = "pci";
1658 phys = <&usb2 0>;
1659 phy-names = "usb";
1660 };
1661 };
1662
1663 pciec: pcie@fe000000 {
1664 compatible = "renesas,pcie-r8a7790", "renesas,pcie-rcar-gen2";
1665 reg = <0 0xfe000000 0 0x80000>;
1666 #address-cells = <3>;
1667 #size-cells = <2>;
1668 bus-range = <0x00 0xff>;
1669 device_type = "pci";
1670 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1671 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1672 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1673 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1674 /* Map all possible DDR as inbound ranges */
1675 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1676 0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
1677 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1678 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1679 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1680 #interrupt-cells = <1>;
1681 interrupt-map-mask = <0 0 0 0>;
1682 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1683 clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>;
1684 clock-names = "pcie", "pcie_bus";
1685 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1686 status = "disabled";
1687 };
1688
1689 rcar_sound: sound@ec500000 {
1690 /*
1691 * #sound-dai-cells is required
1692 *
1693 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1694 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1695 */
1696 compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2";
1697 reg = <0 0xec500000 0 0x1000>, /* SCU */
1698 <0 0xec5a0000 0 0x100>, /* ADG */
1699 <0 0xec540000 0 0x1000>, /* SSIU */
1700 <0 0xec541000 0 0x280>, /* SSI */
1701 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
1702 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1703
1704 clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>,
1705 <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>,
1706 <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>,
1707 <&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>,
1708 <&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>,
1709 <&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>,
1710 <&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>,
1711 <&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>,
1712 <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>,
1713 <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>,
1714 <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>,
1715 <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>,
1716 <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>,
1717 <&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>,
1718 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1719 clock-names = "ssi-all",
1720 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1721 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1722 "src.9", "src.8", "src.7", "src.6", "src.5",
1723 "src.4", "src.3", "src.2", "src.1", "src.0",
1724 "ctu.0", "ctu.1",
1725 "mix.0", "mix.1",
1726 "dvc.0", "dvc.1",
1727 "clk_a", "clk_b", "clk_c", "clk_i";
1728 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1729
1730 status = "disabled";
1731
1732 rcar_sound,dvc {
1733 dvc0: dvc-0 {
1734 dmas = <&audma0 0xbc>;
1735 dma-names = "tx";
1736 };
1737 dvc1: dvc-1 {
1738 dmas = <&audma0 0xbe>;
1739 dma-names = "tx";
1740 };
1741 };
1742
1743 rcar_sound,mix {
1744 mix0: mix-0 { };
1745 mix1: mix-1 { };
1746 };
1747
1748 rcar_sound,ctu {
1749 ctu00: ctu-0 { };
1750 ctu01: ctu-1 { };
1751 ctu02: ctu-2 { };
1752 ctu03: ctu-3 { };
1753 ctu10: ctu-4 { };
1754 ctu11: ctu-5 { };
1755 ctu12: ctu-6 { };
1756 ctu13: ctu-7 { };
1757 };
1758
1759 rcar_sound,src {
1760 src0: src-0 {
1761 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1762 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1763 dma-names = "rx", "tx";
1764 };
1765 src1: src-1 {
1766 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1767 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1768 dma-names = "rx", "tx";
1769 };
1770 src2: src-2 {
1771 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1772 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1773 dma-names = "rx", "tx";
1774 };
1775 src3: src-3 {
1776 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1777 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1778 dma-names = "rx", "tx";
1779 };
1780 src4: src-4 {
1781 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1782 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1783 dma-names = "rx", "tx";
1784 };
1785 src5: src-5 {
1786 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1787 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1788 dma-names = "rx", "tx";
1789 };
1790 src6: src-6 {
1791 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1792 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1793 dma-names = "rx", "tx";
1794 };
1795 src7: src-7 {
1796 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1797 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1798 dma-names = "rx", "tx";
1799 };
1800 src8: src-8 {
1801 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1802 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1803 dma-names = "rx", "tx";
1804 };
1805 src9: src-9 {
1806 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1807 dmas = <&audma0 0x97>, <&audma1 0xba>;
1808 dma-names = "rx", "tx";
1809 };
1810 };
1811
1812 rcar_sound,ssi {
1813 ssi0: ssi-0 {
1814 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1815 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1816 dma-names = "rx", "tx", "rxu", "txu";
1817 };
1818 ssi1: ssi-1 {
1819 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1820 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1821 dma-names = "rx", "tx", "rxu", "txu";
1822 };
1823 ssi2: ssi-2 {
1824 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1825 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1826 dma-names = "rx", "tx", "rxu", "txu";
1827 };
1828 ssi3: ssi-3 {
1829 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1830 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1831 dma-names = "rx", "tx", "rxu", "txu";
1832 };
1833 ssi4: ssi-4 {
1834 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1835 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1836 dma-names = "rx", "tx", "rxu", "txu";
1837 };
1838 ssi5: ssi-5 {
1839 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1840 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1841 dma-names = "rx", "tx", "rxu", "txu";
1842 };
1843 ssi6: ssi-6 {
1844 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1845 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1846 dma-names = "rx", "tx", "rxu", "txu";
1847 };
1848 ssi7: ssi-7 {
1849 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1850 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1851 dma-names = "rx", "tx", "rxu", "txu";
1852 };
1853 ssi8: ssi-8 {
1854 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1855 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1856 dma-names = "rx", "tx", "rxu", "txu";
1857 };
1858 ssi9: ssi-9 {
1859 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1860 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1861 dma-names = "rx", "tx", "rxu", "txu";
1862 };
1863 };
1864 };
1865
1866 ipmmu_sy0: mmu@e6280000 {
1867 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1868 reg = <0 0xe6280000 0 0x1000>;
1869 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1870 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1871 #iommu-cells = <1>;
1872 status = "disabled";
1873 };
1874
1875 ipmmu_sy1: mmu@e6290000 {
1876 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1877 reg = <0 0xe6290000 0 0x1000>;
1878 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1879 #iommu-cells = <1>;
1880 status = "disabled";
1881 };
1882
1883 ipmmu_ds: mmu@e6740000 {
1884 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1885 reg = <0 0xe6740000 0 0x1000>;
1886 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1887 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1888 #iommu-cells = <1>;
1889 status = "disabled";
1890 };
1891
1892 ipmmu_mp: mmu@ec680000 {
1893 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1894 reg = <0 0xec680000 0 0x1000>;
1895 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1896 #iommu-cells = <1>;
1897 status = "disabled";
1898 };
1899
1900 ipmmu_mx: mmu@fe951000 {
1901 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1902 reg = <0 0xfe951000 0 0x1000>;
1903 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1904 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1905 #iommu-cells = <1>;
1906 status = "disabled";
1907 };
1908
1909 ipmmu_rt: mmu@ffc80000 {
1910 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1911 reg = <0 0xffc80000 0 0x1000>;
1912 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1913 #iommu-cells = <1>;
1914 status = "disabled";
1915 };
1916 };
Linux kernel - Deliverables
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