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ARM: shmobile: r8a7790: Fix HSUSB clock to hp_clk from mp_clk
[deliverable/linux.git] / arch / arm / boot / dts / r8a7790.dtsi
1 /*
2 * Device Tree Source for the r8a7790 SoC
3 *
4 * Copyright (C) 2015 Renesas Electronics Corporation
5 * Copyright (C) 2013-2014 Renesas Solutions Corp.
6 * Copyright (C) 2014 Cogent Embedded Inc.
7 *
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
11 */
12
13 #include <dt-bindings/clock/r8a7790-clock.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
16
17 / {
18 compatible = "renesas,r8a7790";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
22
23 aliases {
24 i2c0 = &i2c0;
25 i2c1 = &i2c1;
26 i2c2 = &i2c2;
27 i2c3 = &i2c3;
28 i2c4 = &iic0;
29 i2c5 = &iic1;
30 i2c6 = &iic2;
31 i2c7 = &iic3;
32 spi0 = &qspi;
33 spi1 = &msiof0;
34 spi2 = &msiof1;
35 spi3 = &msiof2;
36 spi4 = &msiof3;
37 vin0 = &vin0;
38 vin1 = &vin1;
39 vin2 = &vin2;
40 vin3 = &vin3;
41 };
42
43 cpus {
44 #address-cells = <1>;
45 #size-cells = <0>;
46
47 cpu0: cpu@0 {
48 device_type = "cpu";
49 compatible = "arm,cortex-a15";
50 reg = <0>;
51 clock-frequency = <1300000000>;
52 voltage-tolerance = <1>; /* 1% */
53 clocks = <&cpg_clocks R8A7790_CLK_Z>;
54 clock-latency = <300000>; /* 300 us */
55
56 /* kHz - uV - OPPs unknown yet */
57 operating-points = <1400000 1000000>,
58 <1225000 1000000>,
59 <1050000 1000000>,
60 < 875000 1000000>,
61 < 700000 1000000>,
62 < 350000 1000000>;
63 };
64
65 cpu1: cpu@1 {
66 device_type = "cpu";
67 compatible = "arm,cortex-a15";
68 reg = <1>;
69 clock-frequency = <1300000000>;
70 };
71
72 cpu2: cpu@2 {
73 device_type = "cpu";
74 compatible = "arm,cortex-a15";
75 reg = <2>;
76 clock-frequency = <1300000000>;
77 };
78
79 cpu3: cpu@3 {
80 device_type = "cpu";
81 compatible = "arm,cortex-a15";
82 reg = <3>;
83 clock-frequency = <1300000000>;
84 };
85
86 cpu4: cpu@4 {
87 device_type = "cpu";
88 compatible = "arm,cortex-a7";
89 reg = <0x100>;
90 clock-frequency = <780000000>;
91 };
92
93 cpu5: cpu@5 {
94 device_type = "cpu";
95 compatible = "arm,cortex-a7";
96 reg = <0x101>;
97 clock-frequency = <780000000>;
98 };
99
100 cpu6: cpu@6 {
101 device_type = "cpu";
102 compatible = "arm,cortex-a7";
103 reg = <0x102>;
104 clock-frequency = <780000000>;
105 };
106
107 cpu7: cpu@7 {
108 device_type = "cpu";
109 compatible = "arm,cortex-a7";
110 reg = <0x103>;
111 clock-frequency = <780000000>;
112 };
113 };
114
115 gic: interrupt-controller@f1001000 {
116 compatible = "arm,cortex-a15-gic";
117 #interrupt-cells = <3>;
118 #address-cells = <0>;
119 interrupt-controller;
120 reg = <0 0xf1001000 0 0x1000>,
121 <0 0xf1002000 0 0x1000>,
122 <0 0xf1004000 0 0x2000>,
123 <0 0xf1006000 0 0x2000>;
124 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
125 };
126
127 gpio0: gpio@e6050000 {
128 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
129 reg = <0 0xe6050000 0 0x50>;
130 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
131 #gpio-cells = <2>;
132 gpio-controller;
133 gpio-ranges = <&pfc 0 0 32>;
134 #interrupt-cells = <2>;
135 interrupt-controller;
136 clocks = <&mstp9_clks R8A7790_CLK_GPIO0>;
137 };
138
139 gpio1: gpio@e6051000 {
140 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
141 reg = <0 0xe6051000 0 0x50>;
142 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
143 #gpio-cells = <2>;
144 gpio-controller;
145 gpio-ranges = <&pfc 0 32 32>;
146 #interrupt-cells = <2>;
147 interrupt-controller;
148 clocks = <&mstp9_clks R8A7790_CLK_GPIO1>;
149 };
150
151 gpio2: gpio@e6052000 {
152 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
153 reg = <0 0xe6052000 0 0x50>;
154 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
155 #gpio-cells = <2>;
156 gpio-controller;
157 gpio-ranges = <&pfc 0 64 32>;
158 #interrupt-cells = <2>;
159 interrupt-controller;
160 clocks = <&mstp9_clks R8A7790_CLK_GPIO2>;
161 };
162
163 gpio3: gpio@e6053000 {
164 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
165 reg = <0 0xe6053000 0 0x50>;
166 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
167 #gpio-cells = <2>;
168 gpio-controller;
169 gpio-ranges = <&pfc 0 96 32>;
170 #interrupt-cells = <2>;
171 interrupt-controller;
172 clocks = <&mstp9_clks R8A7790_CLK_GPIO3>;
173 };
174
175 gpio4: gpio@e6054000 {
176 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
177 reg = <0 0xe6054000 0 0x50>;
178 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
179 #gpio-cells = <2>;
180 gpio-controller;
181 gpio-ranges = <&pfc 0 128 32>;
182 #interrupt-cells = <2>;
183 interrupt-controller;
184 clocks = <&mstp9_clks R8A7790_CLK_GPIO4>;
185 };
186
187 gpio5: gpio@e6055000 {
188 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
189 reg = <0 0xe6055000 0 0x50>;
190 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
191 #gpio-cells = <2>;
192 gpio-controller;
193 gpio-ranges = <&pfc 0 160 32>;
194 #interrupt-cells = <2>;
195 interrupt-controller;
196 clocks = <&mstp9_clks R8A7790_CLK_GPIO5>;
197 };
198
199 thermal@e61f0000 {
200 compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
201 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
202 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
203 clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
204 };
205
206 timer {
207 compatible = "arm,armv7-timer";
208 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
209 <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
210 <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
211 <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
212 };
213
214 cmt0: timer@ffca0000 {
215 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
216 reg = <0 0xffca0000 0 0x1004>;
217 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
218 <0 143 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
220 clock-names = "fck";
221
222 renesas,channels-mask = <0x60>;
223
224 status = "disabled";
225 };
226
227 cmt1: timer@e6130000 {
228 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
229 reg = <0 0xe6130000 0 0x1004>;
230 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
231 <0 121 IRQ_TYPE_LEVEL_HIGH>,
232 <0 122 IRQ_TYPE_LEVEL_HIGH>,
233 <0 123 IRQ_TYPE_LEVEL_HIGH>,
234 <0 124 IRQ_TYPE_LEVEL_HIGH>,
235 <0 125 IRQ_TYPE_LEVEL_HIGH>,
236 <0 126 IRQ_TYPE_LEVEL_HIGH>,
237 <0 127 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
239 clock-names = "fck";
240
241 renesas,channels-mask = <0xff>;
242
243 status = "disabled";
244 };
245
246 irqc0: interrupt-controller@e61c0000 {
247 compatible = "renesas,irqc-r8a7790", "renesas,irqc";
248 #interrupt-cells = <2>;
249 interrupt-controller;
250 reg = <0 0xe61c0000 0 0x200>;
251 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
252 <0 1 IRQ_TYPE_LEVEL_HIGH>,
253 <0 2 IRQ_TYPE_LEVEL_HIGH>,
254 <0 3 IRQ_TYPE_LEVEL_HIGH>;
255 };
256
257 dmac0: dma-controller@e6700000 {
258 compatible = "renesas,rcar-dmac";
259 reg = <0 0xe6700000 0 0x20000>;
260 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
261 0 200 IRQ_TYPE_LEVEL_HIGH
262 0 201 IRQ_TYPE_LEVEL_HIGH
263 0 202 IRQ_TYPE_LEVEL_HIGH
264 0 203 IRQ_TYPE_LEVEL_HIGH
265 0 204 IRQ_TYPE_LEVEL_HIGH
266 0 205 IRQ_TYPE_LEVEL_HIGH
267 0 206 IRQ_TYPE_LEVEL_HIGH
268 0 207 IRQ_TYPE_LEVEL_HIGH
269 0 208 IRQ_TYPE_LEVEL_HIGH
270 0 209 IRQ_TYPE_LEVEL_HIGH
271 0 210 IRQ_TYPE_LEVEL_HIGH
272 0 211 IRQ_TYPE_LEVEL_HIGH
273 0 212 IRQ_TYPE_LEVEL_HIGH
274 0 213 IRQ_TYPE_LEVEL_HIGH
275 0 214 IRQ_TYPE_LEVEL_HIGH>;
276 interrupt-names = "error",
277 "ch0", "ch1", "ch2", "ch3",
278 "ch4", "ch5", "ch6", "ch7",
279 "ch8", "ch9", "ch10", "ch11",
280 "ch12", "ch13", "ch14";
281 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
282 clock-names = "fck";
283 #dma-cells = <1>;
284 dma-channels = <15>;
285 };
286
287 dmac1: dma-controller@e6720000 {
288 compatible = "renesas,rcar-dmac";
289 reg = <0 0xe6720000 0 0x20000>;
290 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
291 0 216 IRQ_TYPE_LEVEL_HIGH
292 0 217 IRQ_TYPE_LEVEL_HIGH
293 0 218 IRQ_TYPE_LEVEL_HIGH
294 0 219 IRQ_TYPE_LEVEL_HIGH
295 0 308 IRQ_TYPE_LEVEL_HIGH
296 0 309 IRQ_TYPE_LEVEL_HIGH
297 0 310 IRQ_TYPE_LEVEL_HIGH
298 0 311 IRQ_TYPE_LEVEL_HIGH
299 0 312 IRQ_TYPE_LEVEL_HIGH
300 0 313 IRQ_TYPE_LEVEL_HIGH
301 0 314 IRQ_TYPE_LEVEL_HIGH
302 0 315 IRQ_TYPE_LEVEL_HIGH
303 0 316 IRQ_TYPE_LEVEL_HIGH
304 0 317 IRQ_TYPE_LEVEL_HIGH
305 0 318 IRQ_TYPE_LEVEL_HIGH>;
306 interrupt-names = "error",
307 "ch0", "ch1", "ch2", "ch3",
308 "ch4", "ch5", "ch6", "ch7",
309 "ch8", "ch9", "ch10", "ch11",
310 "ch12", "ch13", "ch14";
311 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
312 clock-names = "fck";
313 #dma-cells = <1>;
314 dma-channels = <15>;
315 };
316
317 audma0: dma-controller@ec700000 {
318 compatible = "renesas,rcar-dmac";
319 reg = <0 0xec700000 0 0x10000>;
320 interrupts = <0 346 IRQ_TYPE_LEVEL_HIGH
321 0 320 IRQ_TYPE_LEVEL_HIGH
322 0 321 IRQ_TYPE_LEVEL_HIGH
323 0 322 IRQ_TYPE_LEVEL_HIGH
324 0 323 IRQ_TYPE_LEVEL_HIGH
325 0 324 IRQ_TYPE_LEVEL_HIGH
326 0 325 IRQ_TYPE_LEVEL_HIGH
327 0 326 IRQ_TYPE_LEVEL_HIGH
328 0 327 IRQ_TYPE_LEVEL_HIGH
329 0 328 IRQ_TYPE_LEVEL_HIGH
330 0 329 IRQ_TYPE_LEVEL_HIGH
331 0 330 IRQ_TYPE_LEVEL_HIGH
332 0 331 IRQ_TYPE_LEVEL_HIGH
333 0 332 IRQ_TYPE_LEVEL_HIGH>;
334 interrupt-names = "error",
335 "ch0", "ch1", "ch2", "ch3",
336 "ch4", "ch5", "ch6", "ch7",
337 "ch8", "ch9", "ch10", "ch11",
338 "ch12";
339 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>;
340 clock-names = "fck";
341 #dma-cells = <1>;
342 dma-channels = <13>;
343 };
344
345 audma1: dma-controller@ec720000 {
346 compatible = "renesas,rcar-dmac";
347 reg = <0 0xec720000 0 0x10000>;
348 interrupts = <0 347 IRQ_TYPE_LEVEL_HIGH
349 0 333 IRQ_TYPE_LEVEL_HIGH
350 0 334 IRQ_TYPE_LEVEL_HIGH
351 0 335 IRQ_TYPE_LEVEL_HIGH
352 0 336 IRQ_TYPE_LEVEL_HIGH
353 0 337 IRQ_TYPE_LEVEL_HIGH
354 0 338 IRQ_TYPE_LEVEL_HIGH
355 0 339 IRQ_TYPE_LEVEL_HIGH
356 0 340 IRQ_TYPE_LEVEL_HIGH
357 0 341 IRQ_TYPE_LEVEL_HIGH
358 0 342 IRQ_TYPE_LEVEL_HIGH
359 0 343 IRQ_TYPE_LEVEL_HIGH
360 0 344 IRQ_TYPE_LEVEL_HIGH
361 0 345 IRQ_TYPE_LEVEL_HIGH>;
362 interrupt-names = "error",
363 "ch0", "ch1", "ch2", "ch3",
364 "ch4", "ch5", "ch6", "ch7",
365 "ch8", "ch9", "ch10", "ch11",
366 "ch12";
367 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>;
368 clock-names = "fck";
369 #dma-cells = <1>;
370 dma-channels = <13>;
371 };
372
373 audmapp: dma-controller@ec740000 {
374 compatible = "renesas,rcar-audmapp";
375 #dma-cells = <1>;
376
377 reg = <0 0xec740000 0 0x200>;
378 };
379
380 i2c0: i2c@e6508000 {
381 #address-cells = <1>;
382 #size-cells = <0>;
383 compatible = "renesas,i2c-r8a7790";
384 reg = <0 0xe6508000 0 0x40>;
385 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
386 clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
387 status = "disabled";
388 };
389
390 i2c1: i2c@e6518000 {
391 #address-cells = <1>;
392 #size-cells = <0>;
393 compatible = "renesas,i2c-r8a7790";
394 reg = <0 0xe6518000 0 0x40>;
395 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
396 clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
397 status = "disabled";
398 };
399
400 i2c2: i2c@e6530000 {
401 #address-cells = <1>;
402 #size-cells = <0>;
403 compatible = "renesas,i2c-r8a7790";
404 reg = <0 0xe6530000 0 0x40>;
405 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
407 status = "disabled";
408 };
409
410 i2c3: i2c@e6540000 {
411 #address-cells = <1>;
412 #size-cells = <0>;
413 compatible = "renesas,i2c-r8a7790";
414 reg = <0 0xe6540000 0 0x40>;
415 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
416 clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
417 status = "disabled";
418 };
419
420 iic0: i2c@e6500000 {
421 #address-cells = <1>;
422 #size-cells = <0>;
423 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
424 reg = <0 0xe6500000 0 0x425>;
425 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
426 clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
427 dmas = <&dmac0 0x61>, <&dmac0 0x62>;
428 dma-names = "tx", "rx";
429 status = "disabled";
430 };
431
432 iic1: i2c@e6510000 {
433 #address-cells = <1>;
434 #size-cells = <0>;
435 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
436 reg = <0 0xe6510000 0 0x425>;
437 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
438 clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
439 dmas = <&dmac0 0x65>, <&dmac0 0x66>;
440 dma-names = "tx", "rx";
441 status = "disabled";
442 };
443
444 iic2: i2c@e6520000 {
445 #address-cells = <1>;
446 #size-cells = <0>;
447 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
448 reg = <0 0xe6520000 0 0x425>;
449 interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>;
450 clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
451 dmas = <&dmac0 0x69>, <&dmac0 0x6a>;
452 dma-names = "tx", "rx";
453 status = "disabled";
454 };
455
456 iic3: i2c@e60b0000 {
457 #address-cells = <1>;
458 #size-cells = <0>;
459 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
460 reg = <0 0xe60b0000 0 0x425>;
461 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
462 clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
463 dmas = <&dmac0 0x77>, <&dmac0 0x78>;
464 dma-names = "tx", "rx";
465 status = "disabled";
466 };
467
468 mmcif0: mmc@ee200000 {
469 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
470 reg = <0 0xee200000 0 0x80>;
471 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
473 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
474 dma-names = "tx", "rx";
475 reg-io-width = <4>;
476 status = "disabled";
477 };
478
479 mmcif1: mmc@ee220000 {
480 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
481 reg = <0 0xee220000 0 0x80>;
482 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
483 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
484 dmas = <&dmac0 0xe1>, <&dmac0 0xe2>;
485 dma-names = "tx", "rx";
486 reg-io-width = <4>;
487 status = "disabled";
488 };
489
490 pfc: pfc@e6060000 {
491 compatible = "renesas,pfc-r8a7790";
492 reg = <0 0xe6060000 0 0x250>;
493 };
494
495 sdhi0: sd@ee100000 {
496 compatible = "renesas,sdhi-r8a7790";
497 reg = <0 0xee100000 0 0x328>;
498 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
499 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
500 dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
501 dma-names = "tx", "rx";
502 status = "disabled";
503 };
504
505 sdhi1: sd@ee120000 {
506 compatible = "renesas,sdhi-r8a7790";
507 reg = <0 0xee120000 0 0x328>;
508 interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
509 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
510 dmas = <&dmac1 0xc9>, <&dmac1 0xca>;
511 dma-names = "tx", "rx";
512 status = "disabled";
513 };
514
515 sdhi2: sd@ee140000 {
516 compatible = "renesas,sdhi-r8a7790";
517 reg = <0 0xee140000 0 0x100>;
518 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
519 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
520 dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
521 dma-names = "tx", "rx";
522 status = "disabled";
523 };
524
525 sdhi3: sd@ee160000 {
526 compatible = "renesas,sdhi-r8a7790";
527 reg = <0 0xee160000 0 0x100>;
528 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
529 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
530 dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
531 dma-names = "tx", "rx";
532 status = "disabled";
533 };
534
535 scifa0: serial@e6c40000 {
536 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
537 reg = <0 0xe6c40000 0 64>;
538 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
539 clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
540 clock-names = "sci_ick";
541 status = "disabled";
542 };
543
544 scifa1: serial@e6c50000 {
545 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
546 reg = <0 0xe6c50000 0 64>;
547 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
548 clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>;
549 clock-names = "sci_ick";
550 status = "disabled";
551 };
552
553 scifa2: serial@e6c60000 {
554 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
555 reg = <0 0xe6c60000 0 64>;
556 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
557 clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>;
558 clock-names = "sci_ick";
559 status = "disabled";
560 };
561
562 scifb0: serial@e6c20000 {
563 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
564 reg = <0 0xe6c20000 0 64>;
565 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
566 clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>;
567 clock-names = "sci_ick";
568 status = "disabled";
569 };
570
571 scifb1: serial@e6c30000 {
572 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
573 reg = <0 0xe6c30000 0 64>;
574 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
575 clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>;
576 clock-names = "sci_ick";
577 status = "disabled";
578 };
579
580 scifb2: serial@e6ce0000 {
581 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
582 reg = <0 0xe6ce0000 0 64>;
583 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
584 clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>;
585 clock-names = "sci_ick";
586 status = "disabled";
587 };
588
589 scif0: serial@e6e60000 {
590 compatible = "renesas,scif-r8a7790", "renesas,scif";
591 reg = <0 0xe6e60000 0 64>;
592 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
593 clocks = <&mstp7_clks R8A7790_CLK_SCIF0>;
594 clock-names = "sci_ick";
595 status = "disabled";
596 };
597
598 scif1: serial@e6e68000 {
599 compatible = "renesas,scif-r8a7790", "renesas,scif";
600 reg = <0 0xe6e68000 0 64>;
601 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
602 clocks = <&mstp7_clks R8A7790_CLK_SCIF1>;
603 clock-names = "sci_ick";
604 status = "disabled";
605 };
606
607 hscif0: serial@e62c0000 {
608 compatible = "renesas,hscif-r8a7790", "renesas,hscif";
609 reg = <0 0xe62c0000 0 96>;
610 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
611 clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>;
612 clock-names = "sci_ick";
613 status = "disabled";
614 };
615
616 hscif1: serial@e62c8000 {
617 compatible = "renesas,hscif-r8a7790", "renesas,hscif";
618 reg = <0 0xe62c8000 0 96>;
619 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
620 clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>;
621 clock-names = "sci_ick";
622 status = "disabled";
623 };
624
625 ether: ethernet@ee700000 {
626 compatible = "renesas,ether-r8a7790";
627 reg = <0 0xee700000 0 0x400>;
628 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
629 clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
630 phy-mode = "rmii";
631 #address-cells = <1>;
632 #size-cells = <0>;
633 status = "disabled";
634 };
635
636 sata0: sata@ee300000 {
637 compatible = "renesas,sata-r8a7790";
638 reg = <0 0xee300000 0 0x2000>;
639 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
640 clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
641 status = "disabled";
642 };
643
644 sata1: sata@ee500000 {
645 compatible = "renesas,sata-r8a7790";
646 reg = <0 0xee500000 0 0x2000>;
647 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
648 clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
649 status = "disabled";
650 };
651
652 hsusb: usb@e6590000 {
653 compatible = "renesas,usbhs-r8a7790";
654 reg = <0 0xe6590000 0 0x100>;
655 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
656 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
657 renesas,buswait = <4>;
658 phys = <&usb0 1>;
659 phy-names = "usb";
660 status = "disabled";
661 };
662
663 usbphy: usb-phy@e6590100 {
664 compatible = "renesas,usb-phy-r8a7790";
665 reg = <0 0xe6590100 0 0x100>;
666 #address-cells = <1>;
667 #size-cells = <0>;
668 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
669 clock-names = "usbhs";
670 status = "disabled";
671
672 usb0: usb-channel@0 {
673 reg = <0>;
674 #phy-cells = <1>;
675 };
676 usb2: usb-channel@2 {
677 reg = <2>;
678 #phy-cells = <1>;
679 };
680 };
681
682 vin0: video@e6ef0000 {
683 compatible = "renesas,vin-r8a7790";
684 clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
685 reg = <0 0xe6ef0000 0 0x1000>;
686 interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
687 status = "disabled";
688 };
689
690 vin1: video@e6ef1000 {
691 compatible = "renesas,vin-r8a7790";
692 clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
693 reg = <0 0xe6ef1000 0 0x1000>;
694 interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
695 status = "disabled";
696 };
697
698 vin2: video@e6ef2000 {
699 compatible = "renesas,vin-r8a7790";
700 clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
701 reg = <0 0xe6ef2000 0 0x1000>;
702 interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>;
703 status = "disabled";
704 };
705
706 vin3: video@e6ef3000 {
707 compatible = "renesas,vin-r8a7790";
708 clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
709 reg = <0 0xe6ef3000 0 0x1000>;
710 interrupts = <0 191 IRQ_TYPE_LEVEL_HIGH>;
711 status = "disabled";
712 };
713
714 vsp1@fe920000 {
715 compatible = "renesas,vsp1";
716 reg = <0 0xfe920000 0 0x8000>;
717 interrupts = <0 266 IRQ_TYPE_LEVEL_HIGH>;
718 clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>;
719
720 renesas,has-sru;
721 renesas,#rpf = <5>;
722 renesas,#uds = <1>;
723 renesas,#wpf = <4>;
724 };
725
726 vsp1@fe928000 {
727 compatible = "renesas,vsp1";
728 reg = <0 0xfe928000 0 0x8000>;
729 interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>;
730 clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>;
731
732 renesas,has-lut;
733 renesas,has-sru;
734 renesas,#rpf = <5>;
735 renesas,#uds = <3>;
736 renesas,#wpf = <4>;
737 };
738
739 vsp1@fe930000 {
740 compatible = "renesas,vsp1";
741 reg = <0 0xfe930000 0 0x8000>;
742 interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>;
743 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>;
744
745 renesas,has-lif;
746 renesas,has-lut;
747 renesas,#rpf = <4>;
748 renesas,#uds = <1>;
749 renesas,#wpf = <4>;
750 };
751
752 vsp1@fe938000 {
753 compatible = "renesas,vsp1";
754 reg = <0 0xfe938000 0 0x8000>;
755 interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>;
756 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>;
757
758 renesas,has-lif;
759 renesas,has-lut;
760 renesas,#rpf = <4>;
761 renesas,#uds = <1>;
762 renesas,#wpf = <4>;
763 };
764
765 du: display@feb00000 {
766 compatible = "renesas,du-r8a7790";
767 reg = <0 0xfeb00000 0 0x70000>,
768 <0 0xfeb90000 0 0x1c>,
769 <0 0xfeb94000 0 0x1c>;
770 reg-names = "du", "lvds.0", "lvds.1";
771 interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
772 <0 268 IRQ_TYPE_LEVEL_HIGH>,
773 <0 269 IRQ_TYPE_LEVEL_HIGH>;
774 clocks = <&mstp7_clks R8A7790_CLK_DU0>,
775 <&mstp7_clks R8A7790_CLK_DU1>,
776 <&mstp7_clks R8A7790_CLK_DU2>,
777 <&mstp7_clks R8A7790_CLK_LVDS0>,
778 <&mstp7_clks R8A7790_CLK_LVDS1>;
779 clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
780 status = "disabled";
781
782 ports {
783 #address-cells = <1>;
784 #size-cells = <0>;
785
786 port@0 {
787 reg = <0>;
788 du_out_rgb: endpoint {
789 };
790 };
791 port@1 {
792 reg = <1>;
793 du_out_lvds0: endpoint {
794 };
795 };
796 port@2 {
797 reg = <2>;
798 du_out_lvds1: endpoint {
799 };
800 };
801 };
802 };
803
804 can0: can@e6e80000 {
805 compatible = "renesas,can-r8a7790";
806 reg = <0 0xe6e80000 0 0x1000>;
807 interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>;
808 clocks = <&mstp9_clks R8A7790_CLK_RCAN0>,
809 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
810 clock-names = "clkp1", "clkp2", "can_clk";
811 status = "disabled";
812 };
813
814 can1: can@e6e88000 {
815 compatible = "renesas,can-r8a7790";
816 reg = <0 0xe6e88000 0 0x1000>;
817 interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH>;
818 clocks = <&mstp9_clks R8A7790_CLK_RCAN1>,
819 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
820 clock-names = "clkp1", "clkp2", "can_clk";
821 status = "disabled";
822 };
823
824 clocks {
825 #address-cells = <2>;
826 #size-cells = <2>;
827 ranges;
828
829 /* External root clock */
830 extal_clk: extal_clk {
831 compatible = "fixed-clock";
832 #clock-cells = <0>;
833 /* This value must be overriden by the board. */
834 clock-frequency = <0>;
835 clock-output-names = "extal";
836 };
837
838 /* External PCIe clock - can be overridden by the board */
839 pcie_bus_clk: pcie_bus_clk {
840 compatible = "fixed-clock";
841 #clock-cells = <0>;
842 clock-frequency = <100000000>;
843 clock-output-names = "pcie_bus";
844 status = "disabled";
845 };
846
847 /*
848 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
849 * default. Boards that provide audio clocks should override them.
850 */
851 audio_clk_a: audio_clk_a {
852 compatible = "fixed-clock";
853 #clock-cells = <0>;
854 clock-frequency = <0>;
855 clock-output-names = "audio_clk_a";
856 };
857 audio_clk_b: audio_clk_b {
858 compatible = "fixed-clock";
859 #clock-cells = <0>;
860 clock-frequency = <0>;
861 clock-output-names = "audio_clk_b";
862 };
863 audio_clk_c: audio_clk_c {
864 compatible = "fixed-clock";
865 #clock-cells = <0>;
866 clock-frequency = <0>;
867 clock-output-names = "audio_clk_c";
868 };
869
870 /* External USB clock - can be overridden by the board */
871 usb_extal_clk: usb_extal_clk {
872 compatible = "fixed-clock";
873 #clock-cells = <0>;
874 clock-frequency = <48000000>;
875 clock-output-names = "usb_extal";
876 };
877
878 /* External CAN clock */
879 can_clk: can_clk {
880 compatible = "fixed-clock";
881 #clock-cells = <0>;
882 /* This value must be overridden by the board. */
883 clock-frequency = <0>;
884 clock-output-names = "can_clk";
885 status = "disabled";
886 };
887
888 /* Special CPG clocks */
889 cpg_clocks: cpg_clocks@e6150000 {
890 compatible = "renesas,r8a7790-cpg-clocks",
891 "renesas,rcar-gen2-cpg-clocks";
892 reg = <0 0xe6150000 0 0x1000>;
893 clocks = <&extal_clk &usb_extal_clk>;
894 #clock-cells = <1>;
895 clock-output-names = "main", "pll0", "pll1", "pll3",
896 "lb", "qspi", "sdh", "sd0", "sd1",
897 "z", "rcan", "adsp";
898 };
899
900 /* Variable factor clocks */
901 sd2_clk: sd2_clk@e6150078 {
902 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
903 reg = <0 0xe6150078 0 4>;
904 clocks = <&pll1_div2_clk>;
905 #clock-cells = <0>;
906 clock-output-names = "sd2";
907 };
908 sd3_clk: sd3_clk@e615026c {
909 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
910 reg = <0 0xe615026c 0 4>;
911 clocks = <&pll1_div2_clk>;
912 #clock-cells = <0>;
913 clock-output-names = "sd3";
914 };
915 mmc0_clk: mmc0_clk@e6150240 {
916 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
917 reg = <0 0xe6150240 0 4>;
918 clocks = <&pll1_div2_clk>;
919 #clock-cells = <0>;
920 clock-output-names = "mmc0";
921 };
922 mmc1_clk: mmc1_clk@e6150244 {
923 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
924 reg = <0 0xe6150244 0 4>;
925 clocks = <&pll1_div2_clk>;
926 #clock-cells = <0>;
927 clock-output-names = "mmc1";
928 };
929 ssp_clk: ssp_clk@e6150248 {
930 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
931 reg = <0 0xe6150248 0 4>;
932 clocks = <&pll1_div2_clk>;
933 #clock-cells = <0>;
934 clock-output-names = "ssp";
935 };
936 ssprs_clk: ssprs_clk@e615024c {
937 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
938 reg = <0 0xe615024c 0 4>;
939 clocks = <&pll1_div2_clk>;
940 #clock-cells = <0>;
941 clock-output-names = "ssprs";
942 };
943
944 /* Fixed factor clocks */
945 pll1_div2_clk: pll1_div2_clk {
946 compatible = "fixed-factor-clock";
947 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
948 #clock-cells = <0>;
949 clock-div = <2>;
950 clock-mult = <1>;
951 clock-output-names = "pll1_div2";
952 };
953 z2_clk: z2_clk {
954 compatible = "fixed-factor-clock";
955 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
956 #clock-cells = <0>;
957 clock-div = <2>;
958 clock-mult = <1>;
959 clock-output-names = "z2";
960 };
961 zg_clk: zg_clk {
962 compatible = "fixed-factor-clock";
963 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
964 #clock-cells = <0>;
965 clock-div = <3>;
966 clock-mult = <1>;
967 clock-output-names = "zg";
968 };
969 zx_clk: zx_clk {
970 compatible = "fixed-factor-clock";
971 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
972 #clock-cells = <0>;
973 clock-div = <3>;
974 clock-mult = <1>;
975 clock-output-names = "zx";
976 };
977 zs_clk: zs_clk {
978 compatible = "fixed-factor-clock";
979 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
980 #clock-cells = <0>;
981 clock-div = <6>;
982 clock-mult = <1>;
983 clock-output-names = "zs";
984 };
985 hp_clk: hp_clk {
986 compatible = "fixed-factor-clock";
987 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
988 #clock-cells = <0>;
989 clock-div = <12>;
990 clock-mult = <1>;
991 clock-output-names = "hp";
992 };
993 i_clk: i_clk {
994 compatible = "fixed-factor-clock";
995 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
996 #clock-cells = <0>;
997 clock-div = <2>;
998 clock-mult = <1>;
999 clock-output-names = "i";
1000 };
1001 b_clk: b_clk {
1002 compatible = "fixed-factor-clock";
1003 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1004 #clock-cells = <0>;
1005 clock-div = <12>;
1006 clock-mult = <1>;
1007 clock-output-names = "b";
1008 };
1009 p_clk: p_clk {
1010 compatible = "fixed-factor-clock";
1011 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1012 #clock-cells = <0>;
1013 clock-div = <24>;
1014 clock-mult = <1>;
1015 clock-output-names = "p";
1016 };
1017 cl_clk: cl_clk {
1018 compatible = "fixed-factor-clock";
1019 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1020 #clock-cells = <0>;
1021 clock-div = <48>;
1022 clock-mult = <1>;
1023 clock-output-names = "cl";
1024 };
1025 m2_clk: m2_clk {
1026 compatible = "fixed-factor-clock";
1027 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1028 #clock-cells = <0>;
1029 clock-div = <8>;
1030 clock-mult = <1>;
1031 clock-output-names = "m2";
1032 };
1033 imp_clk: imp_clk {
1034 compatible = "fixed-factor-clock";
1035 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1036 #clock-cells = <0>;
1037 clock-div = <4>;
1038 clock-mult = <1>;
1039 clock-output-names = "imp";
1040 };
1041 rclk_clk: rclk_clk {
1042 compatible = "fixed-factor-clock";
1043 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1044 #clock-cells = <0>;
1045 clock-div = <(48 * 1024)>;
1046 clock-mult = <1>;
1047 clock-output-names = "rclk";
1048 };
1049 oscclk_clk: oscclk_clk {
1050 compatible = "fixed-factor-clock";
1051 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1052 #clock-cells = <0>;
1053 clock-div = <(12 * 1024)>;
1054 clock-mult = <1>;
1055 clock-output-names = "oscclk";
1056 };
1057 zb3_clk: zb3_clk {
1058 compatible = "fixed-factor-clock";
1059 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1060 #clock-cells = <0>;
1061 clock-div = <4>;
1062 clock-mult = <1>;
1063 clock-output-names = "zb3";
1064 };
1065 zb3d2_clk: zb3d2_clk {
1066 compatible = "fixed-factor-clock";
1067 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1068 #clock-cells = <0>;
1069 clock-div = <8>;
1070 clock-mult = <1>;
1071 clock-output-names = "zb3d2";
1072 };
1073 ddr_clk: ddr_clk {
1074 compatible = "fixed-factor-clock";
1075 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1076 #clock-cells = <0>;
1077 clock-div = <8>;
1078 clock-mult = <1>;
1079 clock-output-names = "ddr";
1080 };
1081 mp_clk: mp_clk {
1082 compatible = "fixed-factor-clock";
1083 clocks = <&pll1_div2_clk>;
1084 #clock-cells = <0>;
1085 clock-div = <15>;
1086 clock-mult = <1>;
1087 clock-output-names = "mp";
1088 };
1089 cp_clk: cp_clk {
1090 compatible = "fixed-factor-clock";
1091 clocks = <&extal_clk>;
1092 #clock-cells = <0>;
1093 clock-div = <2>;
1094 clock-mult = <1>;
1095 clock-output-names = "cp";
1096 };
1097
1098 /* Gate clocks */
1099 mstp0_clks: mstp0_clks@e6150130 {
1100 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1101 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1102 clocks = <&mp_clk>;
1103 #clock-cells = <1>;
1104 clock-indices = <R8A7790_CLK_MSIOF0>;
1105 clock-output-names = "msiof0";
1106 };
1107 mstp1_clks: mstp1_clks@e6150134 {
1108 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1109 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1110 clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&m2_clk>,
1111 <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, <&zs_clk>,
1112 <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
1113 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
1114 #clock-cells = <1>;
1115 clock-indices = <
1116 R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1
1117 R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1
1118 R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC
1119 R8A7790_CLK_FDP1_2 R8A7790_CLK_FDP1_1 R8A7790_CLK_FDP1_0
1120 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 R8A7790_CLK_CMT0
1121 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 R8A7790_CLK_VSP1_DU0
1122 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
1123 >;
1124 clock-output-names =
1125 "vcp1", "vcp0", "vpc1", "vpc0", "jpu", "ssp1",
1126 "tmu1", "3dg", "2ddmac", "fdp1-2", "fdp1-1",
1127 "fdp1-0", "tmu3", "tmu2", "cmt0", "tmu0",
1128 "vsp1-du1", "vsp1-du0", "vsp1-rt", "vsp1-sy";
1129 };
1130 mstp2_clks: mstp2_clks@e6150138 {
1131 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1132 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1133 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1134 <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>,
1135 <&zs_clk>;
1136 #clock-cells = <1>;
1137 clock-indices = <
1138 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
1139 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
1140 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
1141 R8A7790_CLK_SYS_DMAC1 R8A7790_CLK_SYS_DMAC0
1142 >;
1143 clock-output-names =
1144 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
1145 "scifb1", "msiof1", "msiof3", "scifb2",
1146 "sys-dmac1", "sys-dmac0";
1147 };
1148 mstp3_clks: mstp3_clks@e615013c {
1149 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1150 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1151 clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>,
1152 <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
1153 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1154 <&hp_clk>, <&hp_clk>;
1155 #clock-cells = <1>;
1156 clock-indices = <
1157 R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
1158 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
1159 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
1160 R8A7790_CLK_USBDMAC0 R8A7790_CLK_USBDMAC1
1161 >;
1162 clock-output-names =
1163 "iic2", "tpu0", "mmcif1", "sdhi3",
1164 "sdhi2", "sdhi1", "sdhi0", "mmcif0",
1165 "iic0", "pciec", "iic1", "ssusb", "cmt1",
1166 "usbdmac0", "usbdmac1";
1167 };
1168 mstp5_clks: mstp5_clks@e6150144 {
1169 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1170 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1171 clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7790_CLK_ADSP>,
1172 <&extal_clk>, <&p_clk>;
1173 #clock-cells = <1>;
1174 clock-indices = <
1175 R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1
1176 R8A7790_CLK_ADSP_MOD R8A7790_CLK_THERMAL
1177 R8A7790_CLK_PWM
1178 >;
1179 clock-output-names = "audmac0", "audmac1", "adsp_mod",
1180 "thermal", "pwm";
1181 };
1182 mstp7_clks: mstp7_clks@e615014c {
1183 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1184 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1185 clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1186 <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
1187 <&zx_clk>;
1188 #clock-cells = <1>;
1189 clock-indices = <
1190 R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
1191 R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
1192 R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
1193 R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0
1194 >;
1195 clock-output-names =
1196 "ehci", "hsusb", "hscif1", "hscif0", "scif1",
1197 "scif0", "du2", "du1", "du0", "lvds1", "lvds0";
1198 };
1199 mstp8_clks: mstp8_clks@e6150990 {
1200 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1201 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1202 clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
1203 <&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>;
1204 #clock-cells = <1>;
1205 clock-indices = <
1206 R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2
1207 R8A7790_CLK_VIN1 R8A7790_CLK_VIN0 R8A7790_CLK_ETHER
1208 R8A7790_CLK_SATA1 R8A7790_CLK_SATA0
1209 >;
1210 clock-output-names =
1211 "mlb", "vin3", "vin2", "vin1", "vin0", "ether",
1212 "sata1", "sata0";
1213 };
1214 mstp9_clks: mstp9_clks@e6150994 {
1215 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1216 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1217 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>,
1218 <&cp_clk>, <&cp_clk>, <&cp_clk>,
1219 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>,
1220 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
1221 #clock-cells = <1>;
1222 clock-indices = <
1223 R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3
1224 R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0
1225 R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS
1226 R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0
1227 >;
1228 clock-output-names =
1229 "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
1230 "rcan1", "rcan0", "qspi_mod", "iic3",
1231 "i2c3", "i2c2", "i2c1", "i2c0";
1232 };
1233 mstp10_clks: mstp10_clks@e6150998 {
1234 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1235 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1236 clocks = <&p_clk>,
1237 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1238 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1239 <&p_clk>,
1240 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1241 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1242 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1243 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1244 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1245 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>;
1246
1247 #clock-cells = <1>;
1248 clock-indices = <
1249 R8A7790_CLK_SSI_ALL
1250 R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5
1251 R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0
1252 R8A7790_CLK_SCU_ALL
1253 R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0
1254 R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5
1255 R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0
1256 >;
1257 clock-output-names =
1258 "ssi-all",
1259 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1260 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1261 "scu-all",
1262 "scu-dvc1", "scu-dvc0",
1263 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1264 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1265 };
1266 };
1267
1268 qspi: spi@e6b10000 {
1269 compatible = "renesas,qspi-r8a7790", "renesas,qspi";
1270 reg = <0 0xe6b10000 0 0x2c>;
1271 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
1272 clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
1273 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
1274 dma-names = "tx", "rx";
1275 num-cs = <1>;
1276 #address-cells = <1>;
1277 #size-cells = <0>;
1278 status = "disabled";
1279 };
1280
1281 msiof0: spi@e6e20000 {
1282 compatible = "renesas,msiof-r8a7790";
1283 reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>;
1284 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
1285 clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
1286 dmas = <&dmac0 0x51>, <&dmac0 0x52>;
1287 dma-names = "tx", "rx";
1288 #address-cells = <1>;
1289 #size-cells = <0>;
1290 status = "disabled";
1291 };
1292
1293 msiof1: spi@e6e10000 {
1294 compatible = "renesas,msiof-r8a7790";
1295 reg = <0 0xe6e10000 0 0x0064>, <0 0xe7e10000 0 0x0064>;
1296 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
1297 clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
1298 dmas = <&dmac0 0x55>, <&dmac0 0x56>;
1299 dma-names = "tx", "rx";
1300 #address-cells = <1>;
1301 #size-cells = <0>;
1302 status = "disabled";
1303 };
1304
1305 msiof2: spi@e6e00000 {
1306 compatible = "renesas,msiof-r8a7790";
1307 reg = <0 0xe6e00000 0 0x0064>, <0 0xe7e00000 0 0x0064>;
1308 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
1309 clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
1310 dmas = <&dmac0 0x41>, <&dmac0 0x42>;
1311 dma-names = "tx", "rx";
1312 #address-cells = <1>;
1313 #size-cells = <0>;
1314 status = "disabled";
1315 };
1316
1317 msiof3: spi@e6c90000 {
1318 compatible = "renesas,msiof-r8a7790";
1319 reg = <0 0xe6c90000 0 0x0064>, <0 0xe7c90000 0 0x0064>;
1320 interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>;
1321 clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
1322 dmas = <&dmac0 0x45>, <&dmac0 0x46>;
1323 dma-names = "tx", "rx";
1324 #address-cells = <1>;
1325 #size-cells = <0>;
1326 status = "disabled";
1327 };
1328
1329 xhci: usb@ee000000 {
1330 compatible = "renesas,xhci-r8a7790";
1331 reg = <0 0xee000000 0 0xc00>;
1332 interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
1333 clocks = <&mstp3_clks R8A7790_CLK_SSUSB>;
1334 phys = <&usb2 1>;
1335 phy-names = "usb";
1336 status = "disabled";
1337 };
1338
1339 pci0: pci@ee090000 {
1340 compatible = "renesas,pci-r8a7790";
1341 device_type = "pci";
1342 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1343 reg = <0 0xee090000 0 0xc00>,
1344 <0 0xee080000 0 0x1100>;
1345 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1346 status = "disabled";
1347
1348 bus-range = <0 0>;
1349 #address-cells = <3>;
1350 #size-cells = <2>;
1351 #interrupt-cells = <1>;
1352 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1353 interrupt-map-mask = <0xff00 0 0 0x7>;
1354 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1355 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1356 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
1357
1358 usb@0,1 {
1359 reg = <0x800 0 0 0 0>;
1360 device_type = "pci";
1361 phys = <&usb0 0>;
1362 phy-names = "usb";
1363 };
1364
1365 usb@0,2 {
1366 reg = <0x1000 0 0 0 0>;
1367 device_type = "pci";
1368 phys = <&usb0 0>;
1369 phy-names = "usb";
1370 };
1371 };
1372
1373 pci1: pci@ee0b0000 {
1374 compatible = "renesas,pci-r8a7790";
1375 device_type = "pci";
1376 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1377 reg = <0 0xee0b0000 0 0xc00>,
1378 <0 0xee0a0000 0 0x1100>;
1379 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
1380 status = "disabled";
1381
1382 bus-range = <1 1>;
1383 #address-cells = <3>;
1384 #size-cells = <2>;
1385 #interrupt-cells = <1>;
1386 ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
1387 interrupt-map-mask = <0xff00 0 0 0x7>;
1388 interrupt-map = <0x0000 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH
1389 0x0800 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH
1390 0x1000 0 0 2 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>;
1391 };
1392
1393 pci2: pci@ee0d0000 {
1394 compatible = "renesas,pci-r8a7790";
1395 device_type = "pci";
1396 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1397 reg = <0 0xee0d0000 0 0xc00>,
1398 <0 0xee0c0000 0 0x1100>;
1399 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
1400 status = "disabled";
1401
1402 bus-range = <2 2>;
1403 #address-cells = <3>;
1404 #size-cells = <2>;
1405 #interrupt-cells = <1>;
1406 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1407 interrupt-map-mask = <0xff00 0 0 0x7>;
1408 interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1409 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1410 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
1411
1412 usb@0,1 {
1413 reg = <0x800 0 0 0 0>;
1414 device_type = "pci";
1415 phys = <&usb2 0>;
1416 phy-names = "usb";
1417 };
1418
1419 usb@0,2 {
1420 reg = <0x1000 0 0 0 0>;
1421 device_type = "pci";
1422 phys = <&usb2 0>;
1423 phy-names = "usb";
1424 };
1425 };
1426
1427 pciec: pcie@fe000000 {
1428 compatible = "renesas,pcie-r8a7790";
1429 reg = <0 0xfe000000 0 0x80000>;
1430 #address-cells = <3>;
1431 #size-cells = <2>;
1432 bus-range = <0x00 0xff>;
1433 device_type = "pci";
1434 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1435 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1436 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1437 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1438 /* Map all possible DDR as inbound ranges */
1439 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1440 0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
1441 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>,
1442 <0 117 IRQ_TYPE_LEVEL_HIGH>,
1443 <0 118 IRQ_TYPE_LEVEL_HIGH>;
1444 #interrupt-cells = <1>;
1445 interrupt-map-mask = <0 0 0 0>;
1446 interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
1447 clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>;
1448 clock-names = "pcie", "pcie_bus";
1449 status = "disabled";
1450 };
1451
1452 rcar_sound: rcar_sound@ec500000 {
1453 /*
1454 * #sound-dai-cells is required
1455 *
1456 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1457 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1458 */
1459 compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2";
1460 reg = <0 0xec500000 0 0x1000>, /* SCU */
1461 <0 0xec5a0000 0 0x100>, /* ADG */
1462 <0 0xec540000 0 0x1000>, /* SSIU */
1463 <0 0xec541000 0 0x1280>; /* SSI */
1464 clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>,
1465 <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>,
1466 <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>,
1467 <&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>,
1468 <&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>,
1469 <&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>,
1470 <&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>,
1471 <&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>,
1472 <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>,
1473 <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>,
1474 <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>,
1475 <&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>,
1476 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1477 clock-names = "ssi-all",
1478 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1479 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1480 "src.9", "src.8", "src.7", "src.6", "src.5",
1481 "src.4", "src.3", "src.2", "src.1", "src.0",
1482 "dvc.0", "dvc.1",
1483 "clk_a", "clk_b", "clk_c", "clk_i";
1484
1485 status = "disabled";
1486
1487 rcar_sound,dvc {
1488 dvc0: dvc@0 { };
1489 dvc1: dvc@1 { };
1490 };
1491
1492 rcar_sound,src {
1493 src0: src@0 { interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>; };
1494 src1: src@1 { interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>; };
1495 src2: src@2 { interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>; };
1496 src3: src@3 { interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>; };
1497 src4: src@4 { interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>; };
1498 src5: src@5 { interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>; };
1499 src6: src@6 { interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>; };
1500 src7: src@7 { interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>; };
1501 src8: src@8 { interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>; };
1502 src9: src@9 { interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>; };
1503 };
1504
1505 rcar_sound,ssi {
1506 ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; };
1507 ssi1: ssi@1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; };
1508 ssi2: ssi@2 { interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; };
1509 ssi3: ssi@3 { interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; };
1510 ssi4: ssi@4 { interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; };
1511 ssi5: ssi@5 { interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; };
1512 ssi6: ssi@6 { interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; };
1513 ssi7: ssi@7 { interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; };
1514 ssi8: ssi@8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; };
1515 ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; };
1516 };
1517 };
1518
1519 ipmmu_sy0: mmu@e6280000 {
1520 compatible = "renesas,ipmmu-vmsa";
1521 reg = <0 0xe6280000 0 0x1000>;
1522 interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>,
1523 <0 224 IRQ_TYPE_LEVEL_HIGH>;
1524 #iommu-cells = <1>;
1525 status = "disabled";
1526 };
1527
1528 ipmmu_sy1: mmu@e6290000 {
1529 compatible = "renesas,ipmmu-vmsa";
1530 reg = <0 0xe6290000 0 0x1000>;
1531 interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
1532 #iommu-cells = <1>;
1533 status = "disabled";
1534 };
1535
1536 ipmmu_ds: mmu@e6740000 {
1537 compatible = "renesas,ipmmu-vmsa";
1538 reg = <0 0xe6740000 0 0x1000>;
1539 interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
1540 <0 199 IRQ_TYPE_LEVEL_HIGH>;
1541 #iommu-cells = <1>;
1542 status = "disabled";
1543 };
1544
1545 ipmmu_mp: mmu@ec680000 {
1546 compatible = "renesas,ipmmu-vmsa";
1547 reg = <0 0xec680000 0 0x1000>;
1548 interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
1549 #iommu-cells = <1>;
1550 status = "disabled";
1551 };
1552
1553 ipmmu_mx: mmu@fe951000 {
1554 compatible = "renesas,ipmmu-vmsa";
1555 reg = <0 0xfe951000 0 0x1000>;
1556 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
1557 <0 221 IRQ_TYPE_LEVEL_HIGH>;
1558 #iommu-cells = <1>;
1559 status = "disabled";
1560 };
1561
1562 ipmmu_rt: mmu@ffc80000 {
1563 compatible = "renesas,ipmmu-vmsa";
1564 reg = <0 0xffc80000 0 0x1000>;
1565 interrupts = <0 307 IRQ_TYPE_LEVEL_HIGH>;
1566 #iommu-cells = <1>;
1567 status = "disabled";
1568 };
1569 };
Linux kernel - Deliverables
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